Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Fitipower FC0013 tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * partially based on driver code from Fitipower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2010 Fitipower Integrated Technology Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "fc0013.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "fc0013-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) static int fc0013_writereg(struct fc0013_priv *priv, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	u8 buf[2] = {reg, val};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 		.addr = priv->addr, .flags = 0, .buf = buf, .len = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		err("I2C write reg failed, reg: %02x, val: %02x", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static int fc0013_readreg(struct fc0013_priv *priv, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct i2c_msg msg[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		{ .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		{ .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	if (i2c_transfer(priv->i2c, msg, 2) != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		err("I2C read reg failed, reg: %02x", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static void fc0013_release(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	kfree(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	fe->tuner_priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static int fc0013_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct fc0013_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned char reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		0x00,	/* reg. 0x00: dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		0x09,	/* reg. 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		0x16,	/* reg. 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		0x00,	/* reg. 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		0x00,	/* reg. 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		0x17,	/* reg. 0x05 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		0x02,	/* reg. 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		0x0a,	/* reg. 0x07: CHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		0xff,	/* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			   Loop Bw 1/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		0x6f,	/* reg. 0x09: enable LoopThrough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		0xb8,	/* reg. 0x0a: Disable LO Test Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		0x82,	/* reg. 0x0b: CHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		0xfc,	/* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		0x01,	/* reg. 0x0d: AGC Not Forcing & LNA Forcing, may need 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		0x00,	/* reg. 0x0e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		0x00,	/* reg. 0x0f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		0x00,	/* reg. 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		0x00,	/* reg. 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		0x00,	/* reg. 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		0x00,	/* reg. 0x13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		0x50,	/* reg. 0x14: DVB-t High Gain, UHF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			   Middle Gain: 0x48, Low Gain: 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		0x01,	/* reg. 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	switch (priv->xtal_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	case FC_XTAL_27_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	case FC_XTAL_28_8_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		reg[0x07] |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	case FC_XTAL_36_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (priv->dual_master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		reg[0x0c] |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	for (i = 1; i < sizeof(reg); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		ret = fc0013_writereg(priv, i, reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		err("fc0013_writereg failed: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int fc0013_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* nothing to do here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int fc0013_rc_cal_add(struct dvb_frontend *fe, int rc_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct fc0013_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u8 rc_cal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* push rc_cal value, get rc_cal value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ret = fc0013_writereg(priv, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* get rc_cal value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ret = fc0013_readreg(priv, 0x10, &rc_cal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	rc_cal &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	val = (int)rc_cal + rc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* forcing rc_cal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ret = fc0013_writereg(priv, 0x0d, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* modify rc_cal value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (val > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		ret = fc0013_writereg(priv, 0x10, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	else if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		ret = fc0013_writereg(priv, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		ret = fc0013_writereg(priv, 0x10, (u8)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) EXPORT_SYMBOL(fc0013_rc_cal_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int fc0013_rc_cal_reset(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct fc0013_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ret = fc0013_writereg(priv, 0x0d, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		ret = fc0013_writereg(priv, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) EXPORT_SYMBOL(fc0013_rc_cal_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int fc0013_set_vhf_track(struct fc0013_priv *priv, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ret = fc0013_readreg(priv, 0x1d, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	tmp &= 0xe3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (freq <= 177500) {		/* VHF Track: 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	} else if (freq <= 184500) {	/* VHF Track: 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		ret = fc0013_writereg(priv, 0x1d, tmp | 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	} else if (freq <= 191500) {	/* VHF Track: 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		ret = fc0013_writereg(priv, 0x1d, tmp | 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	} else if (freq <= 198500) {	/* VHF Track: 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		ret = fc0013_writereg(priv, 0x1d, tmp | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	} else if (freq <= 205500) {	/* VHF Track: 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		ret = fc0013_writereg(priv, 0x1d, tmp | 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	} else if (freq <= 219500) {	/* VHF Track: 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		ret = fc0013_writereg(priv, 0x1d, tmp | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	} else if (freq < 300000) {	/* VHF Track: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		ret = fc0013_writereg(priv, 0x1d, tmp | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	} else {			/* UHF and GPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		ret = fc0013_writereg(priv, 0x1d, tmp | 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int fc0013_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct fc0013_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u32 freq = p->frequency / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	u32 delsys = p->delivery_system;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned char reg[7], am, pm, multi, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	unsigned long f_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	unsigned short xtal_freq_khz_2, xin, xdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	bool vco_select = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (fe->callback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	switch (priv->xtal_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	case FC_XTAL_27_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		xtal_freq_khz_2 = 27000 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case FC_XTAL_36_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		xtal_freq_khz_2 = 36000 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	case FC_XTAL_28_8_MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		xtal_freq_khz_2 = 28800 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* set VHF track */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ret = fc0013_set_vhf_track(priv, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (freq < 300000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		/* enable VHF filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		ret = fc0013_readreg(priv, 0x07, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		ret = fc0013_writereg(priv, 0x07, tmp | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		/* disable UHF & disable GPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		ret = fc0013_readreg(priv, 0x14, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		ret = fc0013_writereg(priv, 0x14, tmp & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	} else if (freq <= 862000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		/* disable VHF filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		ret = fc0013_readreg(priv, 0x07, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		ret = fc0013_writereg(priv, 0x07, tmp & 0xef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		/* enable UHF & disable GPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		ret = fc0013_readreg(priv, 0x14, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		/* disable VHF filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		ret = fc0013_readreg(priv, 0x07, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		ret = fc0013_writereg(priv, 0x07, tmp & 0xef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		/* disable UHF & enable GPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		ret = fc0013_readreg(priv, 0x14, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		ret = fc0013_writereg(priv, 0x14, (tmp & 0x1f) | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* select frequency divider and the frequency of VCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (freq < 37084) {		/* freq * 96 < 3560000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		multi = 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		reg[5] = 0x82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		reg[6] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	} else if (freq < 55625) {	/* freq * 64 < 3560000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		multi = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		reg[5] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		reg[6] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	} else if (freq < 74167) {	/* freq * 48 < 3560000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		multi = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		reg[5] = 0x42;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		reg[6] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	} else if (freq < 111250) {	/* freq * 32 < 3560000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		multi = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		reg[5] = 0x82;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		reg[6] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	} else if (freq < 148334) {	/* freq * 24 < 3560000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		multi = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		reg[5] = 0x22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		reg[6] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	} else if (freq < 222500) {	/* freq * 16 < 3560000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		multi = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		reg[5] = 0x42;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		reg[6] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	} else if (freq < 296667) {	/* freq * 12 < 3560000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		multi = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		reg[5] = 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		reg[6] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	} else if (freq < 445000) {	/* freq * 8 < 3560000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		multi = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		reg[5] = 0x22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		reg[6] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	} else if (freq < 593334) {	/* freq * 6 < 3560000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		multi = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		reg[5] = 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		reg[6] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	} else if (freq < 950000) {	/* freq * 4 < 3800000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		multi = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		reg[5] = 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		reg[6] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		multi = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		reg[5] = 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		reg[6] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	f_vco = freq * multi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (f_vco >= 3060000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		reg[6] |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		vco_select = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (freq >= 45000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		/* From divided value (XDIV) determined the FA and FP value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		xdiv = (unsigned short)(f_vco / xtal_freq_khz_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		if ((f_vco - xdiv * xtal_freq_khz_2) >= (xtal_freq_khz_2 / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			xdiv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		pm = (unsigned char)(xdiv / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		am = (unsigned char)(xdiv - (8 * pm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		if (am < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			reg[1] = am + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			reg[2] = pm - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			reg[1] = am;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			reg[2] = pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		/* fix for frequency less than 45 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		reg[1] = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		reg[2] = 0x11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	/* fix clock out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	reg[6] |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	/* From VCO frequency determines the XIN ( fractional part of Delta
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	   Sigma PLL) and divided value (XDIV) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	xin = (unsigned short)(f_vco - (f_vco / xtal_freq_khz_2) * xtal_freq_khz_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	xin = (xin << 15) / xtal_freq_khz_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (xin >= 16384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		xin += 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	reg[3] = xin >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	reg[4] = xin & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (delsys == SYS_DVBT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		switch (p->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			reg[6] |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			reg[6] |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		err("%s: modulation type not supported!", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	/* modified for Realtek demod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	reg[5] |= 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	for (i = 1; i <= 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		ret = fc0013_writereg(priv, i, reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	ret = fc0013_readreg(priv, 0x11, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	if (multi == 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		ret = fc0013_writereg(priv, 0x11, tmp | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		ret = fc0013_writereg(priv, 0x11, tmp & 0xfb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	/* VCO Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	ret = fc0013_writereg(priv, 0x0e, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		ret = fc0013_writereg(priv, 0x0e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	/* VCO Re-Calibration if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		ret = fc0013_writereg(priv, 0x0e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		ret = fc0013_readreg(priv, 0x0e, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	/* vco selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	tmp &= 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	if (vco_select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		if (tmp > 0x3c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 			reg[6] &= ~0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 			ret = fc0013_writereg(priv, 0x06, reg[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 			if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 				ret = fc0013_writereg(priv, 0x0e, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 			if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 				ret = fc0013_writereg(priv, 0x0e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		if (tmp < 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			reg[6] |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 			ret = fc0013_writereg(priv, 0x06, reg[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 				ret = fc0013_writereg(priv, 0x0e, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 			if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 				ret = fc0013_writereg(priv, 0x0e, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	priv->frequency = p->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	priv->bandwidth = p->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		warn("%s: failed: %d", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int fc0013_get_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	struct fc0013_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	*frequency = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int fc0013_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	/* always ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	*frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int fc0013_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	struct fc0013_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	*bandwidth = priv->bandwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define INPUT_ADC_LEVEL	-8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int fc0013_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	struct fc0013_priv *priv = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	int int_temp, lna_gain, int_lna, tot_agc_gain, power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	static const int fc0013_lna_gain_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		/* low gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		-63, -58, -99, -73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		-63, -65, -54, -60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		/* middle gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		 71,  70,  68,  67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		 65,  63,  61,  58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		/* high gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		197, 191, 188, 186,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		184, 182, 181, 179,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	ret = fc0013_writereg(priv, 0x13, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	ret = fc0013_readreg(priv, 0x13, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	int_temp = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	ret = fc0013_readreg(priv, 0x14, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	lna_gain = tmp & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	if (lna_gain < ARRAY_SIZE(fc0013_lna_gain_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		int_lna = fc0013_lna_gain_table[lna_gain];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		tot_agc_gain = (abs((int_temp >> 5) - 7) - 2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 				(int_temp & 0x1f)) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		power = INPUT_ADC_LEVEL - tot_agc_gain - int_lna / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		if (power >= 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 			*strength = 255;	/* 100% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		else if (power < -95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 			*strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 			*strength = (power + 95) * 255 / 140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		*strength |= *strength << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 		fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 		warn("%s: failed: %d", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const struct dvb_tuner_ops fc0013_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 		.name		  = "Fitipower FC0013",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 		.frequency_min_hz =   37 * MHz,	/* estimate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		.frequency_max_hz = 1680 * MHz,	/* CHECK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	.release	= fc0013_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	.init		= fc0013_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	.sleep		= fc0013_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	.set_params	= fc0013_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	.get_frequency	= fc0013_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	.get_if_frequency = fc0013_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	.get_bandwidth	= fc0013_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	.get_rf_strength = fc0013_get_rf_strength,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	struct i2c_adapter *i2c, u8 i2c_address, int dual_master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	enum fc001x_xtal_freq xtal_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	struct fc0013_priv *priv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	priv = kzalloc(sizeof(struct fc0013_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	if (priv == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	priv->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	priv->dual_master = dual_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	priv->addr = i2c_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	priv->xtal_freq = xtal_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	info("Fitipower FC0013 successfully attached.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	fe->tuner_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	memcpy(&fe->ops.tuner_ops, &fc0013_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 		sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	return fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) EXPORT_SYMBOL(fc0013_attach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MODULE_DESCRIPTION("Fitipower FC0013 silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MODULE_VERSION("0.2");