Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Elonics E4000 silicon tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include "e4000_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) static int e4000_init(struct e4000_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	ret = regmap_write(dev->regmap, 0x00, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	/* disable output clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	ret = regmap_write(dev->regmap, 0x06, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	ret = regmap_write(dev->regmap, 0x7a, 0x96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	/* configure gains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	ret = regmap_bulk_write(dev->regmap, 0x7e, "\x01\xfe", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	ret = regmap_write(dev->regmap, 0x82, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	ret = regmap_write(dev->regmap, 0x24, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	ret = regmap_bulk_write(dev->regmap, 0x87, "\x20\x01", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	ret = regmap_bulk_write(dev->regmap, 0x9f, "\x7f\x07", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* DC offset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	ret = regmap_write(dev->regmap, 0x2d, 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	ret = regmap_bulk_write(dev->regmap, 0x70, "\x01\x01", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ret = regmap_write(dev->regmap, 0x1a, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ret = regmap_write(dev->regmap, 0x1f, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	dev->active = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static int e4000_sleep(struct e4000_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	dev->active = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	ret = regmap_write(dev->regmap, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static int e4000_set_params(struct e4000_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	unsigned int div_n, k, k_cw, div_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u64 f_vco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u8 buf[5], i_data[4], q_data[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (!dev->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		dev_dbg(&client->dev, "tuner is sleeping\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* gain control manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ret = regmap_write(dev->regmap, 0x1a, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * Fractional-N synthesizer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 *           +----------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 *           v                            |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 *  Fref   +----+     +-------+         +------+     +---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * ------> | PD | --> |  VCO  | ------> | /N.F | <-- | K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 *         +----+     +-------+         +------+     +---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 *                      |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 *                      |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 *                      v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 *                    +-------+  Fout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 *                    | /Rout | ------>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 *                    +-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if (dev->f_frequency <= e4000_pll_lut[i].freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (i == ARRAY_SIZE(e4000_pll_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	#define F_REF dev->clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	div_out = e4000_pll_lut[i].div_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	f_vco = (u64) dev->f_frequency * div_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/* calculate PLL integer and fractional control word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	div_n = div_u64_rem(f_vco, F_REF, &k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	k_cw = div_u64((u64) k * 0x10000, F_REF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		"frequency=%u bandwidth=%u f_vco=%llu F_REF=%u div_n=%u k=%u k_cw=%04x div_out=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		dev->f_frequency, dev->f_bandwidth, f_vco, F_REF, div_n, k,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		k_cw, div_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	buf[0] = div_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	buf[1] = (k_cw >> 0) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	buf[2] = (k_cw >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	buf[3] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	buf[4] = e4000_pll_lut[i].div_out_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ret = regmap_bulk_write(dev->regmap, 0x09, buf, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* LNA filter (RF filter) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		if (dev->f_frequency <= e400_lna_filter_lut[i].freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (i == ARRAY_SIZE(e400_lna_filter_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ret = regmap_write(dev->regmap, 0x10, e400_lna_filter_lut[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* IF filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if (dev->f_bandwidth <= e4000_if_filter_lut[i].freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (i == ARRAY_SIZE(e4000_if_filter_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	buf[0] = e4000_if_filter_lut[i].reg11_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	buf[1] = e4000_if_filter_lut[i].reg12_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ret = regmap_bulk_write(dev->regmap, 0x11, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* frequency band */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		if (dev->f_frequency <= e4000_band_lut[i].freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (i == ARRAY_SIZE(e4000_band_lut)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	ret = regmap_write(dev->regmap, 0x07, e4000_band_lut[i].reg07_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ret = regmap_write(dev->regmap, 0x78, e4000_band_lut[i].reg78_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/* DC offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			ret = regmap_bulk_write(dev->regmap, 0x15, "\x00\x7e\x24", 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		else if (i == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			ret = regmap_bulk_write(dev->regmap, 0x15, "\x00\x7f", 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		else if (i == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			ret = regmap_bulk_write(dev->regmap, 0x15, "\x01", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			ret = regmap_bulk_write(dev->regmap, 0x16, "\x7e", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		ret = regmap_write(dev->regmap, 0x29, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		ret = regmap_bulk_read(dev->regmap, 0x2a, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	swap(q_data[2], q_data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	swap(i_data[2], i_data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ret = regmap_bulk_write(dev->regmap, 0x50, q_data, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	ret = regmap_bulk_write(dev->regmap, 0x60, i_data, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* gain control auto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	ret = regmap_write(dev->regmap, 0x1a, 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  * V4L2 API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #if IS_ENABLED(CONFIG_VIDEO_V4L2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct v4l2_frequency_band bands[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.type = V4L2_TUNER_RF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.rangelow   =    59000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.rangehigh  =  1105000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.type = V4L2_TUNER_RF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.index = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.rangelow   =  1249000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.rangehigh  =  2208000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static inline struct e4000_dev *e4000_subdev_to_dev(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return container_of(sd, struct e4000_dev, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int e4000_standby(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct e4000_dev *dev = e4000_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	ret = e4000_sleep(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	return e4000_set_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int e4000_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct e4000_dev *dev = e4000_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	dev_dbg(&client->dev, "index=%d\n", v->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	strscpy(v->name, "Elonics E4000", sizeof(v->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	v->type = V4L2_TUNER_RF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	v->rangelow  = bands[0].rangelow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	v->rangehigh = bands[1].rangehigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int e4000_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct e4000_dev *dev = e4000_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	dev_dbg(&client->dev, "index=%d\n", v->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int e4000_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct e4000_dev *dev = e4000_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	dev_dbg(&client->dev, "tuner=%d\n", f->tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	f->frequency = dev->f_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int e4000_s_frequency(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			      const struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	struct e4000_dev *dev = e4000_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	dev_dbg(&client->dev, "tuner=%d type=%d frequency=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		f->tuner, f->type, f->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	dev->f_frequency = clamp_t(unsigned int, f->frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				   bands[0].rangelow, bands[1].rangehigh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	return e4000_set_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int e4000_enum_freq_bands(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				  struct v4l2_frequency_band *band)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	struct e4000_dev *dev = e4000_subdev_to_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	dev_dbg(&client->dev, "tuner=%d type=%d index=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		band->tuner, band->type, band->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (band->index >= ARRAY_SIZE(bands))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	band->capability = bands[band->index].capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	band->rangelow = bands[band->index].rangelow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	band->rangehigh = bands[band->index].rangehigh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct v4l2_subdev_tuner_ops e4000_subdev_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.standby                  = e4000_standby,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.g_tuner                  = e4000_g_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	.s_tuner                  = e4000_s_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	.g_frequency              = e4000_g_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.s_frequency              = e4000_s_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.enum_freq_bands          = e4000_enum_freq_bands,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const struct v4l2_subdev_ops e4000_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.tuner                    = &e4000_subdev_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int e4000_set_lna_gain(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	struct e4000_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	u8 u8tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	dev_dbg(&client->dev, "lna auto=%d->%d val=%d->%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		dev->lna_gain_auto->cur.val, dev->lna_gain_auto->val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		dev->lna_gain->cur.val, dev->lna_gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (dev->lna_gain_auto->val && dev->if_gain_auto->cur.val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		u8tmp = 0x17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	else if (dev->lna_gain_auto->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		u8tmp = 0x19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	else if (dev->if_gain_auto->cur.val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		u8tmp = 0x16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		u8tmp = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	ret = regmap_write(dev->regmap, 0x1a, u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	if (dev->lna_gain_auto->val == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		ret = regmap_write(dev->regmap, 0x14, dev->lna_gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int e4000_set_mixer_gain(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	struct e4000_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	u8 u8tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	dev_dbg(&client->dev, "mixer auto=%d->%d val=%d->%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		dev->mixer_gain_auto->cur.val, dev->mixer_gain_auto->val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		dev->mixer_gain->cur.val, dev->mixer_gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	if (dev->mixer_gain_auto->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		u8tmp = 0x15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		u8tmp = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	ret = regmap_write(dev->regmap, 0x20, u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	if (dev->mixer_gain_auto->val == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		ret = regmap_write(dev->regmap, 0x15, dev->mixer_gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int e4000_set_if_gain(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	struct e4000_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	u8 u8tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	dev_dbg(&client->dev, "if auto=%d->%d val=%d->%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		dev->if_gain_auto->cur.val, dev->if_gain_auto->val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		dev->if_gain->cur.val, dev->if_gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	if (dev->if_gain_auto->val && dev->lna_gain_auto->cur.val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		u8tmp = 0x17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	else if (dev->lna_gain_auto->cur.val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		u8tmp = 0x19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	else if (dev->if_gain_auto->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		u8tmp = 0x16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		u8tmp = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	ret = regmap_write(dev->regmap, 0x1a, u8tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	if (dev->if_gain_auto->val == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		buf[0] = e4000_if_gain_lut[dev->if_gain->val].reg16_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		buf[1] = e4000_if_gain_lut[dev->if_gain->val].reg17_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		ret = regmap_bulk_write(dev->regmap, 0x16, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int e4000_pll_lock(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	struct e4000_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	unsigned int uitmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	ret = regmap_read(dev->regmap, 0x07, &uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	dev->pll_lock->val = (uitmp & 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	struct e4000_dev *dev = container_of(ctrl->handler, struct e4000_dev, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	if (!dev->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	case  V4L2_CID_RF_TUNER_PLL_LOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		ret = e4000_pll_lock(dev->fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		dev_dbg(&client->dev, "unknown ctrl: id=%d name=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 			ctrl->id, ctrl->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int e4000_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	struct e4000_dev *dev = container_of(ctrl->handler, struct e4000_dev, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	struct i2c_client *client = dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	if (!dev->active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	case V4L2_CID_RF_TUNER_BANDWIDTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 		 * TODO: Auto logic does not work 100% correctly as tuner driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 		 * do not have information to calculate maximum suitable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		 * bandwidth. Calculating it is responsible of master driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 		dev->f_bandwidth = dev->bandwidth->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		ret = e4000_set_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	case  V4L2_CID_RF_TUNER_LNA_GAIN_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	case  V4L2_CID_RF_TUNER_LNA_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		ret = e4000_set_lna_gain(dev->fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	case  V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	case  V4L2_CID_RF_TUNER_MIXER_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		ret = e4000_set_mixer_gain(dev->fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	case  V4L2_CID_RF_TUNER_IF_GAIN_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	case  V4L2_CID_RF_TUNER_IF_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		ret = e4000_set_if_gain(dev->fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		dev_dbg(&client->dev, "unknown ctrl: id=%d name=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 			ctrl->id, ctrl->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct v4l2_ctrl_ops e4000_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	.g_volatile_ctrl = e4000_g_volatile_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	.s_ctrl = e4000_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)  * DVB API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int e4000_dvb_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	struct e4000_dev *dev = fe->tuner_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	dev->f_frequency = c->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	dev->f_bandwidth = c->bandwidth_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	return e4000_set_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int e4000_dvb_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	return e4000_init(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int e4000_dvb_sleep(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	return e4000_sleep(fe->tuner_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int e4000_dvb_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	*frequency = 0; /* Zero-IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const struct dvb_tuner_ops e4000_dvb_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	.info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 		.name              = "Elonics E4000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		.frequency_min_hz  = 174 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 		.frequency_max_hz  = 862 * MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 	.init = e4000_dvb_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	.sleep = e4000_dvb_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	.set_params = e4000_dvb_set_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	.get_if_frequency = e4000_dvb_get_if_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int e4000_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 		       const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	struct e4000_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	struct e4000_config *cfg = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	struct dvb_frontend *fe = cfg->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	unsigned int uitmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	static const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 		.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 		.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 	dev->clk = cfg->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	dev->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 	dev->fe = cfg->fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 	dev->regmap = devm_regmap_init_i2c(client, &regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	if (IS_ERR(dev->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 		ret = PTR_ERR(dev->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 		goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	/* check if the tuner is there */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	ret = regmap_read(dev->regmap, 0x02, &uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 		goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	dev_dbg(&client->dev, "chip id=%02x\n", uitmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 	if (uitmp != 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 		goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 	/* put sleep as chip seems to be in normal mode by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 	ret = regmap_write(dev->regmap, 0x00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 		goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #if IS_ENABLED(CONFIG_VIDEO_V4L2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 	/* Register controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 	v4l2_ctrl_handler_init(&dev->hdl, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 	dev->bandwidth_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 			V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	dev->bandwidth = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 			V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 	v4l2_ctrl_auto_cluster(2, &dev->bandwidth_auto, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 	dev->lna_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 			V4L2_CID_RF_TUNER_LNA_GAIN_AUTO, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	dev->lna_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 			V4L2_CID_RF_TUNER_LNA_GAIN, 0, 15, 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 	v4l2_ctrl_auto_cluster(2, &dev->lna_gain_auto, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	dev->mixer_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 			V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	dev->mixer_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 			V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 	v4l2_ctrl_auto_cluster(2, &dev->mixer_gain_auto, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	dev->if_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 			V4L2_CID_RF_TUNER_IF_GAIN_AUTO, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 	dev->if_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 			V4L2_CID_RF_TUNER_IF_GAIN, 0, 54, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 	v4l2_ctrl_auto_cluster(2, &dev->if_gain_auto, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 	dev->pll_lock = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 			V4L2_CID_RF_TUNER_PLL_LOCK,  0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	if (dev->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 		ret = dev->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 		dev_err(&client->dev, "Could not initialize controls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 		v4l2_ctrl_handler_free(&dev->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 		goto err_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 	dev->sd.ctrl_handler = &dev->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 	dev->f_frequency = bands[0].rangelow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 	dev->f_bandwidth = dev->bandwidth->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 	v4l2_i2c_subdev_init(&dev->sd, client, &e4000_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 	fe->tuner_priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 	memcpy(&fe->ops.tuner_ops, &e4000_dvb_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 	       sizeof(fe->ops.tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 	v4l2_set_subdevdata(&dev->sd, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 	i2c_set_clientdata(client, &dev->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 	dev_info(&client->dev, "Elonics E4000 successfully identified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) err_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 	dev_dbg(&client->dev, "failed=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static int e4000_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 	struct e4000_dev *dev = container_of(sd, struct e4000_dev, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 	dev_dbg(&client->dev, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #if IS_ENABLED(CONFIG_VIDEO_V4L2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 	v4l2_ctrl_handler_free(&dev->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 	kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct i2c_device_id e4000_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 	{"e4000", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MODULE_DEVICE_TABLE(i2c, e4000_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static struct i2c_driver e4000_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 		.name	= "e4000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 	.probe		= e4000_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 	.remove		= e4000_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 	.id_table	= e4000_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) module_i2c_driver(e4000_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) MODULE_LICENSE("GPL");