^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GS1662 device registration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015-2016 Nexvision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Charles-Antoine Couret <charles-antoine.couret@nexvision.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_FORCE_FMT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_LINES_PER_FRAME 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_WORDS_PER_LINE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_WORDS_PER_ACT_LINE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_ACT_LINES_PER_FRAME 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MASK_H_LOCK 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MASK_V_LOCK 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MASK_STD_LOCK 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MASK_FORCE_STD 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MASK_STD_STATUS 0x3E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GS_WIDTH_MIN 720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GS_WIDTH_MAX 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GS_HEIGHT_MIN 487
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GS_HEIGHT_MAX 1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GS_PIXELCLOCK_MIN 10519200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GS_PIXELCLOCK_MAX 74250000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct gs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct spi_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct v4l2_dv_timings current_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct gs_reg_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u16 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct v4l2_dv_timings format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct gs_reg_fmt_custom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __u64 pixelclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __u32 interlaced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct spi_device_id gs_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { "gs1662", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_DEVICE_TABLE(spi, gs_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct v4l2_dv_timings fmt_cap[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) V4L2_DV_BT_SDI_720X487I60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) V4L2_DV_BT_CEA_720X576P50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) V4L2_DV_BT_CEA_1280X720P24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) V4L2_DV_BT_CEA_1280X720P25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) V4L2_DV_BT_CEA_1280X720P30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) V4L2_DV_BT_CEA_1280X720P50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) V4L2_DV_BT_CEA_1280X720P60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) V4L2_DV_BT_CEA_1920X1080P24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) V4L2_DV_BT_CEA_1920X1080P25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) V4L2_DV_BT_CEA_1920X1080P30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) V4L2_DV_BT_CEA_1920X1080I50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) V4L2_DV_BT_CEA_1920X1080I60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct gs_reg_fmt reg_fmt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { 0x00, V4L2_DV_BT_CEA_1280X720P60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { 0x01, V4L2_DV_BT_CEA_1280X720P60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { 0x02, V4L2_DV_BT_CEA_1280X720P30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { 0x03, V4L2_DV_BT_CEA_1280X720P30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 0x04, V4L2_DV_BT_CEA_1280X720P50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 0x05, V4L2_DV_BT_CEA_1280X720P50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { 0x06, V4L2_DV_BT_CEA_1280X720P25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { 0x07, V4L2_DV_BT_CEA_1280X720P25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { 0x08, V4L2_DV_BT_CEA_1280X720P24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { 0x09, V4L2_DV_BT_CEA_1280X720P24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { 0x0A, V4L2_DV_BT_CEA_1920X1080I60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { 0x0B, V4L2_DV_BT_CEA_1920X1080P30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Default value: keep this field before 0xC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0x14, V4L2_DV_BT_CEA_1920X1080I50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0x0C, V4L2_DV_BT_CEA_1920X1080I50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0x0D, V4L2_DV_BT_CEA_1920X1080P25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0x0E, V4L2_DV_BT_CEA_1920X1080P25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 0x10, V4L2_DV_BT_CEA_1920X1080P24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0x12, V4L2_DV_BT_CEA_1920X1080P24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { 0x16, V4L2_DV_BT_SDI_720X487I60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { 0x19, V4L2_DV_BT_SDI_720X487I60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { 0x18, V4L2_DV_BT_CEA_720X576P50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { 0x1A, V4L2_DV_BT_CEA_720X576P50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Implement following timings before enable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Because of we don't have access to these theoretical timings yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Workaround: use functions to get and set registers for these formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 0x0F, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 0x11, V4L2_DV_BT_XXX_1920X1080I24 }, /* SMPTE 274M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 0x13, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0x15, V4L2_DV_BT_XXX_1920X1035I60 }, /* SMPTE 260M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0x17, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0x1B, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0x1C, V4L2_DV_BT_XXX_2048X1080P25 }, /* SMPTE 428.1M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct v4l2_dv_timings_cap gs_timings_cap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .type = V4L2_DV_BT_656_1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* keep this initialization for compatibility with GCC < 4.4.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .reserved = { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) V4L2_INIT_BT_TIMINGS(GS_WIDTH_MIN, GS_WIDTH_MAX, GS_HEIGHT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) GS_HEIGHT_MAX, GS_PIXELCLOCK_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) GS_PIXELCLOCK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_SDI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) V4L2_DV_BT_CAP_PROGRESSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) | V4L2_DV_BT_CAP_INTERLACED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int gs_read_register(struct spi_device *spi, u16 addr, u16 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u16 buf_addr = (0x8000 | (0x0FFF & addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u16 buf_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct spi_transfer tx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .tx_buf = &buf_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .delay = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .value = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .unit = SPI_DELAY_UNIT_USECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .rx_buf = &buf_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .delay = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .value = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .unit = SPI_DELAY_UNIT_USECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spi_message_add_tail(&tx[0], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) spi_message_add_tail(&tx[1], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *value = buf_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int gs_write_register(struct spi_device *spi, u16 addr, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u16 buf_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u16 buf_value = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct spi_transfer tx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .tx_buf = &buf_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .delay = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .value = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .unit = SPI_DELAY_UNIT_USECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .tx_buf = &buf_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .delay = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .value = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .unit = SPI_DELAY_UNIT_USECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) spi_message_add_tail(&tx[0], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spi_message_add_tail(&tx[1], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int gs_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct spi_device *spi = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = gs_read_register(spi, reg->reg & 0xFFFF, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) reg->val = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg->size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int gs_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct spi_device *spi = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return gs_write_register(spi, reg->reg & 0xFFFF, reg->val & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int gs_status_format(u16 status, struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int std = (status & MASK_STD_STATUS) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (reg_fmt[i].reg_value == std) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *timings = reg_fmt[i].format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static u16 get_register_timings(struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (v4l2_match_dv_timings(timings, ®_fmt[i].format, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return reg_fmt[i].reg_value | MASK_FORCE_STD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static inline struct gs *to_gs(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return container_of(sd, struct gs, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int gs_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct gs *gs = to_gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) reg_value = get_register_timings(timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (reg_value == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) gs->current_timings = *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int gs_g_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct gs *gs = to_gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) *timings = gs->current_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int gs_query_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct gs *gs = to_gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct v4l2_dv_timings fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u16 reg_value, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (gs->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Check if the component detect a line, a frame or something else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * which looks like a video signal activity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, ®_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (reg_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* If no register reports a video signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (i >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) gs_read_register(gs->pdev, REG_STATUS, ®_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (!(reg_value & MASK_H_LOCK) || !(reg_value & MASK_V_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -ENOLCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!(reg_value & MASK_STD_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = gs_status_format(reg_value, &fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *timings = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int gs_enum_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct v4l2_enum_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (timings->index >= ARRAY_SIZE(fmt_cap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (timings->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) timings->timings = fmt_cap[timings->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int gs_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct gs *gs = to_gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (gs->enabled == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) gs->enabled = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* To force the specific format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) reg_value = get_register_timings(&gs->current_timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return gs_write_register(gs->pdev, REG_FORCE_FMT, reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* To renable auto-detection mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return gs_write_register(gs->pdev, REG_FORCE_FMT, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int gs_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct gs *gs = to_gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u16 reg_value, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Check if the component detect a line, a frame or something else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * which looks like a video signal activity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = gs_read_register(gs->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) REG_LINES_PER_FRAME + i, ®_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (reg_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *status = V4L2_IN_ST_NO_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* If no register reports a video signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (i >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *status |= V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = gs_read_register(gs->pdev, REG_STATUS, ®_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!(reg_value & MASK_H_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *status |= V4L2_IN_ST_NO_H_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!(reg_value & MASK_V_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *status |= V4L2_IN_ST_NO_V_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!(reg_value & MASK_STD_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *status |= V4L2_IN_ST_NO_STD_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int gs_dv_timings_cap(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct v4l2_dv_timings_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (cap->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) *cap = gs_timings_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* V4L2 core operation handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct v4l2_subdev_core_ops gs_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .g_register = gs_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .s_register = gs_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct v4l2_subdev_video_ops gs_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .s_dv_timings = gs_s_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .g_dv_timings = gs_g_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .s_stream = gs_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .g_input_status = gs_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .query_dv_timings = gs_query_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct v4l2_subdev_pad_ops gs_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .enum_dv_timings = gs_enum_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .dv_timings_cap = gs_dv_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* V4L2 top level operation handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const struct v4l2_subdev_ops gs_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .core = &gs_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .video = &gs_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .pad = &gs_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int gs_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct gs *gs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) gs = devm_kzalloc(&spi->dev, sizeof(struct gs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) gs->pdev = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sd = &gs->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) spi->mode = SPI_MODE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) spi->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) spi->max_speed_hz = 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) spi->bits_per_word = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) v4l2_spi_subdev_init(sd, spi, &gs_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) gs->current_timings = reg_fmt[0].format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) gs->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Set H_CONFIG to SMPTE timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) gs_write_register(spi, 0x0, 0x300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int gs_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct v4l2_subdev *sd = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct spi_driver gs_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .name = "gs1662",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .probe = gs_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .remove = gs_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .id_table = gs_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) module_spi_driver(gs_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_AUTHOR("Charles-Antoine Couret <charles-antoine.couret@nexvision.fr>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_DESCRIPTION("Gennum GS1662 HD/SD-SDI Serializer driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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