^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Sanechips Technology Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DRIVER_NAME "zx-irdec"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ZX_IR_ENABLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ZX_IREN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ZX_IR_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ZX_DEGL_MASK GENMASK(21, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ZX_DEGL_VALUE(x) (((x) << 20) & ZX_DEGL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ZX_WDBEGIN_MASK GENMASK(18, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ZX_WDBEGIN_VALUE(x) (((x) << 8) & ZX_WDBEGIN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ZX_IR_INTEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ZX_IR_INTSTCLR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ZX_IR_CODE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ZX_IR_CNUM 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ZX_NECRPT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct zx_irdec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct rc_dev *rcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void zx_irdec_set_mask(struct zx_irdec *irdec, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) data = readl(irdec->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) data |= value & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) writel(data, irdec->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static irqreturn_t zx_irdec_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct zx_irdec *irdec = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 address, not_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 command, not_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 rawcode, scancode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum rc_proto rc_proto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel(1, irdec->base + ZX_IR_INTSTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Check repeat frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (readl(irdec->base + ZX_IR_CNUM) & ZX_NECRPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) rc_repeat(irdec->rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) rawcode = readl(irdec->base + ZX_IR_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) not_command = (rawcode >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) command = (rawcode >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) not_address = (rawcode >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) address = rawcode & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) scancode = ir_nec_bytes_to_scancode(address, not_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) command, not_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) &rc_proto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) rc_keydown(irdec->rcd, rc_proto, scancode, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int zx_irdec_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct zx_irdec *irdec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct rc_dev *rcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) irdec = devm_kzalloc(dev, sizeof(*irdec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!irdec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) irdec->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (IS_ERR(irdec->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return PTR_ERR(irdec->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) rcd = devm_rc_allocate_device(dev, RC_DRIVER_SCANCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!rcd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev_err(dev, "failed to allocate rc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) irdec->rcd = rcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) rcd->priv = irdec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rcd->input_phys = DRIVER_NAME "/input0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) rcd->input_id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) rcd->map_name = RC_MAP_ZX_IRDEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) rcd->allowed_protocols = RC_PROTO_BIT_NEC | RC_PROTO_BIT_NECX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) RC_PROTO_BIT_NEC32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rcd->driver_name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) rcd->device_name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) platform_set_drvdata(pdev, irdec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = devm_rc_register_device(dev, rcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_err(dev, "failed to register rc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = devm_request_irq(dev, irq, zx_irdec_irq, 0, NULL, irdec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_err(dev, "failed to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Initialize deglitch level and watchdog counter beginner as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * recommended by vendor BSP code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) zx_irdec_set_mask(irdec, ZX_IR_CTRL, ZX_DEGL_MASK, ZX_DEGL_VALUE(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) zx_irdec_set_mask(irdec, ZX_IR_CTRL, ZX_WDBEGIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ZX_WDBEGIN_VALUE(0x21c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(1, irdec->base + ZX_IR_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Enable the decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) zx_irdec_set_mask(irdec, ZX_IR_ENABLE, ZX_IREN, ZX_IREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int zx_irdec_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct zx_irdec *irdec = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Disable the decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) zx_irdec_set_mask(irdec, ZX_IR_ENABLE, ZX_IREN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(0, irdec->base + ZX_IR_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct of_device_id zx_irdec_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .compatible = "zte,zx296718-irdec" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MODULE_DEVICE_TABLE(of, zx_irdec_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct platform_driver zx_irdec_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .probe = zx_irdec_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .remove = zx_irdec_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .of_match_table = zx_irdec_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) module_platform_driver(zx_irdec_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MODULE_DESCRIPTION("ZTE ZX IR remote control driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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