Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2015 Mans Rullgard <mans@mansr.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DRIVER_NAME "tango-ir"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IR_NEC_CTRL	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IR_NEC_DATA	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IR_CTRL		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IR_RC5_CLK_DIV	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define IR_RC5_DATA	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IR_INT		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define NEC_TIME_BASE	560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define RC5_TIME_BASE	1778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RC6_CTRL	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RC6_CLKDIV	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RC6_DATA0	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RC6_DATA1	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RC6_DATA2	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RC6_DATA3	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RC6_DATA4	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define RC6_CARRIER	36000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RC6_TIME_BASE	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define NEC_CAP(n)	((n) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define GPIO_SEL(n)	((n) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DISABLE_NEC	(BIT(4) | BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ENABLE_RC5	(BIT(0) | BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ENABLE_RC6	(BIT(0) | BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ACK_IR_INT	(BIT(0) | BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ACK_RC6_INT	(BIT(31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define NEC_ANY (RC_PROTO_BIT_NEC | RC_PROTO_BIT_NECX | RC_PROTO_BIT_NEC32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct tango_ir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	void __iomem *rc5_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	void __iomem *rc6_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct rc_dev *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void tango_ir_handle_nec(struct tango_ir *ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 v, code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	enum rc_proto proto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	v = readl_relaxed(ir->rc5_base + IR_NEC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (!v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		rc_repeat(ir->rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	code = ir_nec_bytes_to_scancode(v, v >> 8, v >> 16, v >> 24, &proto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	rc_keydown(ir->rc, proto, code, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static void tango_ir_handle_rc5(struct tango_ir *ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u32 data, field, toggle, addr, cmd, code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	data = readl_relaxed(ir->rc5_base + IR_RC5_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (data & BIT(31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	field = data >> 12 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	toggle = data >> 11 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	addr = data >> 6 & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	cmd = (data & 0x3f) | (field ^ 1) << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	code = RC_SCANCODE_RC5(addr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	rc_keydown(ir->rc, RC_PROTO_RC5, code, toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static void tango_ir_handle_rc6(struct tango_ir *ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u32 data0, data1, toggle, mode, addr, cmd, code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	data0 = readl_relaxed(ir->rc6_base + RC6_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	data1 = readl_relaxed(ir->rc6_base + RC6_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	mode = data0 >> 1 & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (mode != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	toggle = data0 & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	addr = data0 >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	cmd = data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	code = RC_SCANCODE_RC6_0(addr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	rc_keydown(ir->rc, RC_PROTO_RC6_0, code, toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static irqreturn_t tango_ir_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct tango_ir *ir = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned int rc5_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned int rc6_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	rc5_stat = readl_relaxed(ir->rc5_base + IR_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	writel_relaxed(rc5_stat, ir->rc5_base + IR_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	rc6_stat = readl_relaxed(ir->rc6_base + RC6_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	writel_relaxed(rc6_stat, ir->rc6_base + RC6_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (!(rc5_stat & 3) && !(rc6_stat & BIT(31)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (rc5_stat & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		tango_ir_handle_rc5(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (rc5_stat & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		tango_ir_handle_nec(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (rc6_stat & BIT(31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		tango_ir_handle_rc6(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int tango_change_protocol(struct rc_dev *dev, u64 *rc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct tango_ir *ir = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u32 rc5_ctrl = DISABLE_NEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32 rc6_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (*rc_type & NEC_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		rc5_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (*rc_type & RC_PROTO_BIT_RC5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		rc5_ctrl |= ENABLE_RC5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (*rc_type & RC_PROTO_BIT_RC6_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		rc6_ctrl = ENABLE_RC6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	writel_relaxed(rc5_ctrl, ir->rc5_base + IR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	writel_relaxed(rc6_ctrl, ir->rc6_base + RC6_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int tango_ir_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	const char *map_name = RC_MAP_TANGO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct rc_dev *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct tango_ir *ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u64 clkrate, clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int irq, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ir = devm_kzalloc(dev, sizeof(*ir), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (!ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	ir->rc5_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (IS_ERR(ir->rc5_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return PTR_ERR(ir->rc5_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ir->rc6_base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (IS_ERR(ir->rc6_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return PTR_ERR(ir->rc6_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ir->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (IS_ERR(ir->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return PTR_ERR(ir->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	rc = devm_rc_allocate_device(dev, RC_DRIVER_SCANCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	of_property_read_string(dev->of_node, "linux,rc-map-name", &map_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	rc->device_name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	rc->driver_name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	rc->input_phys = DRIVER_NAME "/input0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	rc->map_name = map_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	rc->allowed_protocols = NEC_ANY | RC_PROTO_BIT_RC5 | RC_PROTO_BIT_RC6_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	rc->change_protocol = tango_change_protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	rc->priv = ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ir->rc = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	err = clk_prepare_enable(ir->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	clkrate = clk_get_rate(ir->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	clkdiv = clkrate * NEC_TIME_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	do_div(clkdiv, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	val = NEC_CAP(31) | GPIO_SEL(12) | clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	writel_relaxed(val, ir->rc5_base + IR_NEC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	clkdiv = clkrate * RC5_TIME_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	do_div(clkdiv, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	writel_relaxed(DISABLE_NEC, ir->rc5_base + IR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	writel_relaxed(clkdiv, ir->rc5_base + IR_RC5_CLK_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	writel_relaxed(ACK_IR_INT, ir->rc5_base + IR_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	clkdiv = clkrate * RC6_TIME_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	do_div(clkdiv, RC6_CARRIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	writel_relaxed(ACK_RC6_INT, ir->rc6_base + RC6_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	writel_relaxed((clkdiv >> 2) << 18 | clkdiv, ir->rc6_base + RC6_CLKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	err = devm_request_irq(dev, irq, tango_ir_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			       dev_name(dev), ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	err = devm_rc_register_device(dev, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	platform_set_drvdata(pdev, ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	clk_disable_unprepare(ir->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int tango_ir_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct tango_ir *ir = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	clk_disable_unprepare(ir->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct of_device_id tango_ir_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	{ .compatible = "sigma,smp8642-ir" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MODULE_DEVICE_TABLE(of, tango_ir_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct platform_driver tango_ir_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.probe	= tango_ir_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.remove	= tango_ir_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.name		= DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.of_match_table	= tango_ir_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) module_platform_driver(tango_ir_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_DESCRIPTION("SMP86xx IR decoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MODULE_AUTHOR("Mans Rullgard <mans@mansr.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MODULE_LICENSE("GPL");