^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IR SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * sir_ir - Device driver for use with SIR (serial infra red)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * mode of IrDA on many notebooks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* SECTION: Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PULSE '['
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TIME_CONST (9000000ul / 115200ul)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIR_TIMEOUT (HZ * 5 / 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* onboard sir ports are typically com3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int io = 0x3e8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int irq = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int threshold = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static DEFINE_SPINLOCK(timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct timer_list timerlist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* time of last signal change detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static ktime_t last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* time of last UART data ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static ktime_t last_intr_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int last_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct rc_dev *rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct platform_device *sir_ir_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static DEFINE_SPINLOCK(hardware_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* SECTION: Prototypes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Communication with user-space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void add_read_queue(int flag, unsigned long val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static irqreturn_t sir_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void send_space(unsigned long len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void send_pulse(unsigned long len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int init_hardware(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void drop_hardware(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline unsigned int sinp(int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return inb(io + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline void soutp(int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) outb(value, io + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* SECTION: Communication with user-space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int sir_tx_ir(struct rc_dev *dev, unsigned int *tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) for (i = 0; i < count;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (tx_buf[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) send_pulse(tx_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (i >= count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (tx_buf[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) send_space(tx_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void add_read_queue(int flag, unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct ir_raw_event ev = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pr_debug("add flag %d with val %lu\n", flag, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * statistically, pulses are ~TIME_CONST/2 too long. we could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * maybe make this more exact, but this is good enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (val > TIME_CONST / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val -= TIME_CONST / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) else /* should not ever happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ev.pulse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val += TIME_CONST / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ev.duration = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ir_raw_event_store_with_filter(rcdev, &ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* SECTION: Hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void sir_timeout(struct timer_list *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * if last received signal was a pulse, but receiving stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * within the 9 bit frame, we need to finish this pulse and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * simulate a signal change to from pulse to space. Otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * upper layers will receive two sequences next time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned long pulse_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* avoid interference with interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spin_lock_irqsave(&timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (last_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* clear unread bits in UART and restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* determine 'virtual' pulse end: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pulse_end = min_t(unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ktime_us_delta(last, last_intr_time),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) IR_MAX_DURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_dbg(&sir_ir_dev->dev, "timeout add %d for %lu usec\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) last_value, pulse_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) add_read_queue(last_value, pulse_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) last_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) last = last_intr_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) spin_unlock_irqrestore(&timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ir_raw_event_handle(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static irqreturn_t sir_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ktime_t curr_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long delt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long deltintr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int iir, lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (++counter > 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(&sir_ir_dev->dev, "Trapped in interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) switch (iir & UART_IIR_ID) { /* FIXME toto treba preriedit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case UART_IIR_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (void)inb(io + UART_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case UART_IIR_RLSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case UART_IIR_THRI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (void)inb(io + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case UART_IIR_RDI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* avoid interference with timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) spin_lock_irqsave(&timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) del_timer(&timerlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) data = inb(io + UART_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) curr_time = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) delt = min_t(unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ktime_us_delta(last, curr_time),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IR_MAX_DURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) deltintr = min_t(unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ktime_us_delta(last_intr_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) curr_time),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IR_MAX_DURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_dbg(&sir_ir_dev->dev, "t %lu, d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) deltintr, (int)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * if nothing came in last X cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * it was gap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (deltintr > TIME_CONST * threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (last_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_dbg(&sir_ir_dev->dev, "GAP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* simulate signal change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) add_read_queue(last_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) delt -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) deltintr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) last_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) last = last_intr_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) delt = deltintr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) data = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (data ^ last_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * deltintr > 2*TIME_CONST, remember?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * the other case is timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) add_read_queue(last_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) delt - TIME_CONST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) last_value = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) last = curr_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) last = ktime_sub_us(last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) TIME_CONST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) last_intr_time = curr_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * start timer for end of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * sequence detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) timerlist.expires = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SIR_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) add_timer(&timerlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) lsr = inb(io + UART_LSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } while (lsr & UART_LSR_DR); /* data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) spin_unlock_irqrestore(&timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ir_raw_event_handle(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return IRQ_RETVAL(IRQ_HANDLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void send_space(unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) usleep_range(len, len + 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void send_pulse(unsigned long len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) long bytes_out = len / TIME_CONST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (bytes_out == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bytes_out++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) while (bytes_out--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) outb(PULSE, io + UART_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* FIXME treba seriozne cakanie z char/serial.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) while (!(inb(io + UART_LSR) & UART_LSR_THRE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int init_hardware(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 scratch, scratch2, scratch3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spin_lock_irqsave(&hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * This is a simple port existence test, borrowed from the autoconfig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * function in drivers/tty/serial/8250/8250_port.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) scratch = sinp(UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) soutp(UART_IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #ifdef __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) outb(0xff, 0x080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) scratch2 = sinp(UART_IER) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) soutp(UART_IER, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #ifdef __i386__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) outb(0x00, 0x080);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) scratch3 = sinp(UART_IER) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) soutp(UART_IER, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (scratch2 != 0 || scratch3 != 0x0f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* we fail, there's nothing here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) spin_unlock_irqrestore(&hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pr_err("port existence test failed, cannot continue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* reset UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) outb(0, io + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) outb(0, io + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* init UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* set DLAB, speed = 115200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) outb(1, io + UART_DLL); outb(0, io + UART_DLM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) outb(UART_LCR_WLEN7, io + UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* FIFO operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) outb(UART_IER_RDI, io + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* turn on UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) outb(UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2, io + UART_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_unlock_irqrestore(&hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void drop_hardware(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) spin_lock_irqsave(&hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* turn off interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) outb(0, io + UART_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) spin_unlock_irqrestore(&hardware_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* SECTION: Initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int sir_ir_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) rcdev = devm_rc_allocate_device(&sir_ir_dev->dev, RC_DRIVER_IR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) rcdev->device_name = "SIR IrDA port";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rcdev->input_phys = KBUILD_MODNAME "/input0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) rcdev->input_id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) rcdev->input_id.vendor = 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) rcdev->input_id.product = 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) rcdev->input_id.version = 0x0100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) rcdev->tx_ir = sir_tx_ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) rcdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) rcdev->driver_name = KBUILD_MODNAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rcdev->map_name = RC_MAP_RC6_MCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rcdev->timeout = IR_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) rcdev->dev.parent = &sir_ir_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) timer_setup(&timerlist, sir_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* get I/O port access and IRQ line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!devm_request_region(&sir_ir_dev->dev, io, 8, KBUILD_MODNAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pr_err("i/o port 0x%.4x already in use.\n", io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) retval = devm_request_irq(&sir_ir_dev->dev, irq, sir_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) KBUILD_MODNAME, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pr_err("IRQ %d already in use.\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) retval = init_hardware();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) del_timer_sync(&timerlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pr_info("I/O port 0x%.4x, IRQ %d.\n", io, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) retval = devm_rc_register_device(&sir_ir_dev->dev, rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (retval < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int sir_ir_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) drop_hardware();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) del_timer_sync(&timerlist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct platform_driver sir_ir_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .probe = sir_ir_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .remove = sir_ir_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .name = "sir_ir",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int __init sir_ir_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) retval = platform_driver_register(&sir_ir_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) sir_ir_dev = platform_device_alloc("sir_ir", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!sir_ir_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) goto pdev_alloc_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) retval = platform_device_add(sir_ir_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) goto pdev_add_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pdev_add_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) platform_device_put(sir_ir_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pdev_alloc_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) platform_driver_unregister(&sir_ir_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void __exit sir_ir_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) platform_device_unregister(sir_ir_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) platform_driver_unregister(&sir_ir_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) module_init(sir_ir_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) module_exit(sir_ir_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_AUTHOR("Milan Pikula");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) module_param_hw(io, int, ioport, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) module_param_hw(irq, int, irq, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) module_param(threshold, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MODULE_PARM_DESC(threshold, "space detection threshold (3)");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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