Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2009 Nuvoton PS Team
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Special thanks to Nuvoton for providing hardware, spec sheets and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * sample code upon which portions of this driver are based. Indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * modeled after.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* platform driver name to register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define NVT_DRIVER_NAME "nuvoton-cir"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* debugging module parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define nvt_dbg(text, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		printk(KERN_DEBUG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define nvt_dbg_verbose(text, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	if (debug > 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		printk(KERN_DEBUG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define nvt_dbg_wake(text, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	if (debug > 2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		printk(KERN_DEBUG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RX_BUF_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SIO_ID_MASK 0xfff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) enum nvt_chip_ver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	NVT_UNKNOWN	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	NVT_W83667HG	= 0xa510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	NVT_6775F	= 0xb470,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	NVT_6776F	= 0xc330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	NVT_6779D	= 0xc560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	NVT_INVALID	= 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) struct nvt_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	enum nvt_chip_ver chip_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) struct nvt_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct rc_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* for rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u8 buf[RX_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned int pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* EFER Config register index/data pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 cr_efir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 cr_efdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/* hardware I/O settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned long cir_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	unsigned long cir_wake_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int cir_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	enum nvt_chip_ver chip_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/* hardware id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u8 chip_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u8 chip_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* carrier period = 1 / frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* buffer packet constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define BUF_PULSE_BIT	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define BUF_LEN_MASK	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define BUF_REPEAT_BYTE	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define BUF_REPEAT_MASK	0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* CIR settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* total length of CIR and CIR WAKE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CIR_IOREG_LENGTH	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CIR_RX_LIMIT_COUNT  (IR_DEFAULT_TIMEOUT / SAMPLE_PERIOD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* CIR Regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CIR_IRCON	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CIR_IRSTS	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CIR_IREN	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CIR_RXFCONT	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CIR_CP		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CIR_CC		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CIR_SLCH	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CIR_SLCL	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CIR_FIFOCON	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CIR_IRFIFOSTS	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CIR_SRXFIFO	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CIR_TXFCONT	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CIR_STXFIFO	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CIR_FCCH	0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CIR_FCCL	0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CIR_IRFSM	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* CIR IRCON settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CIR_IRCON_RECV	 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CIR_IRCON_WIREN	 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CIR_IRCON_TXEN	 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CIR_IRCON_RXEN	 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CIR_IRCON_WRXINV 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CIR_IRCON_RXINV	 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CIR_IRCON_SAMPLE_PERIOD_SEL_1	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CIR_IRCON_SAMPLE_PERIOD_SEL_25	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CIR_IRCON_SAMPLE_PERIOD_SEL_50	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CIR_IRCON_SAMPLE_PERIOD_SEL_100	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* FIXME: make this a runtime option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* select sample period as 50us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CIR_IRCON_SAMPLE_PERIOD_SEL	CIR_IRCON_SAMPLE_PERIOD_SEL_50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* CIR IRSTS settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CIR_IRSTS_RDR	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CIR_IRSTS_RTR	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CIR_IRSTS_PE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CIR_IRSTS_RFO	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CIR_IRSTS_TE	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CIR_IRSTS_TTR	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CIR_IRSTS_TFU	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CIR_IRSTS_GH	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* CIR IREN settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CIR_IREN_RDR	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CIR_IREN_RTR	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CIR_IREN_PE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CIR_IREN_RFO	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CIR_IREN_TE	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CIR_IREN_TTR	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CIR_IREN_TFU	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CIR_IREN_GH	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* CIR FIFOCON settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CIR_FIFOCON_TXFIFOCLR		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CIR_FIFOCON_TX_TRIGGER_LEV_31	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CIR_FIFOCON_TX_TRIGGER_LEV_24	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CIR_FIFOCON_TX_TRIGGER_LEV_16	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CIR_FIFOCON_TX_TRIGGER_LEV_8	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* FIXME: make this a runtime option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* select TX trigger level as 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CIR_FIFOCON_TX_TRIGGER_LEV	CIR_FIFOCON_TX_TRIGGER_LEV_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CIR_FIFOCON_RXFIFOCLR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CIR_FIFOCON_RX_TRIGGER_LEV_1	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CIR_FIFOCON_RX_TRIGGER_LEV_8	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CIR_FIFOCON_RX_TRIGGER_LEV_16	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CIR_FIFOCON_RX_TRIGGER_LEV_24	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* FIXME: make this a runtime option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* select RX trigger level as 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CIR_FIFOCON_RX_TRIGGER_LEV	CIR_FIFOCON_RX_TRIGGER_LEV_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* CIR IRFIFOSTS settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CIR_IRFIFOSTS_IR_PENDING	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CIR_IRFIFOSTS_RX_GS		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CIR_IRFIFOSTS_RX_FTA		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CIR_IRFIFOSTS_RX_EMPTY		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CIR_IRFIFOSTS_RX_FULL		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CIR_IRFIFOSTS_TX_FTA		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CIR_IRFIFOSTS_TX_EMPTY		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CIR_IRFIFOSTS_TX_FULL		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* CIR WAKE UP Regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CIR_WAKE_IRCON			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CIR_WAKE_IRSTS			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CIR_WAKE_IREN			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CIR_WAKE_FIFO_CMP_DEEP		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CIR_WAKE_FIFO_CMP_TOL		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CIR_WAKE_FIFO_COUNT		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CIR_WAKE_SLCH			0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CIR_WAKE_SLCL			0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CIR_WAKE_FIFOCON		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CIR_WAKE_SRXFSTS		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CIR_WAKE_SAMPLE_RX_FIFO		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CIR_WAKE_WR_FIFO_DATA		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CIR_WAKE_RD_FIFO_ONLY		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CIR_WAKE_RD_FIFO_ONLY_IDX	0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CIR_WAKE_FIFO_IGNORE		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CIR_WAKE_IRFSM			0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* CIR WAKE UP IRCON settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CIR_WAKE_IRCON_DEC_RST		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CIR_WAKE_IRCON_MODE1		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CIR_WAKE_IRCON_MODE0		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CIR_WAKE_IRCON_RXEN		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CIR_WAKE_IRCON_R		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CIR_WAKE_IRCON_RXINV		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* FIXME/jarod: make this a runtime option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* select a same sample period like cir register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL	CIR_IRCON_SAMPLE_PERIOD_SEL_50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* CIR WAKE IRSTS Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CIR_WAKE_IRSTS_RDR		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CIR_WAKE_IRSTS_RTR		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CIR_WAKE_IRSTS_PE		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CIR_WAKE_IRSTS_RFO		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CIR_WAKE_IRSTS_GH		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CIR_WAKE_IRSTS_IR_PENDING	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* CIR WAKE UP IREN Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CIR_WAKE_IREN_RDR		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CIR_WAKE_IREN_RTR		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CIR_WAKE_IREN_PE		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CIR_WAKE_IREN_RFO		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CIR_WAKE_IREN_GH		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* CIR WAKE FIFOCON settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CIR_WAKE_FIFOCON_RXFIFOCLR	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* FIXME: make this a runtime option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* select WAKE UP RX trigger level as 67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV	CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* CIR WAKE SRXFSTS settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CIR_WAKE_IRFIFOSTS_RX_GS	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CIR_WAKE_IRFIFOSTS_RX_FTA	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CIR_WAKE_IRFIFOSTS_RX_EMPTY	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CIR_WAKE_IRFIFOSTS_RX_FULL	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * the system comparing only 65 bytes (fails with this set to 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CIR_WAKE_FIFO_CMP_BYTES		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* CIR Wake byte comparison tolerance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CIR_WAKE_CMP_TOLERANCE		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * Extended Function Enable Registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  *  Extended Function Index Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  *  Extended Function Data Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CR_EFIR			0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CR_EFDR			0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Possible alternate EFER values, depends on how the chip is wired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CR_EFIR2		0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CR_EFDR2		0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Extended Function Mode enable/disable magic values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define EFER_EFM_ENABLE		0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define EFER_EFM_DISABLE	0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Config regs we need to care about */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CR_SOFTWARE_RESET	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CR_LOGICAL_DEV_SEL	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CR_CHIP_ID_HI		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CR_CHIP_ID_LO		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CR_DEV_POWER_DOWN	0x22 /* bit 2 is CIR power, default power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CR_OUTPUT_PIN_SEL	0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CR_MULTIFUNC_PIN_SEL	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CR_LOGICAL_DEV_EN	0x30 /* valid for all logical devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* next three regs valid for both the CIR and CIR_WAKE logical devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CR_CIR_BASE_ADDR_HI	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CR_CIR_BASE_ADDR_LO	0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CR_CIR_IRQ_RSRC		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* next three regs valid only for ACPI logical dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CR_ACPI_CIR_WAKE	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CR_ACPI_IRQ_EVENTS	0xf6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CR_ACPI_IRQ_EVENTS2	0xf7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Logical devices that we need to care about */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define LOGICAL_DEV_LPT		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define LOGICAL_DEV_CIR		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define LOGICAL_DEV_ACPI	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define LOGICAL_DEV_CIR_WAKE	0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define LOGICAL_DEV_DISABLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define LOGICAL_DEV_ENABLE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CIR_WAKE_ENABLE_BIT	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define PME_INTR_CIR_PASS_BIT	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* w83677hg CIR pin config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define OUTPUT_PIN_SEL_MASK	0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define OUTPUT_ENABLE_CIR	0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define OUTPUT_ENABLE_CIRWB	0x40 /* enable wide-band sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* w83667hg CIR pin config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MULTIFUNC_PIN_SEL_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MULTIFUNC_ENABLE_CIR	0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MULTIFUNC_ENABLE_CIRWB	0x20 /* enable wide-band sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* MCE CIR signal length, related on sample period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* MCE CIR controller signal length: about 43ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  * 43ms / 50us (sample period) * 0.85 (inaccuracy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CONTROLLER_BUF_LEN_MIN 830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* MCE CIR keyboard signal length: about 26ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  * 26ms / 50us (sample period) * 0.85 (inaccuracy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define KEYBOARD_BUF_LEN_MAX 650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define KEYBOARD_BUF_LEN_MIN 610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* MCE CIR mouse signal length: about 24ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)  * 24ms / 50us (sample period) * 0.85 (inaccuracy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MOUSE_BUF_LEN_MIN 565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CIR_SAMPLE_PERIOD 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CIR_SAMPLE_LOW_INACCURACY 0.85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* MAX silence time that driver will sent to lirc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MAX_SILENCE_TIME 60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SAMPLE_PERIOD 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SAMPLE_PERIOD 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SAMPLE_PERIOD 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SAMPLE_PERIOD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* as VISTA MCE definition, valid carrier value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MAX_CARRIER 60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MIN_CARRIER 30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* max wakeup sequence length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define WAKEUP_MAX_SIZE 65