Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for Mediatek IR Receiver Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MTK_IR_DEV KBUILD_MODNAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* Register to enable PWM and IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MTK_CONFIG_HIGH_REG       0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* Bit to enable IR pulse width detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MTK_PWM_EN		  BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * Register to setting ok count whose unit based on hardware sampling period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * indicating IR receiving completion and then making IRQ fires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MTK_OK_COUNT(x)		  (((x) & GENMASK(23, 16)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* Bit to enable IR hardware function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MTK_IR_EN		  BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* Bit to restart IR receiving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MTK_IRCLR		  BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Fields containing pulse width data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MTK_WIDTH_MASK		  (GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* IR threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MTK_IRTHD		 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MTK_DG_CNT_MASK		 (GENMASK(12, 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MTK_DG_CNT(x)		 ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* Bit to enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MTK_IRINT_EN		  BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Bit to clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MTK_IRINT_CLR		  BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* Maximum count of samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MTK_MAX_SAMPLES		  0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* Indicate the end of IR message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MTK_IR_END(v, p)	  ((v) == MTK_MAX_SAMPLES && (p) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* Number of registers to record the pulse width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MTK_CHKDATA_SZ		  17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Sample period in us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MTK_IR_SAMPLE		  46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) enum mtk_fields {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/* Register to setting software sampling period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	MTK_CHK_PERIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* Register to setting hardware sampling period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	MTK_HW_PERIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) enum mtk_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* Register to clear state of state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	MTK_IRCLR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* Register containing pulse width data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	MTK_CHKDATA_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* Register to enable IR interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	MTK_IRINT_EN_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* Register to ack IR interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	MTK_IRINT_CLR_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static const u32 mt7623_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	[MTK_IRCLR_REG] =	0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	[MTK_CHKDATA_REG] =	0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	[MTK_IRINT_EN_REG] =	0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	[MTK_IRINT_CLR_REG] =	0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static const u32 mt7622_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	[MTK_IRCLR_REG] =	0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	[MTK_CHKDATA_REG] =	0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	[MTK_IRINT_EN_REG] =	0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	[MTK_IRINT_CLR_REG] =	0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) struct mtk_field_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * struct mtk_ir_data -	This is the structure holding all differences among
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			various hardwares
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * @regs:		The pointer to the array holding registers offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * @fields:		The pointer to the array holding fields location
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * @div:		The internal divisor for the based reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * @ok_count:		The count indicating the completion of IR data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  *			receiving when count is reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * @hw_period:		The value indicating the hardware sampling period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct mtk_ir_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	const u32 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	const struct mtk_field_type *fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u8 ok_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u32 hw_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct mtk_field_type mt7623_fields[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	[MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	[MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct mtk_field_type mt7622_fields[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	[MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	[MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * struct mtk_ir -	This is the main datasructure for holding the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *			of the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * @dev:		The device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * @rc:			The rc instrance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * @base:		The mapped register i/o base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * @irq:		The IRQ that we are using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * @clk:		The clock that IR internal is using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * @bus:		The clock that software decoder is using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * @data:		Holding specific data for vaious platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mtk_ir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct device	*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct rc_dev	*rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	void __iomem	*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	int		irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct clk	*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct clk	*bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	const struct mtk_ir_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline u32 mtk_chk_period(struct mtk_ir *ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * Period for software decoder used in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 * unit of raw software sampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	dev_dbg(ir->dev, "@pwm clk  = \t%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		clk_get_rate(ir->bus) / ir->data->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	dev_dbg(ir->dev, "@chkperiod = %08x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	tmp = __raw_readl(ir->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	tmp = (tmp & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	__raw_writel(tmp, ir->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	__raw_writel(val, ir->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return __raw_readl(ir->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct mtk_ir *ir = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u8  wid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u32 i, j, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct ir_raw_event rawir = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 * Reset decoder state machine explicitly is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * because 1) the longest duration for space MTK IR hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 * could record is not safely long. e.g  12ms if rx resolution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * is 46us by default. There is still the risk to satisfying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 * every decoder to reset themselves through long enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 * trailing spaces and 2) the IRQ handler guarantees that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * start of IR message is always contained in and starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * from register mtk_chkdata_reg(ir, i).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ir_raw_event_reset(ir->rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* First message must be pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	rawir.pulse = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* Handle all pulse and space IR controller captures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		for (j = 0 ; j < 4 ; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			rawir.pulse = !rawir.pulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			rawir.duration = wid * (MTK_IR_SAMPLE + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			ir_raw_event_store_with_filter(ir->rc, &rawir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 * The maximum number of edges the IR controller can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * hold is MTK_CHKDATA_SZ * 4. So if received IR messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * is over the limit, the last incomplete IR message would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * be appended trailing space and still would be sent into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 * ir-rc-raw to decode. That helps it is possible that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * has enough information to decode a scancode even if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * trailing end of the message is missing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (!MTK_IR_END(wid, rawir.pulse)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		rawir.pulse = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		ir_raw_event_store_with_filter(ir->rc, &rawir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	ir_raw_event_handle(ir->rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * Restart controller for the next receive that would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * clear up all CHKDATA registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/* Clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		     ir->data->regs[MTK_IRINT_CLR_REG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct mtk_ir_data mt7623_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.regs = mt7623_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.fields = mt7623_fields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.ok_count = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.hw_period = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.div	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const struct mtk_ir_data mt7622_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.regs = mt7622_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.fields = mt7622_fields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.ok_count = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.hw_period = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.div	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct of_device_id mtk_ir_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	{ .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	{ .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DEVICE_TABLE(of, mtk_ir_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int mtk_ir_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct device_node *dn = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct mtk_ir *ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	const char *map_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	ir->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	ir->data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ir->clk = devm_clk_get(dev, "clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (IS_ERR(ir->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		dev_err(dev, "failed to get a ir clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		return PTR_ERR(ir->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	ir->bus = devm_clk_get(dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (IS_ERR(ir->bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		 * For compatibility with older device trees try unnamed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		 * ir->bus uses the same clock as ir->clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		ir->bus = ir->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	ir->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (IS_ERR(ir->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		return PTR_ERR(ir->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (!ir->rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		dev_err(dev, "failed to allocate device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	ir->rc->priv = ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ir->rc->device_name = MTK_IR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	ir->rc->input_phys = MTK_IR_DEV "/input0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ir->rc->input_id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ir->rc->input_id.vendor = 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	ir->rc->input_id.product = 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	ir->rc->input_id.version = 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	map_name = of_get_property(dn, "linux,rc-map-name", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	ir->rc->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ir->rc->driver_name = MTK_IR_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	ir->rc->rx_resolution = MTK_IR_SAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	ret = devm_rc_register_device(dev, ir->rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		dev_err(dev, "failed to register rc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	platform_set_drvdata(pdev, ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	ir->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (ir->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (clk_prepare_enable(ir->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		dev_err(dev, "try to enable ir_clk failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (clk_prepare_enable(ir->bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		dev_err(dev, "try to enable ir_clk failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		goto exit_clkdisable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	 * Enable interrupt after proper hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	 * setup and IRQ handler registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	mtk_irq_disable(ir, MTK_IRINT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		dev_err(dev, "failed request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		goto exit_clkdisable_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	 * Setup software sample period as the reference of software decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	       ir->data->fields[MTK_CHK_PERIOD].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		     ir->data->fields[MTK_CHK_PERIOD].reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	 * Setup hardware sampling period used to setup the proper timeout for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	 * indicating end of IR receiving completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	       ir->data->fields[MTK_HW_PERIOD].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		     ir->data->fields[MTK_HW_PERIOD].reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	/* Set de-glitch counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	/* Enable IR and PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	val |= MTK_OK_COUNT(ir->data->ok_count) |  MTK_PWM_EN | MTK_IR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	mtk_irq_enable(ir, MTK_IRINT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		 MTK_IR_SAMPLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) exit_clkdisable_bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	clk_disable_unprepare(ir->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) exit_clkdisable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	clk_disable_unprepare(ir->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int mtk_ir_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	struct mtk_ir *ir = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	 * Avoid contention between remove handler and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	 * IRQ handler so that disabling IR interrupt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	 * waiting for pending IRQ handler to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	mtk_irq_disable(ir, MTK_IRINT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	synchronize_irq(ir->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	clk_disable_unprepare(ir->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	clk_disable_unprepare(ir->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct platform_driver mtk_ir_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	.probe          = mtk_ir_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	.remove         = mtk_ir_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.name = MTK_IR_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.of_match_table = mtk_ir_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) module_platform_driver(mtk_ir_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_LICENSE("GPL");