Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for Amlogic Meson IR remote receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DRIVER_NAME		"meson-ir"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* valid on all Meson platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IR_DEC_LDR_ACTIVE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IR_DEC_LDR_IDLE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IR_DEC_LDR_REPEAT	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IR_DEC_BIT_0		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IR_DEC_REG0		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IR_DEC_FRAME		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IR_DEC_STATUS		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IR_DEC_REG1		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* only available on Meson 8b and newer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IR_DEC_REG2		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define REG0_RATE_MASK		GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DECODE_MODE_NEC		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DECODE_MODE_RAW		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* Meson 6b uses REG1 to configure the mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define REG1_MODE_MASK		GENMASK(8, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define REG1_MODE_SHIFT		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* Meson 8b / GXBB use REG2 to configure the mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define REG2_MODE_MASK		GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define REG2_MODE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define REG1_TIME_IV_MASK	GENMASK(28, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define REG1_IRQSEL_MASK	GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define REG1_IRQSEL_NEC_MODE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define REG1_IRQSEL_RISE_FALL	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define REG1_IRQSEL_FALL	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define REG1_IRQSEL_RISE	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define REG1_RESET		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define REG1_ENABLE		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define STATUS_IR_DEC_IN	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MESON_TRATE		10	/* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct meson_ir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	void __iomem	*reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct rc_dev	*rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	spinlock_t	lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			      u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	data = readl(ir->reg + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	data |= (value & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	writel(data, ir->reg + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct meson_ir *ir = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 duration, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct ir_raw_event rawir = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	spin_lock(&ir->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	duration = readl_relaxed(ir->reg + IR_DEC_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	duration = FIELD_GET(REG1_TIME_IV_MASK, duration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	rawir.duration = duration * MESON_TRATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	status = readl_relaxed(ir->reg + IR_DEC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	rawir.pulse = !!(status & STATUS_IR_DEC_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ir_raw_event_store_with_timeout(ir->rc, &rawir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	spin_unlock(&ir->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int meson_ir_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	const char *map_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct meson_ir *ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ir = devm_kzalloc(dev, sizeof(struct meson_ir), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (!ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ir->reg = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (IS_ERR(ir->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return PTR_ERR(ir->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (!ir->rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		dev_err(dev, "failed to allocate rc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ir->rc->priv = ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	ir->rc->device_name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ir->rc->input_phys = DRIVER_NAME "/input0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	ir->rc->input_id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	map_name = of_get_property(node, "linux,rc-map-name", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	ir->rc->rx_resolution = MESON_TRATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ir->rc->min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ir->rc->timeout = IR_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ir->rc->driver_name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	spin_lock_init(&ir->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	platform_set_drvdata(pdev, ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ret = devm_rc_register_device(dev, ir->rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		dev_err(dev, "failed to register rc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	ret = devm_request_irq(dev, irq, meson_ir_irq, 0, NULL, ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		dev_err(dev, "failed to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* Reset the decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* Set general operation mode (= raw/software decoding) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				  FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				  FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* Set rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* IRQ on rising and falling edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			  FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Enable the decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	dev_info(dev, "receiver initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int meson_ir_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct meson_ir *ir = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	/* Disable the decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	spin_lock_irqsave(&ir->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	spin_unlock_irqrestore(&ir->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void meson_ir_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct meson_ir *ir = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	spin_lock_irqsave(&ir->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * Set operation mode to NEC/hardware decoding to give
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 * bootloader a chance to power the system back on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				  DECODE_MODE_NEC << REG1_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 				  DECODE_MODE_NEC << REG2_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* Set rate to default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, 0x13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	spin_unlock_irqrestore(&ir->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct of_device_id meson_ir_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	{ .compatible = "amlogic,meson6-ir" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	{ .compatible = "amlogic,meson8b-ir" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	{ .compatible = "amlogic,meson-gxbb-ir" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MODULE_DEVICE_TABLE(of, meson_ir_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct platform_driver meson_ir_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.probe		= meson_ir_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.remove		= meson_ir_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.shutdown	= meson_ir_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.name		= DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.of_match_table	= meson_ir_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) module_platform_driver(meson_ir_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_DESCRIPTION("Amlogic Meson IR remote receiver driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_LICENSE("GPL v2");