^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for USB Windows Media Center Ed. eHome Infrared Transceivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010-2011, Jarod Wilson <jarod@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on the original lirc_mceusb and lirc_mceusb2 drivers, by Dan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Conti, Martin Blatter and Daniel Melander, the latter of which was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * in turn also based on the lirc_atiusb driver by Paul Miller. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * two mce drivers were merged into one by Jarod Wilson, with transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * support for the 1st-gen device added primarily by Patrick Calhoun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * with a bit of tweaks by Jarod. Debugging improvements and proper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * support for what appears to be 3rd-gen hardware added by Jarod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Initial port from lirc driver to ir-core drivery by Jarod, based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * partially on a port to an earlier proposed IR infrastructure by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Jon Smirl, which included enhancements and simplifications to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * incoming IR buffer parsing routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Updated in July of 2011 with the aid of Microsoft's official
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * remote/transceiver requirements and specification document, found at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * download.microsoft.com, title
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Windows-Media-Center-RC-IR-Collection-Green-Button-Specification-03-08-2011-V2.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/usb/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pm_wakeup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRIVER_VERSION "1.95"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRIVER_AUTHOR "Jarod Wilson <jarod@redhat.com>"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRIVER_DESC "Windows Media Center Ed. eHome Infrared Transceiver " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "device driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRIVER_NAME "mceusb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USB_TX_TIMEOUT 1000 /* in milliseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USB_CTRL_MSG_SZ 2 /* Size of usb ctrl msg on gen1 hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCE_G1_INIT_MSGS 40 /* Init messages on gen1 hw to throw out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* MCE constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MCE_IRBUF_SIZE 128 /* TX IR buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCE_TIME_UNIT 50 /* Approx 50us resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCE_PACKET_SIZE 31 /* Max length of packet (with header) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCE_IRDATA_HEADER (0x80 + MCE_PACKET_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Actual format is 0x80 + num_bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCE_IRDATA_TRAILER 0x80 /* End of IR data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCE_MAX_CHANNELS 2 /* Two transmitters, hardware dependent? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCE_DEFAULT_TX_MASK 0x03 /* Vals: TX1=0x01, TX2=0x02, ALL=0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCE_PULSE_BIT 0x80 /* Pulse bit, MSB set == PULSE else SPACE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCE_PULSE_MASK 0x7f /* Pulse mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCE_MAX_PULSE_LENGTH 0x7f /* Longest transmittable pulse symbol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * The interface between the host and the IR hardware is command-response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * based. All commands and responses have a consistent format, where a lead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * byte always identifies the type of data following it. The lead byte has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * a port value in the 3 highest bits and a length value in the 5 lowest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * The length field is overloaded, with a value of 11111 indicating that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * following byte is a command or response code, and the length of the entire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * message is determined by the code. If the length field is not 11111, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * it specifies the number of bytes of port data that follow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MCE_CMD 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MCE_PORT_IR 0x4 /* (0x4 << 5) | MCE_CMD = 0x9f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MCE_PORT_SYS 0x7 /* (0x7 << 5) | MCE_CMD = 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCE_PORT_SER 0x6 /* 0xc0 through 0xdf flush & 0x1f bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MCE_PORT_MASK 0xe0 /* Mask out command bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Command port headers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MCE_CMD_PORT_IR 0x9f /* IR-related cmd/rsp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MCE_CMD_PORT_SYS 0xff /* System (non-IR) device cmd/rsp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Commands that set device state (2-4 bytes in length) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MCE_CMD_RESET 0xfe /* Reset device, 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MCE_CMD_RESUME 0xaa /* Resume device after error, 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MCE_CMD_SETIRCFS 0x06 /* Set tx carrier, 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MCE_CMD_SETIRTIMEOUT 0x0c /* Set timeout, 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MCE_CMD_SETIRTXPORTS 0x08 /* Set tx ports, 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MCE_CMD_SETIRRXPORTEN 0x14 /* Set rx ports, 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MCE_CMD_FLASHLED 0x23 /* Flash receiver LED, 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Commands that query device state (all 2 bytes, unless noted) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MCE_CMD_GETIRCFS 0x07 /* Get carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MCE_CMD_GETIRTIMEOUT 0x0d /* Get timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MCE_CMD_GETIRTXPORTS 0x13 /* Get tx ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MCE_CMD_GETIRRXPORTEN 0x15 /* Get rx ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MCE_CMD_GETPORTSTATUS 0x11 /* Get tx port status, 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MCE_CMD_GETIRNUMPORTS 0x16 /* Get number of ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MCE_CMD_GETWAKESOURCE 0x17 /* Get wake source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MCE_CMD_GETEMVER 0x22 /* Get emulator interface version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MCE_CMD_GETDEVDETAILS 0x21 /* Get device details (em ver2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MCE_CMD_GETWAKESUPPORT 0x20 /* Get wake details (em ver2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MCE_CMD_GETWAKEVERSION 0x18 /* Get wake pattern (em ver2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Misc commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MCE_CMD_NOP 0xff /* No operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Responses to commands (non-error cases) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MCE_RSP_EQIRCFS 0x06 /* tx carrier, 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MCE_RSP_EQIRTIMEOUT 0x0c /* rx timeout, 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MCE_RSP_GETWAKESOURCE 0x17 /* wake source, 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MCE_RSP_EQIRTXPORTS 0x08 /* tx port mask, 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MCE_RSP_EQIRRXPORTEN 0x14 /* rx port mask, 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MCE_RSP_GETPORTSTATUS 0x11 /* tx port status, 7 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MCE_RSP_EQIRRXCFCNT 0x15 /* rx carrier count, 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MCE_RSP_EQIRNUMPORTS 0x16 /* number of ports, 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCE_RSP_EQWAKESUPPORT 0x20 /* wake capabilities, 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCE_RSP_EQWAKEVERSION 0x18 /* wake pattern details, 6 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCE_RSP_EQDEVDETAILS 0x21 /* device capabilities, 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCE_RSP_EQEMVER 0x22 /* emulator interface ver, 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCE_RSP_FLASHLED 0x23 /* success flashing LED, 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Responses to error cases, must send MCE_CMD_RESUME to clear them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCE_RSP_CMD_ILLEGAL 0xfe /* illegal command for port, 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCE_RSP_TX_TIMEOUT 0x81 /* tx timed out, 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Misc commands/responses not defined in the MCE remote/transceiver spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MCE_CMD_SIG_END 0x01 /* End of signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCE_CMD_PING 0x03 /* Ping device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCE_CMD_UNKNOWN 0x04 /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCE_CMD_UNKNOWN2 0x05 /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MCE_CMD_UNKNOWN3 0x09 /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCE_CMD_UNKNOWN4 0x0a /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCE_CMD_G_REVISION 0x0b /* Get hw/sw revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MCE_CMD_UNKNOWN5 0x0e /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MCE_CMD_UNKNOWN6 0x0f /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCE_CMD_UNKNOWN8 0x19 /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCE_CMD_UNKNOWN9 0x1b /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCE_CMD_NULL 0x00 /* These show up various places... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* if buf[i] & MCE_PORT_MASK == 0x80 and buf[i] != MCE_CMD_PORT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * then we're looking at a raw IR data sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MCE_COMMAND_IRDATA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MCE_PACKET_LENGTH_MASK 0x1f /* Packet length mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VENDOR_PHILIPS 0x0471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define VENDOR_SMK 0x0609
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VENDOR_TATUNG 0x1460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VENDOR_GATEWAY 0x107b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VENDOR_SHUTTLE 0x1308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VENDOR_SHUTTLE2 0x051c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VENDOR_MITSUMI 0x03ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VENDOR_TOPSEED 0x1784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define VENDOR_RICAVISION 0x179d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define VENDOR_ITRON 0x195d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define VENDOR_FIC 0x1509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VENDOR_LG 0x043e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VENDOR_MICROSOFT 0x045e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define VENDOR_FORMOSA 0x147a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VENDOR_FINTEK 0x1934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VENDOR_PINNACLE 0x2304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define VENDOR_ECS 0x1019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VENDOR_WISTRON 0x0fb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define VENDOR_COMPRO 0x185b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VENDOR_NORTHSTAR 0x04eb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VENDOR_REALTEK 0x0bda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VENDOR_TIVO 0x105a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define VENDOR_CONEXANT 0x0572
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VENDOR_TWISTEDMELON 0x2596
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VENDOR_HAUPPAUGE 0x2040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VENDOR_PCTV 0x2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VENDOR_ADAPTEC 0x03f3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) enum mceusb_model_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MCE_GEN2 = 0, /* Most boards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MCE_GEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MCE_GEN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MCE_GEN3_BROKEN_IRTIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MCE_GEN2_TX_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MCE_GEN2_TX_INV_RX_GOOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) POLARIS_EVK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) CX_HYBRID_TV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MULTIFUNCTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) TIVO_KIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MCE_GEN2_NO_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) HAUPPAUGE_CX_HYBRID_TV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) EVROMEDIA_FULL_HYBRID_FULLHD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ASTROMETA_T2HYBRID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct mceusb_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 mce_gen1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 mce_gen2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 mce_gen3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 tx_mask_normal:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 no_tx:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 broken_irtimeout:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * 2nd IR receiver (short-range, wideband) for learning mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * 0, absent 2nd receiver (rx2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * 1, rx2 present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * 2, rx2 which under counts IR carrier cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 rx2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ir_intfnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const char *rc_map; /* Allow specify a per-board map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const char *name; /* per-board name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct mceusb_model mceusb_model[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [MCE_GEN1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .mce_gen1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .tx_mask_normal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .rx2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [MCE_GEN2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .mce_gen2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .rx2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [MCE_GEN2_NO_TX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .mce_gen2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .no_tx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [MCE_GEN2_TX_INV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .mce_gen2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .tx_mask_normal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .rx2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [MCE_GEN2_TX_INV_RX_GOOD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .mce_gen2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .tx_mask_normal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .rx2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [MCE_GEN3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .mce_gen3 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .tx_mask_normal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .rx2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [MCE_GEN3_BROKEN_IRTIMEOUT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .mce_gen3 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .tx_mask_normal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .rx2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .broken_irtimeout = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [POLARIS_EVK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * In fact, the EVK is shipped without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * remotes, but we should have something handy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * to allow testing it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .name = "Conexant Hybrid TV (cx231xx) MCE IR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .rx2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [CX_HYBRID_TV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .no_tx = 1, /* tx isn't wired up at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = "Conexant Hybrid TV (cx231xx) MCE IR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [HAUPPAUGE_CX_HYBRID_TV] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .no_tx = 1, /* eeprom says it has no tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "Conexant Hybrid TV (cx231xx) MCE IR no TX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [MULTIFUNCTION] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .mce_gen2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .ir_intfnum = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .rx2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [TIVO_KIT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .mce_gen2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .rc_map = RC_MAP_TIVO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .rx2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [EVROMEDIA_FULL_HYBRID_FULLHD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "Evromedia USB Full Hybrid Full HD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .no_tx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .rc_map = RC_MAP_MSI_DIGIVOX_III,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [ASTROMETA_T2HYBRID] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = "Astrometa T2Hybrid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .no_tx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .rc_map = RC_MAP_ASTROMETA_T2HYBRID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const struct usb_device_id mceusb_dev_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Original Microsoft MCE IR Transceiver (often HP-branded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { USB_DEVICE(VENDOR_MICROSOFT, 0x006d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .driver_info = MCE_GEN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Philips Infrared Transceiver - Sahara branded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { USB_DEVICE(VENDOR_PHILIPS, 0x0608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Philips Infrared Transceiver - HP branded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { USB_DEVICE(VENDOR_PHILIPS, 0x060c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .driver_info = MCE_GEN2_TX_INV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Philips SRM5100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { USB_DEVICE(VENDOR_PHILIPS, 0x060d) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Philips Infrared Transceiver - Omaura */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { USB_DEVICE(VENDOR_PHILIPS, 0x060f) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Philips Infrared Transceiver - Spinel plus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { USB_DEVICE(VENDOR_PHILIPS, 0x0613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Philips eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { USB_DEVICE(VENDOR_PHILIPS, 0x0815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Philips/Spinel plus IR transceiver for ASUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { USB_DEVICE(VENDOR_PHILIPS, 0x206c) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Philips/Spinel plus IR transceiver for ASUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { USB_DEVICE(VENDOR_PHILIPS, 0x2088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Philips IR transceiver (Dell branded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { USB_DEVICE(VENDOR_PHILIPS, 0x2093),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .driver_info = MCE_GEN2_TX_INV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Realtek MCE IR Receiver and card reader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { USB_DEVICE(VENDOR_REALTEK, 0x0161),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .driver_info = MULTIFUNCTION },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* SMK/Toshiba G83C0004D410 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { USB_DEVICE(VENDOR_SMK, 0x031d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .driver_info = MCE_GEN2_TX_INV_RX_GOOD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* SMK eHome Infrared Transceiver (Sony VAIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { USB_DEVICE(VENDOR_SMK, 0x0322),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .driver_info = MCE_GEN2_TX_INV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* bundled with Hauppauge PVR-150 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { USB_DEVICE(VENDOR_SMK, 0x0334),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .driver_info = MCE_GEN2_TX_INV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* SMK eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { USB_DEVICE(VENDOR_SMK, 0x0338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* SMK/I-O Data GV-MC7/RCKIT Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { USB_DEVICE(VENDOR_SMK, 0x0353),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .driver_info = MCE_GEN2_NO_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* SMK RXX6000 Infrared Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { USB_DEVICE(VENDOR_SMK, 0x0357),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .driver_info = MCE_GEN2_NO_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Tatung eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { USB_DEVICE(VENDOR_TATUNG, 0x9150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Shuttle eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { USB_DEVICE(VENDOR_SHUTTLE, 0xc001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Shuttle eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { USB_DEVICE(VENDOR_SHUTTLE2, 0xc001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Gateway eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { USB_DEVICE(VENDOR_GATEWAY, 0x3009) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Mitsumi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { USB_DEVICE(VENDOR_MITSUMI, 0x2501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Topseed eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { USB_DEVICE(VENDOR_TOPSEED, 0x0001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .driver_info = MCE_GEN2_TX_INV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Topseed HP eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { USB_DEVICE(VENDOR_TOPSEED, 0x0006),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .driver_info = MCE_GEN2_TX_INV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Topseed eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { USB_DEVICE(VENDOR_TOPSEED, 0x0007),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .driver_info = MCE_GEN2_TX_INV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Topseed eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { USB_DEVICE(VENDOR_TOPSEED, 0x0008),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .driver_info = MCE_GEN3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Topseed eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { USB_DEVICE(VENDOR_TOPSEED, 0x000a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .driver_info = MCE_GEN2_TX_INV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Topseed eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { USB_DEVICE(VENDOR_TOPSEED, 0x0011),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .driver_info = MCE_GEN3_BROKEN_IRTIMEOUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Ricavision internal Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { USB_DEVICE(VENDOR_RICAVISION, 0x0010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Itron ione Libra Q-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { USB_DEVICE(VENDOR_ITRON, 0x7002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* FIC eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { USB_DEVICE(VENDOR_FIC, 0x9242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* LG eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { USB_DEVICE(VENDOR_LG, 0x9803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Microsoft MCE Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { USB_DEVICE(VENDOR_MICROSOFT, 0x00a0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Formosa eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { USB_DEVICE(VENDOR_FORMOSA, 0xe015) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Formosa21 / eHome Infrared Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { USB_DEVICE(VENDOR_FORMOSA, 0xe016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Formosa aim / Trust MCE Infrared Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { USB_DEVICE(VENDOR_FORMOSA, 0xe017),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .driver_info = MCE_GEN2_NO_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Formosa Industrial Computing / Beanbag Emulation Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { USB_DEVICE(VENDOR_FORMOSA, 0xe018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Formosa21 / eHome Infrared Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { USB_DEVICE(VENDOR_FORMOSA, 0xe03a) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Formosa Industrial Computing AIM IR605/A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { USB_DEVICE(VENDOR_FORMOSA, 0xe03c) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Formosa Industrial Computing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { USB_DEVICE(VENDOR_FORMOSA, 0xe03e) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Formosa Industrial Computing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { USB_DEVICE(VENDOR_FORMOSA, 0xe042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Fintek eHome Infrared Transceiver (HP branded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { USB_DEVICE(VENDOR_FINTEK, 0x5168),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .driver_info = MCE_GEN2_TX_INV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Fintek eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { USB_DEVICE(VENDOR_FINTEK, 0x0602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Fintek eHome Infrared Transceiver (in the AOpen MP45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { USB_DEVICE(VENDOR_FINTEK, 0x0702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Pinnacle Remote Kit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { USB_DEVICE(VENDOR_PINNACLE, 0x0225),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .driver_info = MCE_GEN3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Elitegroup Computer Systems IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { USB_DEVICE(VENDOR_ECS, 0x0f38) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Wistron Corp. eHome Infrared Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { USB_DEVICE(VENDOR_WISTRON, 0x0002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Compro K100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { USB_DEVICE(VENDOR_COMPRO, 0x3020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Compro K100 v2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { USB_DEVICE(VENDOR_COMPRO, 0x3082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Northstar Systems, Inc. eHome Infrared Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { USB_DEVICE(VENDOR_NORTHSTAR, 0xe004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* TiVo PC IR Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { USB_DEVICE(VENDOR_TIVO, 0x2000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .driver_info = TIVO_KIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Conexant Hybrid TV "Shelby" Polaris SDK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { USB_DEVICE(VENDOR_CONEXANT, 0x58a1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .driver_info = POLARIS_EVK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Conexant Hybrid TV RDU253S Polaris */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { USB_DEVICE(VENDOR_CONEXANT, 0x58a5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .driver_info = CX_HYBRID_TV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Twisted Melon Inc. - Manta Mini Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { USB_DEVICE(VENDOR_TWISTEDMELON, 0x8008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Twisted Melon Inc. - Manta Pico Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { USB_DEVICE(VENDOR_TWISTEDMELON, 0x8016) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Twisted Melon Inc. - Manta Transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { USB_DEVICE(VENDOR_TWISTEDMELON, 0x8042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Hauppauge WINTV-HVR-HVR 930C-HD - based on cx231xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb130),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .driver_info = HAUPPAUGE_CX_HYBRID_TV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb131),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .driver_info = HAUPPAUGE_CX_HYBRID_TV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb138),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .driver_info = HAUPPAUGE_CX_HYBRID_TV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb139),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .driver_info = HAUPPAUGE_CX_HYBRID_TV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Hauppauge WinTV-HVR-935C - based on cx231xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb151),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .driver_info = HAUPPAUGE_CX_HYBRID_TV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Hauppauge WinTV-HVR-955Q - based on cx231xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb123),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .driver_info = HAUPPAUGE_CX_HYBRID_TV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Hauppauge WinTV-HVR-975 - based on cx231xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .driver_info = HAUPPAUGE_CX_HYBRID_TV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { USB_DEVICE(VENDOR_PCTV, 0x0259),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .driver_info = HAUPPAUGE_CX_HYBRID_TV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { USB_DEVICE(VENDOR_PCTV, 0x025e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .driver_info = HAUPPAUGE_CX_HYBRID_TV },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Adaptec / HP eHome Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { USB_DEVICE(VENDOR_ADAPTEC, 0x0094) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Evromedia USB Full Hybrid Full HD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { USB_DEVICE(0x1b80, 0xd3b2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .driver_info = EVROMEDIA_FULL_HYBRID_FULLHD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Astrometa T2hybrid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { USB_DEVICE(0x15f4, 0x0135),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .driver_info = ASTROMETA_T2HYBRID },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Terminating entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* data structure for each usb transceiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct mceusb_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* ir-core bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct rc_dev *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* optional features we can enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) bool carrier_report_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) bool wideband_rx_enabled; /* aka learning mode, short-range rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* core device bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* usb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct usb_device *usbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct usb_interface *usbintf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct urb *urb_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned int pipe_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct usb_endpoint_descriptor *usb_ep_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int pipe_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* buffers and dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) unsigned char *buf_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned int len_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dma_addr_t dma_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) CMD_HEADER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) SUBCMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) CMD_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PARSE_IRDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) } parser_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u8 cmd, rem; /* Remaining IR data bytes in packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 connected:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 tx_mask_normal:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 microsoft_gen1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 no_tx:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 rx2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) } flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* transmit support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned char tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) char name[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) char phys[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) enum mceusb_model_type model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) bool need_reset; /* flag to issue a device resume cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 emver; /* emulator interface version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 num_txports; /* number of transmit ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 num_rxports; /* number of receive sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u8 txports_cabled; /* bitmask of transmitters with cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u8 rxports_active; /* bitmask of active receive sensors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bool learning_active; /* wideband rx is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* receiver carrier frequency detection support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 pulse_tunit; /* IR pulse "on" cumulative time units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 pulse_count; /* pulse "on" count in measurement interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * support for async error handler mceusb_deferred_kevent()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * where usb_clear_halt(), usb_reset_configuration(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * usb_reset_device(), etc. must be done in process context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct work_struct kevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned long kevent_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) # define EVENT_TX_HALT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) # define EVENT_RX_HALT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) # define EVENT_RST_PEND 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* MCE Device Command Strings, generally a port and command pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static char DEVICE_RESUME[] = {MCE_CMD_NULL, MCE_CMD_PORT_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MCE_CMD_RESUME};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static char GET_REVISION[] = {MCE_CMD_PORT_SYS, MCE_CMD_G_REVISION};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static char GET_EMVER[] = {MCE_CMD_PORT_SYS, MCE_CMD_GETEMVER};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static char GET_WAKEVERSION[] = {MCE_CMD_PORT_SYS, MCE_CMD_GETWAKEVERSION};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static char FLASH_LED[] = {MCE_CMD_PORT_SYS, MCE_CMD_FLASHLED};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static char GET_UNKNOWN2[] = {MCE_CMD_PORT_IR, MCE_CMD_UNKNOWN2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static char GET_CARRIER_FREQ[] = {MCE_CMD_PORT_IR, MCE_CMD_GETIRCFS};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static char GET_RX_TIMEOUT[] = {MCE_CMD_PORT_IR, MCE_CMD_GETIRTIMEOUT};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static char GET_NUM_PORTS[] = {MCE_CMD_PORT_IR, MCE_CMD_GETIRNUMPORTS};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static char GET_TX_BITMASK[] = {MCE_CMD_PORT_IR, MCE_CMD_GETIRTXPORTS};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static char GET_RX_SENSOR[] = {MCE_CMD_PORT_IR, MCE_CMD_GETIRRXPORTEN};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* sub in desired values in lower byte or bytes for full command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* FIXME: make use of these for transmit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static char SET_CARRIER_FREQ[] = {MCE_CMD_PORT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MCE_CMD_SETIRCFS, 0x00, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static char SET_TX_BITMASK[] = {MCE_CMD_PORT_IR, MCE_CMD_SETIRTXPORTS, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static char SET_RX_TIMEOUT[] = {MCE_CMD_PORT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MCE_CMD_SETIRTIMEOUT, 0x00, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static char SET_RX_SENSOR[] = {MCE_CMD_PORT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MCE_RSP_EQIRRXPORTEN, 0x00};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int mceusb_cmd_datasize(u8 cmd, u8 subcmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int datasize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case MCE_CMD_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (subcmd == MCE_CMD_PORT_SYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) datasize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case MCE_CMD_PORT_SYS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) switch (subcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case MCE_RSP_GETPORTSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) datasize = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case MCE_RSP_EQWAKEVERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) datasize = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case MCE_CMD_G_REVISION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) datasize = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case MCE_RSP_EQWAKESUPPORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case MCE_RSP_GETWAKESOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case MCE_RSP_EQDEVDETAILS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case MCE_RSP_EQEMVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) datasize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case MCE_CMD_PORT_IR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) switch (subcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case MCE_CMD_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case MCE_RSP_EQIRCFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case MCE_RSP_EQIRTIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case MCE_RSP_EQIRRXCFCNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case MCE_RSP_EQIRNUMPORTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) datasize = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case MCE_CMD_SIG_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case MCE_RSP_EQIRTXPORTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case MCE_RSP_EQIRRXPORTEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) datasize = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return datasize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static void mceusb_dev_printdata(struct mceusb_dev *ir, u8 *buf, int buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int offset, int len, bool out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) char *inout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u8 cmd, subcmd, *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct device *dev = ir->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 carrier, period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (offset < 0 || offset >= buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_dbg(dev, "%cx data[%d]: %*ph (len=%d sz=%d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) (out ? 't' : 'r'), offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) min(len, buf_len - offset), buf + offset, len, buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) inout = out ? "Request" : "Got";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) cmd = buf[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) subcmd = (offset + 1 < buf_len) ? buf[offset + 1] : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) data = &buf[offset] + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Trace meaningless 0xb1 0x60 header bytes on original receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (ir->flags.microsoft_gen1 && !out && !offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_dbg(dev, "MCE gen 1 header");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Trace IR data header or trailer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (cmd != MCE_CMD_PORT_IR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) (cmd & MCE_PORT_MASK) == MCE_COMMAND_IRDATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (cmd == MCE_IRDATA_TRAILER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_dbg(dev, "End of raw IR data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_dbg(dev, "Raw IR data, %d pulse/space samples",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) cmd & MCE_PACKET_LENGTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Unexpected end of buffer? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (offset + len > buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Decode MCE command/response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) case MCE_CMD_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (subcmd == MCE_CMD_NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if ((subcmd == MCE_CMD_PORT_SYS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) (data[0] == MCE_CMD_RESUME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_dbg(dev, "Device resume requested");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_dbg(dev, "Unknown command 0x%02x 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) cmd, subcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case MCE_CMD_PORT_SYS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) switch (subcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case MCE_RSP_EQEMVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (!out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_dbg(dev, "Emulator interface version %x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case MCE_CMD_G_REVISION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (len == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_dbg(dev, "Get hw/sw rev?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev_dbg(dev, "hw/sw rev %*ph",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 4, &buf[offset + 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) case MCE_CMD_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dev_dbg(dev, "Device resume requested");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case MCE_RSP_CMD_ILLEGAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_dbg(dev, "Illegal PORT_SYS command");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) case MCE_RSP_EQWAKEVERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_dbg(dev, "Wake version, proto: 0x%02x, payload: 0x%02x, address: 0x%02x, version: 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) data[0], data[1], data[2], data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case MCE_RSP_GETPORTSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* We use data1 + 1 here, to match hw labels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_dbg(dev, "TX port %d: blaster is%s connected",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) data[0] + 1, data[3] ? " not" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case MCE_CMD_FLASHLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_dbg(dev, "Attempting to flash LED");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_dbg(dev, "Unknown command 0x%02x 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) cmd, subcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case MCE_CMD_PORT_IR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) switch (subcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case MCE_CMD_SIG_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_dbg(dev, "End of signal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) case MCE_CMD_PING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_dbg(dev, "Ping");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) case MCE_CMD_UNKNOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_dbg(dev, "Resp to 9f 05 of 0x%02x 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) data[0], data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case MCE_RSP_EQIRCFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (!data[0] && !data[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_dbg(dev, "%s: no carrier", inout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) // prescaler should make sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (data[0] > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) period = DIV_ROUND_CLOSEST((1U << data[0] * 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) (data[1] + 1), 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (!period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) carrier = USEC_PER_SEC / period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_dbg(dev, "%s carrier of %u Hz (period %uus)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) inout, carrier, period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case MCE_CMD_GETIRCFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dev_dbg(dev, "Get carrier mode and freq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case MCE_RSP_EQIRTXPORTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_dbg(dev, "%s transmit blaster mask of 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) inout, data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case MCE_RSP_EQIRTIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* value is in units of 50us, so x*50/1000 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) period = ((data[0] << 8) | data[1]) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) MCE_TIME_UNIT / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_dbg(dev, "%s receive timeout of %d ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) inout, period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case MCE_CMD_GETIRTIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev_dbg(dev, "Get receive timeout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case MCE_CMD_GETIRTXPORTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_dbg(dev, "Get transmit blaster mask");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case MCE_RSP_EQIRRXPORTEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_dbg(dev, "%s %s-range receive sensor in use",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) inout, data[0] == 0x02 ? "short" : "long");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case MCE_CMD_GETIRRXPORTEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* aka MCE_RSP_EQIRRXCFCNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dev_dbg(dev, "Get receive sensor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dev_dbg(dev, "RX carrier cycle count: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ((data[0] << 8) | data[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case MCE_RSP_EQIRNUMPORTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_dbg(dev, "Num TX ports: %x, num RX ports: %x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) data[0], data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case MCE_RSP_CMD_ILLEGAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_dbg(dev, "Illegal PORT_IR command");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case MCE_RSP_TX_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_dbg(dev, "IR TX timeout (TX buffer underrun)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev_dbg(dev, "Unknown command 0x%02x 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) cmd, subcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * Schedule work that can't be done in interrupt handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * (mceusb_dev_recv() and mce_write_callback()) nor tasklets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * Invokes mceusb_deferred_kevent() for recovering from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * error events specified by the kevent bit field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static void mceusb_defer_kevent(struct mceusb_dev *ir, int kevent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) set_bit(kevent, &ir->kevent_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (test_bit(EVENT_RST_PEND, &ir->kevent_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev_dbg(ir->dev, "kevent %d dropped pending USB Reset Device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) kevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!schedule_work(&ir->kevent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dev_dbg(ir->dev, "kevent %d already scheduled", kevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_dbg(ir->dev, "kevent %d scheduled", kevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static void mce_write_callback(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) complete(urb->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * Write (TX/send) data to MCE device USB endpoint out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * Used for IR blaster TX and MCE device commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * Return: The number of bytes written (> 0) or errno (< 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int mce_write(struct mceusb_dev *ir, u8 *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct urb *urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct device *dev = ir->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned char *buf_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct completion tx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) unsigned long expire;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) unsigned long ret_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) mceusb_dev_printdata(ir, data, size, 0, size, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) urb = usb_alloc_urb(0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (unlikely(!urb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dev_err(dev, "Error: mce write couldn't allocate urb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) buf_out = kmalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!buf_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) usb_free_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) init_completion(&tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* outbound data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (usb_endpoint_xfer_int(ir->usb_ep_out))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) usb_fill_int_urb(urb, ir->usbdev, ir->pipe_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) buf_out, size, mce_write_callback, &tx_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ir->usb_ep_out->bInterval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) usb_fill_bulk_urb(urb, ir->usbdev, ir->pipe_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) buf_out, size, mce_write_callback, &tx_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) memcpy(buf_out, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = usb_submit_urb(urb, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev_err(dev, "Error: mce write submit urb error = %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) kfree(buf_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) usb_free_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) expire = msecs_to_jiffies(USB_TX_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret_wait = wait_for_completion_timeout(&tx_done, expire);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (!ret_wait) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_err(dev, "Error: mce write timed out (expire = %lu (%dms))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) expire, USB_TX_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) usb_kill_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret = (urb->status == -ENOENT ? -ETIMEDOUT : urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret = urb->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ret = urb->actual_length; /* bytes written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) switch (urb->status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case -ECONNRESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) case -ENOENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case -EILSEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case -ESHUTDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case -EPIPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev_err(ir->dev, "Error: mce write urb status = %d (TX HALT)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mceusb_defer_kevent(ir, EVENT_TX_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev_err(ir->dev, "Error: mce write urb status = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev_dbg(dev, "tx done status = %d (wait = %lu, expire = %lu (%dms), urb->actual_length = %d, urb->status = %d)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret, ret_wait, expire, USB_TX_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) urb->actual_length, urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) kfree(buf_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) usb_free_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static void mce_command_out(struct mceusb_dev *ir, u8 *data, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int rsize = sizeof(DEVICE_RESUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ir->need_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ir->need_reset = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) mce_write(ir, DEVICE_RESUME, rsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) mce_write(ir, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * Transmit IR out the MCE device IR blaster port(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * Convert IR pulse/space sequence from LIRC to MCE format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * Break up a long IR sequence into multiple parts (MCE IR data packets).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * u32 txbuf[] consists of IR pulse, space, ..., and pulse times in usec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * Pulses and spaces are implicit by their position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * The first IR sample, txbuf[0], is always a pulse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * u8 irbuf[] consists of multiple IR data packets for the MCE device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * A packet is 1 u8 MCE_IRDATA_HEADER and up to 30 u8 IR samples.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * An IR sample is 1-bit pulse/space flag with 7-bit time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * in MCE time units (50usec).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * Return: The number of IR samples sent (> 0) or errno (< 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static int mceusb_tx_ir(struct rc_dev *dev, unsigned *txbuf, unsigned count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct mceusb_dev *ir = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u8 cmdbuf[3] = { MCE_CMD_PORT_IR, MCE_CMD_SETIRTXPORTS, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u8 irbuf[MCE_IRBUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) int ircount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) unsigned int irsample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int i, length, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Send the set TX ports command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) cmdbuf[2] = ir->tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) mce_command_out(ir, cmdbuf, sizeof(cmdbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* Generate mce IR data packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) irsample = txbuf[i] / MCE_TIME_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* loop to support long pulses/spaces > 6350us (127*50us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) while (irsample > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Insert IR header every 30th entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (ircount % MCE_PACKET_SIZE == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* Room for IR header and one IR sample? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (ircount >= MCE_IRBUF_SIZE - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* Send near full buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = mce_write(ir, irbuf, ircount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ircount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) irbuf[ircount++] = MCE_IRDATA_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* Insert IR sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (irsample <= MCE_MAX_PULSE_LENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) irbuf[ircount] = irsample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) irsample = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) irbuf[ircount] = MCE_MAX_PULSE_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) irsample -= MCE_MAX_PULSE_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * Even i = IR pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * Odd i = IR space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) irbuf[ircount] |= (i & 1 ? 0 : MCE_PULSE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ircount++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* IR buffer full? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (ircount >= MCE_IRBUF_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* Fix packet length in last header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) length = ircount % MCE_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (length > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) irbuf[ircount - length] -=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) MCE_PACKET_SIZE - length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* Send full buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = mce_write(ir, irbuf, ircount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ircount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) } /* after for loop, 0 <= ircount < MCE_IRBUF_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* Fix packet length in last header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) length = ircount % MCE_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (length > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) irbuf[ircount - length] -= MCE_PACKET_SIZE - length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Append IR trailer (0x80) to final partial (or empty) IR buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) irbuf[ircount++] = MCE_IRDATA_TRAILER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* Send final buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ret = mce_write(ir, irbuf, ircount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* Sets active IR outputs -- mce devices typically have two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int mceusb_set_tx_mask(struct rc_dev *dev, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct mceusb_dev *ir = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* return number of transmitters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int emitters = ir->num_txports ? ir->num_txports : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (mask >= (1 << emitters))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return emitters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ir->flags.tx_mask_normal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ir->tx_mask = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ir->tx_mask = (mask != MCE_DEFAULT_TX_MASK ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) mask ^ MCE_DEFAULT_TX_MASK : mask) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Sets the send carrier frequency and mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static int mceusb_set_tx_carrier(struct rc_dev *dev, u32 carrier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct mceusb_dev *ir = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) int clk = 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int prescaler = 0, divisor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) unsigned char cmdbuf[4] = { MCE_CMD_PORT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) MCE_CMD_SETIRCFS, 0x00, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* Carrier has changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (ir->carrier != carrier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (carrier == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ir->carrier = carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) cmdbuf[2] = MCE_CMD_SIG_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) cmdbuf[3] = MCE_IRDATA_TRAILER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) dev_dbg(ir->dev, "disabling carrier modulation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) mce_command_out(ir, cmdbuf, sizeof(cmdbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) for (prescaler = 0; prescaler < 4; ++prescaler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) divisor = (clk >> (2 * prescaler)) / carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (divisor <= 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ir->carrier = carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) cmdbuf[2] = prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) cmdbuf[3] = divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) dev_dbg(ir->dev, "requesting %u HZ carrier",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) carrier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Transmit new carrier to mce device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mce_command_out(ir, cmdbuf, sizeof(cmdbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int mceusb_set_timeout(struct rc_dev *dev, unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) u8 cmdbuf[4] = { MCE_CMD_PORT_IR, MCE_CMD_SETIRTIMEOUT, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct mceusb_dev *ir = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) unsigned int units;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) units = DIV_ROUND_CLOSEST(timeout, MCE_TIME_UNIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) cmdbuf[2] = units >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) cmdbuf[3] = units;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) mce_command_out(ir, cmdbuf, sizeof(cmdbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* get receiver timeout value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) mce_command_out(ir, GET_RX_TIMEOUT, sizeof(GET_RX_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * Select or deselect the 2nd receiver port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * Second receiver is learning mode, wide-band, short-range receiver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * Only one receiver (long or short range) may be active at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int mceusb_set_rx_wideband(struct rc_dev *dev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct mceusb_dev *ir = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) unsigned char cmdbuf[3] = { MCE_CMD_PORT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) MCE_CMD_SETIRRXPORTEN, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) dev_dbg(ir->dev, "select %s-range receive sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) enable ? "short" : "long");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ir->wideband_rx_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) cmdbuf[2] = 2; /* port 2 is short range receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ir->wideband_rx_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) cmdbuf[2] = 1; /* port 1 is long range receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) mce_command_out(ir, cmdbuf, sizeof(cmdbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* response from device sets ir->learning_active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * Enable/disable receiver carrier frequency pass through reporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * Only the short-range receiver has carrier frequency measuring capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * Implicitly select this receiver when enabling carrier frequency reporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static int mceusb_set_rx_carrier_report(struct rc_dev *dev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct mceusb_dev *ir = dev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) unsigned char cmdbuf[3] = { MCE_CMD_PORT_IR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) MCE_CMD_SETIRRXPORTEN, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev_dbg(ir->dev, "%s short-range receiver carrier reporting",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) enable ? "enable" : "disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ir->carrier_report_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (!ir->learning_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) cmdbuf[2] = 2; /* port 2 is short range receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) mce_command_out(ir, cmdbuf, sizeof(cmdbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ir->carrier_report_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * Revert to normal (long-range) receiver only if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * wideband (short-range) receiver wasn't explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (ir->learning_active && !ir->wideband_rx_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) cmdbuf[2] = 1; /* port 1 is long range receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) mce_command_out(ir, cmdbuf, sizeof(cmdbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * Handle PORT_SYS/IR command response received from the MCE device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * Assumes single response with all its data (not truncated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * in buf_in[]. The response itself determines its total length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * (mceusb_cmd_datasize() + 2) and hence the minimum size of buf_in[].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * We don't do anything but print debug spew for many of the command bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * we receive from the hardware, but some of them are useful information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * we want to store so that we can use them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static void mceusb_handle_command(struct mceusb_dev *ir, u8 *buf_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u8 cmd = buf_in[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) u8 subcmd = buf_in[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u8 *hi = &buf_in[2]; /* read only when required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) u8 *lo = &buf_in[3]; /* read only when required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct ir_raw_event rawir = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) u32 carrier_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) u32 cycles_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (cmd == MCE_CMD_PORT_SYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) switch (subcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* the one and only 5-byte return value command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) case MCE_RSP_GETPORTSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (buf_in[5] == 0 && *hi < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ir->txports_cabled |= 1 << *hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* 1-byte return value commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) case MCE_RSP_EQEMVER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ir->emver = *hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* No return value commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) case MCE_RSP_CMD_ILLEGAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ir->need_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (cmd != MCE_CMD_PORT_IR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) switch (subcmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* 2-byte return value commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) case MCE_RSP_EQIRTIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ir->rc->timeout = (*hi << 8 | *lo) * MCE_TIME_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) case MCE_RSP_EQIRNUMPORTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ir->num_txports = *hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ir->num_rxports = *lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) case MCE_RSP_EQIRRXCFCNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * The carrier cycle counter can overflow and wrap around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * without notice from the device. So frequency measurement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * will be inaccurate with long duration IR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * The long-range (non learning) receiver always reports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * zero count so we always ignore its report.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (ir->carrier_report_enabled && ir->learning_active &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ir->pulse_tunit > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) carrier_cycles = (*hi << 8 | *lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * Adjust carrier cycle count by adding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * 1 missed count per pulse "on"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) cycles_fix = ir->flags.rx2 == 2 ? ir->pulse_count : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) rawir.carrier_report = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) rawir.carrier = (1000000u / MCE_TIME_UNIT) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) (carrier_cycles + cycles_fix) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ir->pulse_tunit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_dbg(ir->dev, "RX carrier frequency %u Hz (pulse count = %u, cycles = %u, duration = %u, rx2 = %u)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) rawir.carrier, ir->pulse_count, carrier_cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ir->pulse_tunit, ir->flags.rx2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ir_raw_event_store(ir->rc, &rawir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* 1-byte return value commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) case MCE_RSP_EQIRTXPORTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ir->tx_mask = *hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) case MCE_RSP_EQIRRXPORTEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ir->learning_active = ((*hi & 0x02) == 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (ir->rxports_active != *hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dev_info(ir->dev, "%s-range (0x%x) receiver active",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ir->learning_active ? "short" : "long", *hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ir->rxports_active = *hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* No return value commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) case MCE_RSP_CMD_ILLEGAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) case MCE_RSP_TX_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ir->need_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static void mceusb_process_ir_data(struct mceusb_dev *ir, int buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct ir_raw_event rawir = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) bool event = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* skip meaningless 0xb1 0x60 header bytes on orig receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (ir->flags.microsoft_gen1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /* if there's no data, just return now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (buf_len <= i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) for (; i < buf_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) switch (ir->parser_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case SUBCMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ir->rem = mceusb_cmd_datasize(ir->cmd, ir->buf_in[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) mceusb_dev_printdata(ir, ir->buf_in, buf_len, i - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ir->rem + 2, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (i + ir->rem < buf_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) mceusb_handle_command(ir, &ir->buf_in[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ir->parser_state = CMD_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) case PARSE_IRDATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ir->rem--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) rawir.pulse = ((ir->buf_in[i] & MCE_PULSE_BIT) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) rawir.duration = (ir->buf_in[i] & MCE_PULSE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (unlikely(!rawir.duration)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) dev_dbg(ir->dev, "nonsensical irdata %02x with duration 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ir->buf_in[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (rawir.pulse) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ir->pulse_tunit += rawir.duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ir->pulse_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) rawir.duration *= MCE_TIME_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dev_dbg(ir->dev, "Storing %s %u us (%02x)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) rawir.pulse ? "pulse" : "space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) rawir.duration, ir->buf_in[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (ir_raw_event_store_with_filter(ir->rc, &rawir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) event = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case CMD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ir->rem--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) case CMD_HEADER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ir->cmd = ir->buf_in[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if ((ir->cmd == MCE_CMD_PORT_IR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ((ir->cmd & MCE_PORT_MASK) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) MCE_COMMAND_IRDATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * got PORT_SYS, PORT_IR, or unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * command response prefix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) ir->parser_state = SUBCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * got IR data prefix (0x80 + num_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * decode MCE packets of the form {0x83, AA, BB, CC}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * IR data packets can span USB messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ir->rem = (ir->cmd & MCE_PACKET_LENGTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) mceusb_dev_printdata(ir, ir->buf_in, buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) i, ir->rem + 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (ir->rem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ir->parser_state = PARSE_IRDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct ir_raw_event ev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .timeout = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .duration = ir->rc->timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (ir_raw_event_store_with_filter(ir->rc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) &ev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) event = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) ir->pulse_tunit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ir->pulse_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (ir->parser_state != CMD_HEADER && !ir->rem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ir->parser_state = CMD_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * Accept IR data spanning multiple rx buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * Reject MCE command response spanning multiple rx buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (ir->parser_state != PARSE_IRDATA || !ir->rem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ir->parser_state = CMD_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dev_dbg(ir->dev, "processed IR data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ir_raw_event_handle(ir->rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static void mceusb_dev_recv(struct urb *urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) struct mceusb_dev *ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (!urb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) ir = urb->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (!ir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) usb_unlink_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) switch (urb->status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) mceusb_process_ir_data(ir, urb->actual_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) case -ECONNRESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) case -ENOENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) case -EILSEQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) case -EPROTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) case -ESHUTDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) usb_unlink_urb(urb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) case -EPIPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) dev_err(ir->dev, "Error: urb status = %d (RX HALT)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) mceusb_defer_kevent(ir, EVENT_RX_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) dev_err(ir->dev, "Error: urb status = %d", urb->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) usb_submit_urb(urb, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static void mceusb_get_emulator_version(struct mceusb_dev *ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* If we get no reply or an illegal command reply, its ver 1, says MS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ir->emver = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) mce_command_out(ir, GET_EMVER, sizeof(GET_EMVER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static void mceusb_gen1_init(struct mceusb_dev *ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) struct device *dev = ir->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) char *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) data = kzalloc(USB_CTRL_MSG_SZ, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev_err(dev, "%s: memory allocation failed!", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * This is a strange one. Windows issues a set address to the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * on the receive control pipe and expect a certain value pair back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ret = usb_control_msg(ir->usbdev, usb_rcvctrlpipe(ir->usbdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) USB_REQ_SET_ADDRESS, USB_TYPE_VENDOR, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) data, USB_CTRL_MSG_SZ, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) dev_dbg(dev, "set address - ret = %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) dev_dbg(dev, "set address - data[0] = %d, data[1] = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) data[0], data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* set feature: bit rate 38400 bps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ret = usb_control_msg(ir->usbdev, usb_sndctrlpipe(ir->usbdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) USB_REQ_SET_FEATURE, USB_TYPE_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) 0xc04e, 0x0000, NULL, 0, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) dev_dbg(dev, "set feature - ret = %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* bRequest 4: set char length to 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ret = usb_control_msg(ir->usbdev, usb_sndctrlpipe(ir->usbdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) 4, USB_TYPE_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) 0x0808, 0x0000, NULL, 0, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) dev_dbg(dev, "set char length - retB = %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* bRequest 2: set handshaking to use DTR/DSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret = usb_control_msg(ir->usbdev, usb_sndctrlpipe(ir->usbdev, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) 2, USB_TYPE_VENDOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) 0x0000, 0x0100, NULL, 0, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dev_dbg(dev, "set handshake - retC = %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* device resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) mce_command_out(ir, DEVICE_RESUME, sizeof(DEVICE_RESUME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* get hw/sw revision? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) mce_command_out(ir, GET_REVISION, sizeof(GET_REVISION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static void mceusb_gen2_init(struct mceusb_dev *ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* device resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) mce_command_out(ir, DEVICE_RESUME, sizeof(DEVICE_RESUME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* get wake version (protocol, key, address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) mce_command_out(ir, GET_WAKEVERSION, sizeof(GET_WAKEVERSION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* unknown what this one actually returns... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) mce_command_out(ir, GET_UNKNOWN2, sizeof(GET_UNKNOWN2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static void mceusb_get_parameters(struct mceusb_dev *ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) unsigned char cmdbuf[3] = { MCE_CMD_PORT_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) MCE_CMD_GETPORTSTATUS, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* defaults, if the hardware doesn't support querying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) ir->num_txports = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ir->num_rxports = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* get number of tx and rx ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) mce_command_out(ir, GET_NUM_PORTS, sizeof(GET_NUM_PORTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* get the carrier and frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) mce_command_out(ir, GET_CARRIER_FREQ, sizeof(GET_CARRIER_FREQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (ir->num_txports && !ir->flags.no_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* get the transmitter bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) mce_command_out(ir, GET_TX_BITMASK, sizeof(GET_TX_BITMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* get receiver timeout value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) mce_command_out(ir, GET_RX_TIMEOUT, sizeof(GET_RX_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* get receiver sensor setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) mce_command_out(ir, GET_RX_SENSOR, sizeof(GET_RX_SENSOR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) for (i = 0; i < ir->num_txports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) cmdbuf[2] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) mce_command_out(ir, cmdbuf, sizeof(cmdbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static void mceusb_flash_led(struct mceusb_dev *ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (ir->emver < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) mce_command_out(ir, FLASH_LED, sizeof(FLASH_LED));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * Workqueue function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * for resetting or recovering device after occurrence of error events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * specified in ir->kevent bit field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * Function runs (via schedule_work()) in non-interrupt context, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * calls here (such as usb_clear_halt()) requiring non-interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static void mceusb_deferred_kevent(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct mceusb_dev *ir =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) container_of(work, struct mceusb_dev, kevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) dev_err(ir->dev, "kevent handler called (flags 0x%lx)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) ir->kevent_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (test_bit(EVENT_RST_PEND, &ir->kevent_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) dev_err(ir->dev, "kevent handler canceled pending USB Reset Device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if (test_bit(EVENT_RX_HALT, &ir->kevent_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) usb_unlink_urb(ir->urb_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) status = usb_clear_halt(ir->usbdev, ir->pipe_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) dev_err(ir->dev, "rx clear halt status = %d", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * Unable to clear RX halt/stall.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * Will need to call usb_reset_device().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) dev_err(ir->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) "stuck RX HALT state requires USB Reset Device to clear");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) usb_queue_reset_device(ir->usbintf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) set_bit(EVENT_RST_PEND, &ir->kevent_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) clear_bit(EVENT_RX_HALT, &ir->kevent_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /* Cancel all other error events and handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) clear_bit(EVENT_TX_HALT, &ir->kevent_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) clear_bit(EVENT_RX_HALT, &ir->kevent_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) status = usb_submit_urb(ir->urb_in, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dev_err(ir->dev, "rx unhalt submit urb error = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (test_bit(EVENT_TX_HALT, &ir->kevent_flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) status = usb_clear_halt(ir->usbdev, ir->pipe_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) dev_err(ir->dev, "tx clear halt status = %d", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * Unable to clear TX halt/stall.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * Will need to call usb_reset_device().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) dev_err(ir->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) "stuck TX HALT state requires USB Reset Device to clear");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) usb_queue_reset_device(ir->usbintf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) set_bit(EVENT_RST_PEND, &ir->kevent_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) clear_bit(EVENT_TX_HALT, &ir->kevent_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /* Cancel all other error events and handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) clear_bit(EVENT_RX_HALT, &ir->kevent_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) clear_bit(EVENT_TX_HALT, &ir->kevent_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static struct rc_dev *mceusb_init_rc_dev(struct mceusb_dev *ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) struct usb_device *udev = ir->usbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct device *dev = ir->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) struct rc_dev *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) rc = rc_allocate_device(RC_DRIVER_IR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) dev_err(dev, "remote dev allocation failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) snprintf(ir->name, sizeof(ir->name), "%s (%04x:%04x)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) mceusb_model[ir->model].name ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) mceusb_model[ir->model].name :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) "Media Center Ed. eHome Infrared Remote Transceiver",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) le16_to_cpu(ir->usbdev->descriptor.idVendor),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) le16_to_cpu(ir->usbdev->descriptor.idProduct));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) usb_make_path(ir->usbdev, ir->phys, sizeof(ir->phys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) rc->device_name = ir->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) rc->input_phys = ir->phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) usb_to_input_id(ir->usbdev, &rc->input_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) rc->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) rc->priv = ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) rc->min_timeout = MCE_TIME_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) rc->timeout = MS_TO_US(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (!mceusb_model[ir->model].broken_irtimeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) rc->s_timeout = mceusb_set_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) * If we can't set the timeout using CMD_SETIRTIMEOUT, we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * rely on software timeouts for timeouts < 100ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) rc->max_timeout = rc->timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (!ir->flags.no_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) rc->s_tx_mask = mceusb_set_tx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) rc->s_tx_carrier = mceusb_set_tx_carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) rc->tx_ir = mceusb_tx_ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (ir->flags.rx2 > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) rc->s_learning_mode = mceusb_set_rx_wideband;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) rc->s_carrier_report = mceusb_set_rx_carrier_report;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) rc->driver_name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) switch (le16_to_cpu(udev->descriptor.idVendor)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) case VENDOR_HAUPPAUGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) rc->map_name = RC_MAP_HAUPPAUGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) case VENDOR_PCTV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) rc->map_name = RC_MAP_PINNACLE_PCTV_HD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) rc->map_name = RC_MAP_RC6_MCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (mceusb_model[ir->model].rc_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) rc->map_name = mceusb_model[ir->model].rc_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) ret = rc_register_device(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) dev_err(dev, "remote dev registration failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) rc_free_device(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static int mceusb_dev_probe(struct usb_interface *intf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) const struct usb_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct usb_device *dev = interface_to_usbdev(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct usb_host_interface *idesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct usb_endpoint_descriptor *ep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) struct usb_endpoint_descriptor *ep_in = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) struct usb_endpoint_descriptor *ep_out = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) struct mceusb_dev *ir = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) int pipe, maxp, i, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) char buf[63], name[128] = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) enum mceusb_model_type model = id->driver_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) bool is_gen3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) bool is_microsoft_gen1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) bool tx_mask_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) int ir_intfnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) dev_dbg(&intf->dev, "%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) idesc = intf->cur_altsetting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) is_gen3 = mceusb_model[model].mce_gen3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) is_microsoft_gen1 = mceusb_model[model].mce_gen1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) tx_mask_normal = mceusb_model[model].tx_mask_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) ir_intfnum = mceusb_model[model].ir_intfnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* There are multi-function devices with non-IR interfaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (idesc->desc.bInterfaceNumber != ir_intfnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /* step through the endpoints to find first bulk in and out endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) for (i = 0; i < idesc->desc.bNumEndpoints; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ep = &idesc->endpoint[i].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (ep_in == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (usb_endpoint_is_bulk_in(ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ep_in = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) dev_dbg(&intf->dev, "acceptable bulk inbound endpoint found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) } else if (usb_endpoint_is_int_in(ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) ep_in = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) ep_in->bInterval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) dev_dbg(&intf->dev, "acceptable interrupt inbound endpoint found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (ep_out == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (usb_endpoint_is_bulk_out(ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ep_out = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) dev_dbg(&intf->dev, "acceptable bulk outbound endpoint found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) } else if (usb_endpoint_is_int_out(ep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ep_out = ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ep_out->bInterval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) dev_dbg(&intf->dev, "acceptable interrupt outbound endpoint found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (!ep_in || !ep_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) dev_dbg(&intf->dev, "required endpoints not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (usb_endpoint_xfer_int(ep_in))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) pipe = usb_rcvintpipe(dev, ep_in->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) pipe = usb_rcvbulkpipe(dev, ep_in->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) maxp = usb_maxpacket(dev, pipe, usb_pipeout(pipe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) ir = kzalloc(sizeof(struct mceusb_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (!ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) goto mem_alloc_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) ir->pipe_in = pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) ir->buf_in = usb_alloc_coherent(dev, maxp, GFP_KERNEL, &ir->dma_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (!ir->buf_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) goto buf_in_alloc_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) ir->urb_in = usb_alloc_urb(0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (!ir->urb_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) goto urb_in_alloc_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) ir->usbintf = intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) ir->usbdev = usb_get_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) ir->dev = &intf->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ir->len_in = maxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) ir->flags.microsoft_gen1 = is_microsoft_gen1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) ir->flags.tx_mask_normal = tx_mask_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) ir->flags.no_tx = mceusb_model[model].no_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) ir->flags.rx2 = mceusb_model[model].rx2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) ir->model = model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) /* Saving usb interface data for use by the transmitter routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) ir->usb_ep_out = ep_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (usb_endpoint_xfer_int(ep_out))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) ir->pipe_out = usb_sndintpipe(ir->usbdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) ep_out->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ir->pipe_out = usb_sndbulkpipe(ir->usbdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) ep_out->bEndpointAddress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (dev->descriptor.iManufacturer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) && usb_string(dev, dev->descriptor.iManufacturer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) buf, sizeof(buf)) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) strscpy(name, buf, sizeof(name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (dev->descriptor.iProduct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) && usb_string(dev, dev->descriptor.iProduct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) buf, sizeof(buf)) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) snprintf(name + strlen(name), sizeof(name) - strlen(name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) " %s", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * Initialize async USB error handler before registering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) * or activating any mceusb RX and TX functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) INIT_WORK(&ir->kevent, mceusb_deferred_kevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) ir->rc = mceusb_init_rc_dev(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (!ir->rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) goto rc_dev_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) /* wire up inbound data handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (usb_endpoint_xfer_int(ep_in))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) usb_fill_int_urb(ir->urb_in, dev, pipe, ir->buf_in, maxp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) mceusb_dev_recv, ir, ep_in->bInterval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) usb_fill_bulk_urb(ir->urb_in, dev, pipe, ir->buf_in, maxp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) mceusb_dev_recv, ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) ir->urb_in->transfer_dma = ir->dma_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) ir->urb_in->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* flush buffers on the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) dev_dbg(&intf->dev, "Flushing receive buffers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) res = usb_submit_urb(ir->urb_in, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) dev_err(&intf->dev, "failed to flush buffers: %d", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /* figure out which firmware/emulator version this hardware has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) mceusb_get_emulator_version(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) /* initialize device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (ir->flags.microsoft_gen1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) mceusb_gen1_init(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) else if (!is_gen3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) mceusb_gen2_init(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) mceusb_get_parameters(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) mceusb_flash_led(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (!ir->flags.no_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) mceusb_set_tx_mask(ir->rc, MCE_DEFAULT_TX_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) usb_set_intfdata(intf, ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /* enable wake via this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) device_set_wakeup_capable(ir->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) device_set_wakeup_enable(ir->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) dev_info(&intf->dev, "Registered %s with mce emulator interface version %x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) name, ir->emver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) dev_info(&intf->dev, "%x tx ports (0x%x cabled) and %x rx sensors (0x%x active)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ir->num_txports, ir->txports_cabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ir->num_rxports, ir->rxports_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* Error-handling path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) rc_dev_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) cancel_work_sync(&ir->kevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) usb_put_dev(ir->usbdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) usb_kill_urb(ir->urb_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) usb_free_urb(ir->urb_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) urb_in_alloc_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) usb_free_coherent(dev, maxp, ir->buf_in, ir->dma_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) buf_in_alloc_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) kfree(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) mem_alloc_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dev_err(&intf->dev, "%s: device setup failed!", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static void mceusb_dev_disconnect(struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) struct usb_device *dev = interface_to_usbdev(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) struct mceusb_dev *ir = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) dev_dbg(&intf->dev, "%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) usb_set_intfdata(intf, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (!ir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ir->usbdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) cancel_work_sync(&ir->kevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) rc_unregister_device(ir->rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) usb_kill_urb(ir->urb_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) usb_free_urb(ir->urb_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) usb_free_coherent(dev, ir->len_in, ir->buf_in, ir->dma_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) usb_put_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) kfree(ir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) static int mceusb_dev_suspend(struct usb_interface *intf, pm_message_t message)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) struct mceusb_dev *ir = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) dev_info(ir->dev, "suspend");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) usb_kill_urb(ir->urb_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static int mceusb_dev_resume(struct usb_interface *intf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) struct mceusb_dev *ir = usb_get_intfdata(intf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) dev_info(ir->dev, "resume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (usb_submit_urb(ir->urb_in, GFP_ATOMIC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static struct usb_driver mceusb_dev_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .probe = mceusb_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .disconnect = mceusb_dev_disconnect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .suspend = mceusb_dev_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .resume = mceusb_dev_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .reset_resume = mceusb_dev_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .id_table = mceusb_dev_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) module_usb_driver(mceusb_dev_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) MODULE_DESCRIPTION(DRIVER_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) MODULE_AUTHOR(DRIVER_AUTHOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) MODULE_DEVICE_TABLE(usb, mceusb_dev_table);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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