Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for ITE Tech Inc. IT8712F/IT8512F CIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) /* platform driver name to register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define ITE_DRIVER_NAME "ite-cir"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* logging macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define ite_pr(level, text, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define ite_dbg(text, ...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 		printk(KERN_DEBUG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define ite_dbg_verbose(text, ...) do {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	if (debug > 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 		printk(KERN_DEBUG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* FIFO sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define ITE_TX_FIFO_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ITE_RX_FIFO_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* interrupt types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ITE_IRQ_TX_FIFO        1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ITE_IRQ_RX_FIFO        2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ITE_IRQ_RX_FIFO_OVERRUN    4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* forward declaration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct ite_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* struct for storing the parameters of different recognized devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct ite_dev_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	/* model of the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	const char *model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/* size of the I/O region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int io_region_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* IR pnp I/O resource number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int io_rsrc_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	/* true if the hardware supports transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	bool hw_tx_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* base sampling period, in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u32 sample_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* rx low carrier frequency, in Hz, 0 means no demodulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned int rx_low_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/* tx high carrier frequency, in Hz, 0 means no demodulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned int rx_high_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* tx carrier frequency, in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	unsigned int tx_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	/* duty cycle, 0-100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int tx_duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* hw-specific operation function pointers; most of these must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	 * called while holding the spin lock, except for the TX FIFO length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* get pending interrupt causes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int (*get_irq_causes) (struct ite_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* enable rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	void (*enable_rx) (struct ite_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* make rx enter the idle state; keep listening for a pulse, but stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * streaming space bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	void (*idle_rx) (struct ite_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	/* disable rx completely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	void (*disable_rx) (struct ite_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* read bytes from RX FIFO; return read count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	int (*get_rx_bytes) (struct ite_dev *dev, u8 *buf, int buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* enable tx FIFO space available interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	void (*enable_tx_interrupt) (struct ite_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* disable tx FIFO space available interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	void (*disable_tx_interrupt) (struct ite_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* get number of full TX FIFO slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	int (*get_tx_used_slots) (struct ite_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* put a byte to the TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	void (*put_tx_byte) (struct ite_dev *dev, u8 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* disable hardware completely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	void (*disable) (struct ite_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* initialize the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	void (*init_hardware) (struct ite_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* set the carrier parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	void (*set_carrier_params) (struct ite_dev *dev, bool high_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				    bool use_demodulator, u8 carrier_freq_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				    u8 allowance_bits, u8 pulse_width_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* ITE CIR device structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct ite_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct pnp_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct rc_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct ir_raw_event rawir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/* sync data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	bool in_use, transmitting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* transmit support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	int tx_fifo_allowance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	wait_queue_head_t tx_queue, tx_ended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* hardware I/O settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned long cir_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int cir_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* overridable copy of model parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct ite_dev_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* common values for all kinds of hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* baud rate divisor default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ITE_BAUDRATE_DIVISOR		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* low-speed carrier frequency limits (Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ITE_LCF_MIN_CARRIER_FREQ	27000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ITE_LCF_MAX_CARRIER_FREQ	58000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* high-speed carrier frequency limits (Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ITE_HCF_MIN_CARRIER_FREQ	400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ITE_HCF_MAX_CARRIER_FREQ	500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* default carrier freq for when demodulator is off (Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ITE_DEFAULT_CARRIER_FREQ	38000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* convert bits to us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ITE_BITS_TO_US(bits, sample_period) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ((u32)((bits) * ITE_BAUDRATE_DIVISOR * (sample_period) / 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * n in RDCR produces a tolerance of +/- n * 6.25% around the center
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * carrier frequency...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * From two limit frequencies, L (low) and H (high), we can get both the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * center frequency F = (L + H) / 2 and the variation from the center
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * frequency A = (H - L) / (H + L). We can use this in order to honor the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * s_rx_carrier_range() call in ir-core. We'll suppose that any request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  * setting L=0 means we must shut down the demodulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ITE_RXDCR_PER_10000_STEP 625
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* high speed carrier freq values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ITE_CFQ_400		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ITE_CFQ_450		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ITE_CFQ_480		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ITE_CFQ_500		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* values for pulse widths */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ITE_TXMPW_A		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ITE_TXMPW_B		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ITE_TXMPW_C		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ITE_TXMPW_D		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ITE_TXMPW_E		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* values for demodulator carrier range allowance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ITE_RXDCR_DEFAULT	0x01	/* default carrier range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ITE_RXDCR_MAX		0x07	/* default carrier range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* DR TX bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ITE_TX_PULSE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ITE_TX_SPACE		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ITE_TX_MAX_RLE		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ITE_TX_RLE_MASK		0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * IT8712F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * hardware data obtained from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * IT8712F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * Environment Control – Low Pin Count Input / Output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * (EC - LPC I/O)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * Preliminary Specification V0. 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IT87_DR		0x00	/* data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IT87_IER	0x01	/* interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IT87_RCR	0x02	/* receiver control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IT87_TCR1	0x03	/* transmitter control register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IT87_TCR2	0x04	/* transmitter control register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IT87_TSR	0x05	/* transmitter status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IT87_RSR	0x06	/* receiver status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IT87_BDLR	0x05	/* baud rate divisor low byte register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IT87_BDHR	0x06	/* baud rate divisor high byte register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IT87_IIR	0x07	/* interrupt identification register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IT87_IOREG_LENGTH 0x08	/* length of register file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* IER bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IT87_TLDLIE	0x01	/* transmitter low data interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IT87_RDAIE	0x02	/* receiver data available interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IT87_RFOIE	0x04	/* receiver FIFO overrun interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IT87_IEC	0x08	/* interrupt enable control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IT87_BR		0x10	/* baud rate register enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IT87_RESET	0x20	/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* RCR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IT87_RXDCR	0x07	/* receiver demodulation carrier range mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IT87_RXACT	0x08	/* receiver active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IT87_RXEND	0x10	/* receiver demodulation enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IT87_RXEN	0x20	/* receiver enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IT87_HCFS	0x40	/* high-speed carrier frequency select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IT87_RDWOS	0x80	/* receiver data without sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* TCR1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IT87_TXMPM	0x03	/* transmitter modulation pulse mode mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IT87_TXMPM_DEFAULT 0x00	/* modulation pulse mode default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IT87_TXENDF	0x04	/* transmitter deferral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IT87_TXRLE	0x08	/* transmitter run length enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IT87_FIFOTL	0x30	/* FIFO level threshold mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IT87_FIFOTL_DEFAULT 0x20	/* FIFO level threshold default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 					 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 					 * 0x30 -> 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IT87_ILE	0x40	/* internal loopback enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IT87_FIFOCLR	0x80	/* FIFO clear bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* TCR2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IT87_TXMPW	0x07	/* transmitter modulation pulse width mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IT87_TXMPW_DEFAULT 0x04	/* default modulation pulse width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IT87_CFQ	0xf8	/* carrier frequency mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IT87_CFQ_SHIFT	3	/* carrier frequency bit shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* TSR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IT87_TXFBC	0x3f	/* transmitter FIFO byte count mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* RSR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IT87_RXFBC	0x3f	/* receiver FIFO byte count mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IT87_RXFTO	0x80	/* receiver FIFO time-out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* IIR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IT87_IP		0x01	/* interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IT87_II		0x06	/* interrupt identification mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IT87_II_NOINT	0x00	/* no interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IT87_II_TXLDL	0x02	/* transmitter low data level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IT87_II_RXDS	0x04	/* receiver data stored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IT87_II_RXFO	0x06	/* receiver FIFO overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  * IT8512E/F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  * Hardware data obtained from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  * IT8512E/F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  * Embedded Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  * Preliminary Specification V0.4.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  * Note that the CIR registers are not directly available to the host, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * they only are accessible to the integrated microcontroller. Thus, in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * use it, some kind of bridging is required. As the bridging may depend on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * the controller firmware in use, we are going to use the PNP ID in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * determine the strategy and ports available. See after these generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * IT8512E/F register definitions for register definitions for those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * strategies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IT85_C0DR	0x00	/* data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IT85_C0MSTCR	0x01	/* master control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IT85_C0IER	0x02	/* interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IT85_C0IIR	0x03	/* interrupt identification register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IT85_C0CFR	0x04	/* carrier frequency register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IT85_C0RCR	0x05	/* receiver control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IT85_C0TCR	0x06	/* transmitter control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IT85_C0SCK	0x07	/* slow clock control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IT85_C0BDLR	0x08	/* baud rate divisor low byte register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IT85_C0BDHR	0x09	/* baud rate divisor high byte register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IT85_C0TFSR	0x0a	/* transmitter FIFO status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IT85_C0RFSR	0x0b	/* receiver FIFO status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IT85_C0WCL	0x0d	/* wakeup code length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IT85_C0WCR	0x0e	/* wakeup code read/write register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IT85_C0WPS	0x0f	/* wakeup power control/status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IT85_IOREG_LENGTH 0x10	/* length of register file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* C0MSTCR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IT85_RESET	0x01	/* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IT85_FIFOCLR	0x02	/* FIFO clear bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IT85_FIFOTL	0x0c	/* FIFO level threshold mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IT85_FIFOTL_DEFAULT 0x08	/* FIFO level threshold default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 					 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 					 * 0x0c -> 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IT85_ILE	0x10	/* internal loopback enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IT85_ILSEL	0x20	/* internal loopback select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* C0IER bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IT85_TLDLIE	0x01	/* TX low data level interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IT85_RDAIE	0x02	/* RX data available interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IT85_RFOIE	0x04	/* RX FIFO overrun interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IT85_IEC	0x80	/* interrupt enable function control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* C0IIR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IT85_TLDLI	0x01	/* transmitter low data level interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IT85_RDAI	0x02	/* receiver data available interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IT85_RFOI	0x04	/* receiver FIFO overrun interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IT85_NIP	0x80	/* no interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* C0CFR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IT85_CFQ	0x1f	/* carrier frequency mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IT85_HCFS	0x20	/* high speed carrier frequency select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* C0RCR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IT85_RXDCR	0x07	/* receiver demodulation carrier range mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IT85_RXACT	0x08	/* receiver active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IT85_RXEND	0x10	/* receiver demodulation enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IT85_RDWOS	0x20	/* receiver data without sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IT85_RXEN	0x80	/* receiver enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* C0TCR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IT85_TXMPW	0x07	/* transmitter modulation pulse width mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IT85_TXMPW_DEFAULT 0x04	/* default modulation pulse width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IT85_TXMPM	0x18	/* transmitter modulation pulse mode mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IT85_TXMPM_DEFAULT 0x00	/* modulation pulse mode default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IT85_TXENDF	0x20	/* transmitter deferral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IT85_TXRLE	0x40	/* transmitter run length enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* C0SCK bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IT85_SCKS	0x01	/* slow clock select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IT85_TXDCKG	0x02	/* TXD clock gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IT85_DLL1P8E	0x04	/* DLL 1.8432M enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IT85_DLLTE	0x08	/* DLL test enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IT85_BRCM	0x70	/* baud rate count mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IT85_DLLOCK	0x80	/* DLL lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* C0TFSR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IT85_TXFBC	0x3f	/* transmitter FIFO count mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* C0RFSR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IT85_RXFBC	0x3f	/* receiver FIFO count mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IT85_RXFTO	0x80	/* receiver FIFO time-out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* C0WCL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IT85_WCL	0x3f	/* wakeup code length mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* C0WPS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IT85_CIRPOSIE	0x01	/* power on/off status interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IT85_CIRPOIS	0x02	/* power on/off interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IT85_CIRPOII	0x04	/* power on/off interrupt identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define IT85_RCRST	0x10	/* wakeup code reading counter reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define IT85_WCRST	0x20	/* wakeup code writing counter reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  * ITE8708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)  * Hardware data obtained from hacked driver for IT8512 in this forum post:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)  *  http://ubuntuforums.org/showthread.php?t=1028640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)  * Although there's no official documentation for that driver, analysis would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)  * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)  * selectable by a single bank-select bit that's mapped onto both banks. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)  * IT8512 registers are mapped in a different order, so that the first bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)  * maps the ones that are used more often, and two registers that share a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)  * reserved high-order bit are placed at the same offset in both banks in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)  * order to reuse the reserved bit as the bank select bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* mapped onto both banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IT8708_BANKSEL	0x07	/* bank select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IT8708_HRAE	0x80	/* high registers access enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* mapped onto the low bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define IT8708_C0DR	0x00	/* data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IT8708_C0MSTCR	0x01	/* master control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define IT8708_C0IER	0x02	/* interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IT8708_C0IIR	0x03	/* interrupt identification register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IT8708_C0RFSR	0x04	/* receiver FIFO status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IT8708_C0RCR	0x05	/* receiver control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IT8708_C0TFSR	0x06	/* transmitter FIFO status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define IT8708_C0TCR	0x07	/* transmitter control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* mapped onto the high bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IT8708_C0BDLR	0x01	/* baud rate divisor low byte register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IT8708_C0BDHR	0x02	/* baud rate divisor high byte register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define IT8708_C0CFR	0x04	/* carrier frequency register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* registers whose bank mapping we don't know, since they weren't being used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)  * in the hacked driver... most probably they belong to the high bank too,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)  * since they fit in the holes the other registers leave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define IT8708_C0SCK	0x03	/* slow clock control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define IT8708_C0WCL	0x05	/* wakeup code length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define IT8708_C0WCR	0x06	/* wakeup code read/write register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define IT8708_C0WPS	0x07	/* wakeup power control/status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define IT8708_IOREG_LENGTH 0x08	/* length of register file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* two more registers that are defined in the hacked driver, but can't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)  * found in the data sheets; no idea what they are or how they are accessed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)  * since the hacked driver doesn't seem to use them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define IT8708_CSCRR	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define IT8708_CGPINTR	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* CSCRR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define IT8708_CSCRR_SCRB 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define IT8708_CSCRR_PM	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* CGPINTR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define IT8708_CGPINT	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)  * ITE8709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)  * Hardware interfacing data obtained from the original lirc_ite8709 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)  * Verbatim from its sources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)  * The ITE8709 device seems to be the combination of IT8512 superIO chip and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)  * a specific firmware running on the IT8512's embedded micro-controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)  * In addition of the embedded micro-controller, the IT8512 chip contains a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)  * CIR module and several other modules. A few modules are directly accessible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)  * by the host CPU, but most of them are only accessible by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)  * micro-controller. The CIR module is only accessible by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)  * micro-controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)  * The battery-backed SRAM module is accessible by the host CPU and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)  * micro-controller. So one of the MC's firmware role is to act as a bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)  * between the host CPU and the CIR module. The firmware implements a kind of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)  * communication protocol using the SRAM module as a shared memory. The IT8512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)  * specification is publicly available on ITE's web site, but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)  * communication protocol is not, so it was reverse-engineered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define IT8709_RAM_IDX	0x00	/* index into the SRAM module bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define IT8709_RAM_VAL	0x01	/* read/write data to the indexed byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define IT8709_IOREG_LENGTH 0x02	/* length of register file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* register offsets inside the SRAM module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define IT8709_MODE	0x1a	/* request/ack byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define IT8709_REG_IDX	0x1b	/* index of the CIR register to access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define IT8709_REG_VAL	0x1c	/* value read/to be written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define IT8709_IIR	0x1e	/* interrupt identification register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define IT8709_RFSR	0x1f	/* receiver FIFO status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define IT8709_FIFO	0x20	/* start of in RAM RX FIFO copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* MODE values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define IT8709_IDLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define IT8709_WRITE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define IT8709_READ	0x02