^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for ITE Tech Inc. IT8712F/IT8512 CIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Inspired by the original lirc_it87 and lirc_ite8709 drivers, on top of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * skeleton provided by the nuvoton-cir driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The lirc_it87 driver was originally written by Hans-Gunter Lutke Uphues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * <hg_lu@web.de> in 2001, with enhancements by Christoph Bartelmus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * <lirc@bartelmus.de>, Andrew Calkin <r_tay@hotmail.com> and James Edwards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * <jimbo-lirc@edwardsclan.net>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The lirc_ite8709 driver was written by Grégory Lardière
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * <spmf2004-lirc@yahoo.fr> in 2008.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pnp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "ite-cir.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* module parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* debug level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) module_param(debug, int, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MODULE_PARM_DESC(debug, "Enable debugging output");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* low limit for RX carrier freq, Hz, 0 for no RX demodulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int rx_low_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) module_param(rx_low_carrier_freq, int, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MODULE_PARM_DESC(rx_low_carrier_freq, "Override low RX carrier frequency, Hz, 0 for no RX demodulation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* high limit for RX carrier freq, Hz, 0 for no RX demodulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int rx_high_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) module_param(rx_high_carrier_freq, int, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_PARM_DESC(rx_high_carrier_freq, "Override high RX carrier frequency, Hz, 0 for no RX demodulation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* override tx carrier frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int tx_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) module_param(tx_carrier_freq, int, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_PARM_DESC(tx_carrier_freq, "Override TX carrier frequency, Hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* override tx duty cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int tx_duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) module_param(tx_duty_cycle, int, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_PARM_DESC(tx_duty_cycle, "Override TX duty cycle, 1-100");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* override default sample period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static long sample_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) module_param(sample_period, long, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MODULE_PARM_DESC(sample_period, "Override carrier sample period, us");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* override detected model id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int model_number = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) module_param(model_number, int, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MODULE_PARM_DESC(model_number, "Use this model number, don't autodetect");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* HW-independent code functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* check whether carrier frequency is high frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline bool ite_is_high_carrier_freq(unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return freq >= ITE_HCF_MIN_CARRIER_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* get the bits required to program the carrier frequency in CFQ bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * unshifted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static u8 ite_get_carrier_freq_bits(unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ite_is_high_carrier_freq(freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (freq < 425000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return ITE_CFQ_400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) else if (freq < 465000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ITE_CFQ_450;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else if (freq < 490000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ITE_CFQ_480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ITE_CFQ_500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* trim to limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (freq < ITE_LCF_MIN_CARRIER_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) freq = ITE_LCF_MIN_CARRIER_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (freq > ITE_LCF_MAX_CARRIER_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) freq = ITE_LCF_MAX_CARRIER_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* convert to kHz and subtract the base freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DIV_ROUND_CLOSEST(freq - ITE_LCF_MIN_CARRIER_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return (u8) freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* get the bits required to program the pulse with in TXMPW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static u8 ite_get_pulse_width_bits(unsigned int freq, int duty_cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long period_ns, on_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* sanitize freq into range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (freq < ITE_LCF_MIN_CARRIER_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) freq = ITE_LCF_MIN_CARRIER_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (freq > ITE_HCF_MAX_CARRIER_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) freq = ITE_HCF_MAX_CARRIER_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) period_ns = 1000000000UL / freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) on_ns = period_ns * duty_cycle / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ite_is_high_carrier_freq(freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (on_ns < 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ITE_TXMPW_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) else if (on_ns < 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ITE_TXMPW_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else if (on_ns < 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return ITE_TXMPW_C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) else if (on_ns < 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ITE_TXMPW_D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ITE_TXMPW_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (on_ns < 6500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return ITE_TXMPW_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) else if (on_ns < 7850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ITE_TXMPW_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) else if (on_ns < 9650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ITE_TXMPW_C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) else if (on_ns < 11950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ITE_TXMPW_D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ITE_TXMPW_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* decode raw bytes as received by the hardware, and push them to the ir-core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void ite_decode_bytes(struct ite_dev *dev, const u8 * data, int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 sample_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long *ldata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int next_one, next_zero, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct ir_raw_event ev = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (length == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sample_period = dev->params.sample_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ldata = (unsigned long *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) size = length << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) next_one = find_next_bit_le(ldata, size, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (next_one > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ev.pulse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ev.duration =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ITE_BITS_TO_US(next_one, sample_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ir_raw_event_store_with_filter(dev->rdev, &ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) while (next_one < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) next_zero = find_next_zero_bit_le(ldata, size, next_one + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ev.pulse = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ev.duration = ITE_BITS_TO_US(next_zero - next_one, sample_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ir_raw_event_store_with_filter(dev->rdev, &ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (next_zero < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) next_one =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) find_next_bit_le(ldata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) next_zero + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ev.pulse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ev.duration =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ITE_BITS_TO_US(next_one - next_zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sample_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ir_raw_event_store_with_filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) (dev->rdev, &ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) next_one = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ir_raw_event_handle(dev->rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ite_dbg_verbose("decoded %d bytes.", length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* set all the rx/tx carrier parameters; this must be called with the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void ite_set_carrier_params(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned int freq, low_freq, high_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int allowance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) bool use_demodulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bool for_tx = dev->transmitting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (for_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* we don't need no stinking calculations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) freq = dev->params.tx_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) allowance = ITE_RXDCR_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) use_demodulator = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) low_freq = dev->params.rx_low_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) high_freq = dev->params.rx_high_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (low_freq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* don't demodulate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ITE_DEFAULT_CARRIER_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) allowance = ITE_RXDCR_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) use_demodulator = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* calculate the middle freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) freq = (low_freq + high_freq) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* calculate the allowance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) allowance =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DIV_ROUND_CLOSEST(10000 * (high_freq - low_freq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ITE_RXDCR_PER_10000_STEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * (high_freq + low_freq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (allowance < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) allowance = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (allowance > ITE_RXDCR_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) allowance = ITE_RXDCR_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) use_demodulator = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* set the carrier parameters in a device-dependent way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev->params.set_carrier_params(dev, ite_is_high_carrier_freq(freq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) use_demodulator, ite_get_carrier_freq_bits(freq), allowance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ite_get_pulse_width_bits(freq, dev->params.tx_duty_cycle));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* interrupt service routine for incoming and outgoing CIR data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static irqreturn_t ite_cir_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct ite_dev *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) irqreturn_t ret = IRQ_RETVAL(IRQ_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 rx_buf[ITE_RX_FIFO_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ite_dbg_verbose("%s firing", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* grab the spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* read the interrupt flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) iflags = dev->params.get_irq_causes(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Check for RX overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (iflags & ITE_IRQ_RX_FIFO_OVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_warn(&dev->rdev->dev, "receive overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ir_raw_event_reset(dev->rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* check for the receive interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (iflags & (ITE_IRQ_RX_FIFO | ITE_IRQ_RX_FIFO_OVERRUN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* read the FIFO bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) rx_bytes =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev->params.get_rx_bytes(dev, rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ITE_RX_FIFO_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (rx_bytes > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* drop the spinlock, since the ir-core layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * may call us back again through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * ite_s_idle() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) spin_unlock_irqrestore(&dev->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* decode the data we've just received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ite_decode_bytes(dev, rx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) rx_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* reacquire the spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) spin_lock_irqsave(&dev->lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* mark the interrupt as serviced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = IRQ_RETVAL(IRQ_HANDLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } else if (iflags & ITE_IRQ_TX_FIFO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* FIFO space available interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ite_dbg_verbose("got interrupt for TX FIFO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* wake any sleeping transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) wake_up_interruptible(&dev->tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* mark the interrupt as serviced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = IRQ_RETVAL(IRQ_HANDLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* drop the spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ite_dbg_verbose("%s done returning %d", __func__, (int)ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* set the rx carrier freq range, guess it's in Hz... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int ite_set_rx_carrier_range(struct rc_dev *rcdev, u32 carrier_low, u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) carrier_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct ite_dev *dev = rcdev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev->params.rx_low_carrier_freq = carrier_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev->params.rx_high_carrier_freq = carrier_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ite_set_carrier_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* set the tx carrier freq, guess it's in Hz... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int ite_set_tx_carrier(struct rc_dev *rcdev, u32 carrier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct ite_dev *dev = rcdev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev->params.tx_carrier_freq = carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ite_set_carrier_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* set the tx duty cycle by controlling the pulse width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int ite_set_tx_duty_cycle(struct rc_dev *rcdev, u32 duty_cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct ite_dev *dev = rcdev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev->params.tx_duty_cycle = duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ite_set_carrier_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* transmit out IR pulses; what you get here is a batch of alternating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * pulse/space/pulse/space lengths that we should write out completely through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * the FIFO, blocking on a full FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int ite_tx_ir(struct rc_dev *rcdev, unsigned *txbuf, unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct ite_dev *dev = rcdev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bool is_pulse = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int remaining_us, fifo_avail, fifo_remaining, last_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int max_rle_us, next_rle_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u8 last_sent[ITE_TX_FIFO_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* clear the array just in case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) memset(last_sent, 0, sizeof(last_sent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* let everybody know we're now transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev->transmitting = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* and set the carrier values for transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ite_set_carrier_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* calculate how much time we can send in one byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) max_rle_us =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) (ITE_BAUDRATE_DIVISOR * dev->params.sample_period *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ITE_TX_MAX_RLE) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* disable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev->params.disable_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* this is where we'll begin filling in the FIFO, until it's full.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * then we'll just activate the interrupt, wait for it to wake us up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * again, disable it, continue filling the FIFO... until everything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * has been pushed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) fifo_avail =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ITE_TX_FIFO_LEN - dev->params.get_tx_used_slots(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) while (n > 0 && dev->in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* transmit the next sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) is_pulse = !is_pulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) remaining_us = *(txbuf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) n--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ite_dbg("%s: %ld",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ((is_pulse) ? "pulse" : "space"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) (long int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) remaining_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* repeat while the pulse is non-zero length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) while (remaining_us > 0 && dev->in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (remaining_us > max_rle_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) next_rle_us = max_rle_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) next_rle_us = remaining_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) remaining_us -= next_rle_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* check what's the length we have to pump out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) val = (ITE_TX_MAX_RLE * next_rle_us) / max_rle_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* put it into the sent buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) last_sent[last_idx++] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) last_idx &= (ITE_TX_FIFO_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* encode it for 7 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val = (val - 1) & ITE_TX_RLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* take into account pulse/space prefix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (is_pulse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) val |= ITE_TX_PULSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) val |= ITE_TX_SPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * if we get to 0 available, read again, just in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * some other slot got freed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (fifo_avail <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) fifo_avail = ITE_TX_FIFO_LEN - dev->params.get_tx_used_slots(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* if it's still full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (fifo_avail <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* enable the tx interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev->params.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) enable_tx_interrupt(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* drop the spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* wait for the FIFO to empty enough */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) wait_event_interruptible(dev->tx_queue, (fifo_avail = ITE_TX_FIFO_LEN - dev->params.get_tx_used_slots(dev)) >= 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* get the spinlock again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* disable the tx interrupt again. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev->params.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) disable_tx_interrupt(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* now send the byte through the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev->params.put_tx_byte(dev, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) fifo_avail--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* wait and don't return until the whole FIFO has been sent out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * otherwise we could configure the RX carrier params instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * TX ones while the transmission is still being performed! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) fifo_remaining = dev->params.get_tx_used_slots(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) remaining_us = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) while (fifo_remaining > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) fifo_remaining--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) last_idx--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) last_idx &= (ITE_TX_FIFO_LEN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) remaining_us += last_sent[last_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) remaining_us = (remaining_us * max_rle_us) / (ITE_TX_MAX_RLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* drop the spinlock while we sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* sleep remaining_us microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mdelay(DIV_ROUND_UP(remaining_us, 1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* reacquire the spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* now we're not transmitting anymore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev->transmitting = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* and set the carrier values for reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ite_set_carrier_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* re-enable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (dev->in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev->params.enable_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* notify transmission end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) wake_up_interruptible(&dev->tx_ended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* idle the receiver if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void ite_s_idle(struct rc_dev *rcdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct ite_dev *dev = rcdev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev->params.idle_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* IT8712F HW-specific functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* retrieve a bitmask of the current causes for a pending interrupt; this may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int it87_get_irq_causes(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u8 iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* read the interrupt flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) iflags = inb(dev->cir_addr + IT87_IIR) & IT87_II;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) switch (iflags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case IT87_II_RXDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret = ITE_IRQ_RX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case IT87_II_RXFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = ITE_IRQ_RX_FIFO_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case IT87_II_TXLDL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = ITE_IRQ_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* set the carrier parameters; to be called with the spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void it87_set_carrier_params(struct ite_dev *dev, bool high_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) bool use_demodulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u8 carrier_freq_bits, u8 allowance_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u8 pulse_width_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* program the RCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) val = inb(dev->cir_addr + IT87_RCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) & ~(IT87_HCFS | IT87_RXEND | IT87_RXDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (high_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) val |= IT87_HCFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (use_demodulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) val |= IT87_RXEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) val |= allowance_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) outb(val, dev->cir_addr + IT87_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* program the TCR2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) outb((carrier_freq_bits << IT87_CFQ_SHIFT) | pulse_width_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev->cir_addr + IT87_TCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int it87_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int fifo, read = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* read how many bytes are still in the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) fifo = inb(dev->cir_addr + IT87_RSR) & IT87_RXFBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) while (fifo > 0 && buf_size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *(buf++) = inb(dev->cir_addr + IT87_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) fifo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) read++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) buf_size--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* return how many bytes are still in the FIFO; this will be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * with the device spinlock NOT HELD while waiting for the TX FIFO to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * empty; let's expect this won't be a problem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int it87_get_tx_used_slots(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return inb(dev->cir_addr + IT87_TSR) & IT87_TXFBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* put a byte to the TX fifo; this should be called with the spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static void it87_put_tx_byte(struct ite_dev *dev, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) outb(value, dev->cir_addr + IT87_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* idle the receiver so that we won't receive samples until another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) pulse is detected; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void it87_idle_rx(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* disable streaming by clearing RXACT writing it as 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev->cir_addr + IT87_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* clear the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) outb(inb(dev->cir_addr + IT87_TCR1) | IT87_FIFOCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dev->cir_addr + IT87_TCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* disable the receiver; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static void it87_disable_rx(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* disable the receiver interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) outb(inb(dev->cir_addr + IT87_IER) & ~(IT87_RDAIE | IT87_RFOIE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dev->cir_addr + IT87_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* disable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) outb(inb(dev->cir_addr + IT87_RCR) & ~IT87_RXEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev->cir_addr + IT87_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* clear the FIFO and RXACT (actually RXACT should have been cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * in the previous outb() call) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) it87_idle_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* enable the receiver; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static void it87_enable_rx(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* enable the receiver by setting RXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev->cir_addr + IT87_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* just prepare it to idle for the next reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) it87_idle_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* enable the receiver interrupts and master enable flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) outb(inb(dev->cir_addr + IT87_IER) | IT87_RDAIE | IT87_RFOIE | IT87_IEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev->cir_addr + IT87_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* disable the transmitter interrupt; this must be called with the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void it87_disable_tx_interrupt(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* disable the transmitter interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) outb(inb(dev->cir_addr + IT87_IER) & ~IT87_TLDLIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev->cir_addr + IT87_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* enable the transmitter interrupt; this must be called with the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void it87_enable_tx_interrupt(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* enable the transmitter interrupts and master enable flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) outb(inb(dev->cir_addr + IT87_IER) | IT87_TLDLIE | IT87_IEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev->cir_addr + IT87_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* disable the device; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static void it87_disable(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* clear out all interrupt enable flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) outb(inb(dev->cir_addr + IT87_IER) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ~(IT87_IEC | IT87_RFOIE | IT87_RDAIE | IT87_TLDLIE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev->cir_addr + IT87_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* disable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) it87_disable_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* erase the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) outb(IT87_FIFOCLR | inb(dev->cir_addr + IT87_TCR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev->cir_addr + IT87_TCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* initialize the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static void it87_init_hardware(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* enable just the baud rate divisor register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) disabling all the interrupts at the same time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) outb((inb(dev->cir_addr + IT87_IER) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ~(IT87_IEC | IT87_RFOIE | IT87_RDAIE | IT87_TLDLIE)) | IT87_BR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev->cir_addr + IT87_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* write out the baud rate divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) outb(ITE_BAUDRATE_DIVISOR & 0xff, dev->cir_addr + IT87_BDLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) outb((ITE_BAUDRATE_DIVISOR >> 8) & 0xff, dev->cir_addr + IT87_BDHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* disable the baud rate divisor register again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) outb(inb(dev->cir_addr + IT87_IER) & ~IT87_BR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dev->cir_addr + IT87_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* program the RCR register defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) outb(ITE_RXDCR_DEFAULT, dev->cir_addr + IT87_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* program the TCR1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) outb(IT87_TXMPM_DEFAULT | IT87_TXENDF | IT87_TXRLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) | IT87_FIFOTL_DEFAULT | IT87_FIFOCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev->cir_addr + IT87_TCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* program the carrier parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ite_set_carrier_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* IT8512F on ITE8708 HW-specific functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* retrieve a bitmask of the current causes for a pending interrupt; this may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int it8708_get_irq_causes(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u8 iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* read the interrupt flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) iflags = inb(dev->cir_addr + IT8708_C0IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (iflags & IT85_TLDLI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret |= ITE_IRQ_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (iflags & IT85_RDAI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret |= ITE_IRQ_RX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (iflags & IT85_RFOI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ret |= ITE_IRQ_RX_FIFO_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* set the carrier parameters; to be called with the spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static void it8708_set_carrier_params(struct ite_dev *dev, bool high_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) bool use_demodulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u8 carrier_freq_bits, u8 allowance_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u8 pulse_width_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* program the C0CFR register, with HRAE=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dev->cir_addr + IT8708_BANKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) val = (inb(dev->cir_addr + IT8708_C0CFR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) & ~(IT85_HCFS | IT85_CFQ)) | carrier_freq_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (high_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) val |= IT85_HCFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) outb(val, dev->cir_addr + IT8708_C0CFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev->cir_addr + IT8708_BANKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* program the C0RCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) val = inb(dev->cir_addr + IT8708_C0RCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) & ~(IT85_RXEND | IT85_RXDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (use_demodulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) val |= IT85_RXEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) val |= allowance_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) outb(val, dev->cir_addr + IT8708_C0RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* program the C0TCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) val = inb(dev->cir_addr + IT8708_C0TCR) & ~IT85_TXMPW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) val |= pulse_width_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) outb(val, dev->cir_addr + IT8708_C0TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int it8708_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int fifo, read = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* read how many bytes are still in the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) fifo = inb(dev->cir_addr + IT8708_C0RFSR) & IT85_RXFBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) while (fifo > 0 && buf_size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) *(buf++) = inb(dev->cir_addr + IT8708_C0DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) fifo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) read++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) buf_size--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* return how many bytes are still in the FIFO; this will be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * with the device spinlock NOT HELD while waiting for the TX FIFO to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * empty; let's expect this won't be a problem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int it8708_get_tx_used_slots(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return inb(dev->cir_addr + IT8708_C0TFSR) & IT85_TXFBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* put a byte to the TX fifo; this should be called with the spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static void it8708_put_tx_byte(struct ite_dev *dev, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) outb(value, dev->cir_addr + IT8708_C0DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* idle the receiver so that we won't receive samples until another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) pulse is detected; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static void it8708_idle_rx(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* disable streaming by clearing RXACT writing it as 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev->cir_addr + IT8708_C0RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* clear the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) outb(inb(dev->cir_addr + IT8708_C0MSTCR) | IT85_FIFOCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) dev->cir_addr + IT8708_C0MSTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* disable the receiver; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static void it8708_disable_rx(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* disable the receiver interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) outb(inb(dev->cir_addr + IT8708_C0IER) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ~(IT85_RDAIE | IT85_RFOIE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev->cir_addr + IT8708_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* disable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) outb(inb(dev->cir_addr + IT8708_C0RCR) & ~IT85_RXEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev->cir_addr + IT8708_C0RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* clear the FIFO and RXACT (actually RXACT should have been cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * in the previous outb() call) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) it8708_idle_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* enable the receiver; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static void it8708_enable_rx(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* enable the receiver by setting RXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dev->cir_addr + IT8708_C0RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* just prepare it to idle for the next reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) it8708_idle_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* enable the receiver interrupts and master enable flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) outb(inb(dev->cir_addr + IT8708_C0IER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) |IT85_RDAIE | IT85_RFOIE | IT85_IEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dev->cir_addr + IT8708_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* disable the transmitter interrupt; this must be called with the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static void it8708_disable_tx_interrupt(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* disable the transmitter interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) outb(inb(dev->cir_addr + IT8708_C0IER) & ~IT85_TLDLIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dev->cir_addr + IT8708_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* enable the transmitter interrupt; this must be called with the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static void it8708_enable_tx_interrupt(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* enable the transmitter interrupts and master enable flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) outb(inb(dev->cir_addr + IT8708_C0IER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) |IT85_TLDLIE | IT85_IEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dev->cir_addr + IT8708_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* disable the device; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static void it8708_disable(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* clear out all interrupt enable flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) outb(inb(dev->cir_addr + IT8708_C0IER) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev->cir_addr + IT8708_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* disable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) it8708_disable_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* erase the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) outb(IT85_FIFOCLR | inb(dev->cir_addr + IT8708_C0MSTCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dev->cir_addr + IT8708_C0MSTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* initialize the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static void it8708_init_hardware(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* disable all the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) outb(inb(dev->cir_addr + IT8708_C0IER) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dev->cir_addr + IT8708_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* program the baud rate divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev->cir_addr + IT8708_BANKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) outb(ITE_BAUDRATE_DIVISOR & 0xff, dev->cir_addr + IT8708_C0BDLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) outb((ITE_BAUDRATE_DIVISOR >> 8) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev->cir_addr + IT8708_C0BDHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dev->cir_addr + IT8708_BANKSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* program the C0MSTCR register defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) outb((inb(dev->cir_addr + IT8708_C0MSTCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ~(IT85_ILSEL | IT85_ILE | IT85_FIFOTL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) IT85_FIFOCLR | IT85_RESET)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) IT85_FIFOTL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) dev->cir_addr + IT8708_C0MSTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* program the C0RCR register defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) outb((inb(dev->cir_addr + IT8708_C0RCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ~(IT85_RXEN | IT85_RDWOS | IT85_RXEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) IT85_RXACT | IT85_RXDCR)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ITE_RXDCR_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dev->cir_addr + IT8708_C0RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* program the C0TCR register defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) outb((inb(dev->cir_addr + IT8708_C0TCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ~(IT85_TXMPM | IT85_TXMPW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) |IT85_TXRLE | IT85_TXENDF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) IT85_TXMPM_DEFAULT | IT85_TXMPW_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev->cir_addr + IT8708_C0TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* program the carrier parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ite_set_carrier_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* IT8512F on ITE8709 HW-specific functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* read a byte from the SRAM module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static inline u8 it8709_rm(struct ite_dev *dev, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) outb(index, dev->cir_addr + IT8709_RAM_IDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return inb(dev->cir_addr + IT8709_RAM_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* write a byte to the SRAM module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static inline void it8709_wm(struct ite_dev *dev, u8 val, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) outb(index, dev->cir_addr + IT8709_RAM_IDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) outb(val, dev->cir_addr + IT8709_RAM_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static void it8709_wait(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * loop until device tells it's ready to continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * iterations count is usually ~750 but can sometimes achieve 13000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) for (i = 0; i < 15000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (it8709_rm(dev, IT8709_MODE) == IT8709_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* read the value of a CIR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static u8 it8709_rr(struct ite_dev *dev, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* just wait in case the previous access was a write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) it8709_wait(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) it8709_wm(dev, index, IT8709_REG_IDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) it8709_wm(dev, IT8709_READ, IT8709_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* wait for the read data to be available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) it8709_wait(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* return the read value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return it8709_rm(dev, IT8709_REG_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* write the value of a CIR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static void it8709_wr(struct ite_dev *dev, u8 val, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* we wait before writing, and not afterwards, since this allows us to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * pipeline the host CPU with the microcontroller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) it8709_wait(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) it8709_wm(dev, val, IT8709_REG_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) it8709_wm(dev, index, IT8709_REG_IDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) it8709_wm(dev, IT8709_WRITE, IT8709_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* retrieve a bitmask of the current causes for a pending interrupt; this may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int it8709_get_irq_causes(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) u8 iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* read the interrupt flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) iflags = it8709_rm(dev, IT8709_IIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (iflags & IT85_TLDLI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ret |= ITE_IRQ_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (iflags & IT85_RDAI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret |= ITE_IRQ_RX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (iflags & IT85_RFOI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ret |= ITE_IRQ_RX_FIFO_OVERRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* set the carrier parameters; to be called with the spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static void it8709_set_carrier_params(struct ite_dev *dev, bool high_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) bool use_demodulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) u8 carrier_freq_bits, u8 allowance_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u8 pulse_width_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) val = (it8709_rr(dev, IT85_C0CFR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) &~(IT85_HCFS | IT85_CFQ)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) carrier_freq_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (high_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) val |= IT85_HCFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) it8709_wr(dev, val, IT85_C0CFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* program the C0RCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) val = it8709_rr(dev, IT85_C0RCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) & ~(IT85_RXEND | IT85_RXDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (use_demodulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) val |= IT85_RXEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) val |= allowance_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) it8709_wr(dev, val, IT85_C0RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* program the C0TCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) val = it8709_rr(dev, IT85_C0TCR) & ~IT85_TXMPW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) val |= pulse_width_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) it8709_wr(dev, val, IT85_C0TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static int it8709_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int fifo, read = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* read how many bytes are still in the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) fifo = it8709_rm(dev, IT8709_RFSR) & IT85_RXFBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) while (fifo > 0 && buf_size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) *(buf++) = it8709_rm(dev, IT8709_FIFO + read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) fifo--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) read++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) buf_size--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* 'clear' the FIFO by setting the writing index to 0; this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * completely bound to be racy, but we can't help it, since it's a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * limitation of the protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) it8709_wm(dev, 0, IT8709_RFSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* return how many bytes are still in the FIFO; this will be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * with the device spinlock NOT HELD while waiting for the TX FIFO to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * empty; let's expect this won't be a problem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static int it8709_get_tx_used_slots(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return it8709_rr(dev, IT85_C0TFSR) & IT85_TXFBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* put a byte to the TX fifo; this should be called with the spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static void it8709_put_tx_byte(struct ite_dev *dev, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) it8709_wr(dev, value, IT85_C0DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* idle the receiver so that we won't receive samples until another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) pulse is detected; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static void it8709_idle_rx(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* disable streaming by clearing RXACT writing it as 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) | IT85_RXACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) IT85_C0RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /* clear the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) it8709_wr(dev, it8709_rr(dev, IT85_C0MSTCR) | IT85_FIFOCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) IT85_C0MSTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /* disable the receiver; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static void it8709_disable_rx(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* disable the receiver interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ~(IT85_RDAIE | IT85_RFOIE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) IT85_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* disable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) & ~IT85_RXEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) IT85_C0RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* clear the FIFO and RXACT (actually RXACT should have been cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * in the previous it8709_wr(dev, ) call) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) it8709_idle_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* enable the receiver; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static void it8709_enable_rx(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* enable the receiver by setting RXEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) | IT85_RXEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) IT85_C0RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* just prepare it to idle for the next reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) it8709_idle_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* enable the receiver interrupts and master enable flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) it8709_wr(dev, it8709_rr(dev, IT85_C0IER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) |IT85_RDAIE | IT85_RFOIE | IT85_IEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) IT85_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /* disable the transmitter interrupt; this must be called with the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static void it8709_disable_tx_interrupt(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* disable the transmitter interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) it8709_wr(dev, it8709_rr(dev, IT85_C0IER) & ~IT85_TLDLIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) IT85_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* enable the transmitter interrupt; this must be called with the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static void it8709_enable_tx_interrupt(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* enable the transmitter interrupts and master enable flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) it8709_wr(dev, it8709_rr(dev, IT85_C0IER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) |IT85_TLDLIE | IT85_IEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) IT85_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /* disable the device; this must be called with the device spinlock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static void it8709_disable(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* clear out all interrupt enable flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) IT85_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* disable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) it8709_disable_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* erase the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) it8709_wr(dev, IT85_FIFOCLR | it8709_rr(dev, IT85_C0MSTCR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) IT85_C0MSTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* initialize the hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static void it8709_init_hardware(struct ite_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* disable all the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) IT85_C0IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* program the baud rate divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) it8709_wr(dev, ITE_BAUDRATE_DIVISOR & 0xff, IT85_C0BDLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) it8709_wr(dev, (ITE_BAUDRATE_DIVISOR >> 8) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) IT85_C0BDHR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* program the C0MSTCR register defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) it8709_wr(dev, (it8709_rr(dev, IT85_C0MSTCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ~(IT85_ILSEL | IT85_ILE | IT85_FIFOTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) | IT85_FIFOCLR | IT85_RESET)) | IT85_FIFOTL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) IT85_C0MSTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /* program the C0RCR register defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) it8709_wr(dev, (it8709_rr(dev, IT85_C0RCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ~(IT85_RXEN | IT85_RDWOS | IT85_RXEND | IT85_RXACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) | IT85_RXDCR)) | ITE_RXDCR_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) IT85_C0RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* program the C0TCR register defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) it8709_wr(dev, (it8709_rr(dev, IT85_C0TCR) & ~(IT85_TXMPM | IT85_TXMPW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) | IT85_TXRLE | IT85_TXENDF | IT85_TXMPM_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) | IT85_TXMPW_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) IT85_C0TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /* program the carrier parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ite_set_carrier_params(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* generic hardware setup/teardown code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* activate the device for use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static int ite_open(struct rc_dev *rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct ite_dev *dev = rcdev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev->in_use = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* enable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev->params.enable_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* deactivate the device for use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static void ite_close(struct rc_dev *rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct ite_dev *dev = rcdev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev->in_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* wait for any transmission to end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) wait_event_interruptible(dev->tx_ended, !dev->transmitting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) dev->params.disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* supported models and their parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static const struct ite_dev_params ite_dev_descs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) { /* 0: ITE8704 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .model = "ITE8704 CIR transceiver",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .io_region_size = IT87_IOREG_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .io_rsrc_no = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .hw_tx_capable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .sample_period = (u32) (1000000000ULL / 115200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .tx_carrier_freq = 38000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .tx_duty_cycle = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .rx_low_carrier_freq = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .rx_high_carrier_freq = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) /* operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .get_irq_causes = it87_get_irq_causes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .enable_rx = it87_enable_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .idle_rx = it87_idle_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .disable_rx = it87_idle_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .get_rx_bytes = it87_get_rx_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .enable_tx_interrupt = it87_enable_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .disable_tx_interrupt = it87_disable_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .get_tx_used_slots = it87_get_tx_used_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .put_tx_byte = it87_put_tx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .disable = it87_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .init_hardware = it87_init_hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .set_carrier_params = it87_set_carrier_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) { /* 1: ITE8713 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .model = "ITE8713 CIR transceiver",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .io_region_size = IT87_IOREG_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .io_rsrc_no = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .hw_tx_capable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .sample_period = (u32) (1000000000ULL / 115200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .tx_carrier_freq = 38000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .tx_duty_cycle = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .rx_low_carrier_freq = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .rx_high_carrier_freq = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .get_irq_causes = it87_get_irq_causes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .enable_rx = it87_enable_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .idle_rx = it87_idle_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .disable_rx = it87_idle_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .get_rx_bytes = it87_get_rx_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .enable_tx_interrupt = it87_enable_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .disable_tx_interrupt = it87_disable_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .get_tx_used_slots = it87_get_tx_used_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .put_tx_byte = it87_put_tx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .disable = it87_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .init_hardware = it87_init_hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .set_carrier_params = it87_set_carrier_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) { /* 2: ITE8708 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .model = "ITE8708 CIR transceiver",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .io_region_size = IT8708_IOREG_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .io_rsrc_no = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .hw_tx_capable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .sample_period = (u32) (1000000000ULL / 115200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .tx_carrier_freq = 38000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .tx_duty_cycle = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .rx_low_carrier_freq = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .rx_high_carrier_freq = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /* operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .get_irq_causes = it8708_get_irq_causes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .enable_rx = it8708_enable_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .idle_rx = it8708_idle_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .disable_rx = it8708_idle_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .get_rx_bytes = it8708_get_rx_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .enable_tx_interrupt = it8708_enable_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .disable_tx_interrupt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) it8708_disable_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .get_tx_used_slots = it8708_get_tx_used_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .put_tx_byte = it8708_put_tx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .disable = it8708_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .init_hardware = it8708_init_hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .set_carrier_params = it8708_set_carrier_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) { /* 3: ITE8709 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .model = "ITE8709 CIR transceiver",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .io_region_size = IT8709_IOREG_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .io_rsrc_no = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .hw_tx_capable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .sample_period = (u32) (1000000000ULL / 115200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .tx_carrier_freq = 38000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .tx_duty_cycle = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .rx_low_carrier_freq = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .rx_high_carrier_freq = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /* operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .get_irq_causes = it8709_get_irq_causes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .enable_rx = it8709_enable_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .idle_rx = it8709_idle_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .disable_rx = it8709_idle_rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .get_rx_bytes = it8709_get_rx_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .enable_tx_interrupt = it8709_enable_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .disable_tx_interrupt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) it8709_disable_tx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .get_tx_used_slots = it8709_get_tx_used_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .put_tx_byte = it8709_put_tx_byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .disable = it8709_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .init_hardware = it8709_init_hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .set_carrier_params = it8709_set_carrier_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static const struct pnp_device_id ite_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {"ITE8704", 0}, /* Default model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {"ITE8713", 1}, /* CIR found in EEEBox 1501U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {"ITE8708", 2}, /* Bridged IT8512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) {"ITE8709", 3}, /* SRAM-Bridged IT8512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {"", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /* allocate memory, probe hardware, and initialize everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static int ite_probe(struct pnp_dev *pdev, const struct pnp_device_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) const struct ite_dev_params *dev_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) struct ite_dev *itdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) struct rc_dev *rdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) int model_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) int io_rsrc_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) itdev = kzalloc(sizeof(struct ite_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (!itdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* input device for IR remote (and tx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (!rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) goto exit_free_dev_rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) itdev->rdev = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* get the model number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) model_no = (int)dev_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ite_pr(KERN_NOTICE, "Auto-detected model: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ite_dev_descs[model_no].model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (model_number >= 0 && model_number < ARRAY_SIZE(ite_dev_descs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) model_no = model_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ite_pr(KERN_NOTICE, "The model has been fixed by a module parameter.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ite_pr(KERN_NOTICE, "Using model: %s\n", ite_dev_descs[model_no].model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* get the description for the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dev_desc = &ite_dev_descs[model_no];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) io_rsrc_no = dev_desc->io_rsrc_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* validate pnp resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (!pnp_port_valid(pdev, io_rsrc_no) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) pnp_port_len(pdev, io_rsrc_no) != dev_desc->io_region_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) dev_err(&pdev->dev, "IR PNP Port not valid!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) goto exit_free_dev_rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (!pnp_irq_valid(pdev, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) dev_err(&pdev->dev, "PNP IRQ not valid!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) goto exit_free_dev_rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* store resource values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) itdev->cir_addr = pnp_port_start(pdev, io_rsrc_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) itdev->cir_irq = pnp_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* initialize spinlocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) spin_lock_init(&itdev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /* set driver data into the pnp device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) pnp_set_drvdata(pdev, itdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) itdev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* initialize waitqueues for transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) init_waitqueue_head(&itdev->tx_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) init_waitqueue_head(&itdev->tx_ended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* copy model-specific parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) itdev->params = *dev_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* apply any overrides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (sample_period > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) itdev->params.sample_period = sample_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (tx_carrier_freq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) itdev->params.tx_carrier_freq = tx_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (tx_duty_cycle > 0 && tx_duty_cycle <= 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) itdev->params.tx_duty_cycle = tx_duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (rx_low_carrier_freq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) itdev->params.rx_low_carrier_freq = rx_low_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (rx_high_carrier_freq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) itdev->params.rx_high_carrier_freq = rx_high_carrier_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* print out parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ite_pr(KERN_NOTICE, "TX-capable: %d\n", (int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) itdev->params.hw_tx_capable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ite_pr(KERN_NOTICE, "Sample period (ns): %ld\n", (long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) itdev->params.sample_period);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ite_pr(KERN_NOTICE, "TX carrier frequency (Hz): %d\n", (int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) itdev->params.tx_carrier_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ite_pr(KERN_NOTICE, "TX duty cycle (%%): %d\n", (int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) itdev->params.tx_duty_cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ite_pr(KERN_NOTICE, "RX low carrier frequency (Hz): %d\n", (int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) itdev->params.rx_low_carrier_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ite_pr(KERN_NOTICE, "RX high carrier frequency (Hz): %d\n", (int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) itdev->params.rx_high_carrier_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* set up hardware initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) itdev->params.init_hardware(itdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* set up ir-core props */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) rdev->priv = itdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) rdev->open = ite_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) rdev->close = ite_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) rdev->s_idle = ite_s_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) rdev->s_rx_carrier_range = ite_set_rx_carrier_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* FIFO threshold is 17 bytes, so 17 * 8 samples minimum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) rdev->min_timeout = 17 * 8 * ITE_BAUDRATE_DIVISOR *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) itdev->params.sample_period / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) rdev->timeout = IR_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) rdev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) rdev->rx_resolution = ITE_BAUDRATE_DIVISOR *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) itdev->params.sample_period / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) rdev->tx_resolution = ITE_BAUDRATE_DIVISOR *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) itdev->params.sample_period / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* set up transmitter related values if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (itdev->params.hw_tx_capable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) rdev->tx_ir = ite_tx_ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) rdev->s_tx_carrier = ite_set_tx_carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) rdev->s_tx_duty_cycle = ite_set_tx_duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) rdev->device_name = dev_desc->model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) rdev->input_id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) rdev->input_id.vendor = PCI_VENDOR_ID_ITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) rdev->input_id.product = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) rdev->input_id.version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) rdev->driver_name = ITE_DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) rdev->map_name = RC_MAP_RC6_MCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) ret = rc_register_device(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) goto exit_free_dev_rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* now claim resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (!request_region(itdev->cir_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) dev_desc->io_region_size, ITE_DRIVER_NAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) goto exit_unregister_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (request_irq(itdev->cir_irq, ite_cir_isr, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) ITE_DRIVER_NAME, (void *)itdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) goto exit_release_cir_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ite_pr(KERN_NOTICE, "driver has been successfully loaded\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) exit_release_cir_addr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) release_region(itdev->cir_addr, itdev->params.io_region_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) exit_unregister_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) rc_unregister_device(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) rdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) exit_free_dev_rdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) rc_free_device(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) kfree(itdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static void ite_remove(struct pnp_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) struct ite_dev *dev = pnp_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* disable hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) dev->params.disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) /* free resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) free_irq(dev->cir_irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) release_region(dev->cir_addr, dev->params.io_region_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) rc_unregister_device(dev->rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static int ite_suspend(struct pnp_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct ite_dev *dev = pnp_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /* wait for any transmission to end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) wait_event_interruptible(dev->tx_ended, !dev->transmitting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) dev->params.disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static int ite_resume(struct pnp_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) struct ite_dev *dev = pnp_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* reinitialize hardware config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) dev->params.init_hardware(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* enable the receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) dev->params.enable_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static void ite_shutdown(struct pnp_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) struct ite_dev *dev = pnp_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ite_dbg("%s called", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) dev->params.disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static struct pnp_driver ite_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .name = ITE_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .id_table = ite_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .probe = ite_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .remove = ite_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .suspend = ite_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .resume = ite_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .shutdown = ite_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) MODULE_DEVICE_TABLE(pnp, ite_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) MODULE_DESCRIPTION("ITE Tech Inc. IT8712F/ITE8512F CIR driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) MODULE_AUTHOR("Juan J. Garcia de Soria <skandalfo@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) module_pnp_driver(ite_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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