Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* ir-rc6-decoder.c - A decoder for the RC6 IR protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2010 by David Härdeman <david@hardeman.nu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include "rc-core-priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This decoder currently supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * RC6-0-16	(standard toggle bit in header)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * RC6-6A-20	(no toggle bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * RC6-6A-24	(no toggle bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * RC6-6A-32	(MCE version with toggle bit in body)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define RC6_UNIT		444	/* microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define RC6_HEADER_NBITS	4	/* not including toggle bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define RC6_0_NBITS		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define RC6_6A_32_NBITS		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define RC6_6A_NBITS		128	/* Variable 8..128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RC6_PREFIX_PULSE	(6 * RC6_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RC6_PREFIX_SPACE	(2 * RC6_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define RC6_BIT_START		(1 * RC6_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RC6_BIT_END		(1 * RC6_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RC6_TOGGLE_START	(2 * RC6_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RC6_TOGGLE_END		(2 * RC6_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RC6_SUFFIX_SPACE	(6 * RC6_UNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RC6_MODE_MASK		0x07	/* for the header bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RC6_STARTBIT_MASK	0x08	/* for the header bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RC6_6A_MCE_TOGGLE_MASK	0x8000	/* for the body bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RC6_6A_LCC_MASK		0xffff0000 /* RC6-6A-32 long customer code mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RC6_6A_MCE_CC		0x800f0000 /* MCE customer code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define RC6_6A_ZOTAC_CC		0x80340000 /* Zotac customer code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RC6_6A_KATHREIN_CC	0x80460000 /* Kathrein RCU-676 customer code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #ifndef CHAR_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CHAR_BIT 8	/* Normally in <limits.h> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) enum rc6_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	RC6_MODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	RC6_MODE_6A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	RC6_MODE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) enum rc6_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	STATE_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	STATE_PREFIX_SPACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	STATE_HEADER_BIT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	STATE_HEADER_BIT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	STATE_TOGGLE_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	STATE_TOGGLE_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	STATE_BODY_BIT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	STATE_BODY_BIT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	STATE_FINISHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static enum rc6_mode rc6_mode(struct rc6_dec *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	switch (data->header & RC6_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return RC6_MODE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		if (!data->toggle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			return RC6_MODE_6A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return RC6_MODE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * ir_rc6_decode() - Decode one RC6 pulse or space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * @dev:	the struct rc_dev descriptor of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * @ev:		the struct ir_raw_event descriptor of the pulse/space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * This function returns -EINVAL if the pulse violates the state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int ir_rc6_decode(struct rc_dev *dev, struct ir_raw_event ev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct rc6_dec *data = &dev->raw->rc6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 scancode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u8 toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	enum rc_proto protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (!is_timing_event(ev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		if (ev.reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			data->state = STATE_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (!geq_margin(ev.duration, RC6_UNIT, RC6_UNIT / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	dev_dbg(&dev->dev, "RC6 decode started at state %i (%uus %s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		data->state, ev.duration, TO_STR(ev.pulse));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (!geq_margin(ev.duration, RC6_UNIT, RC6_UNIT / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	switch (data->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case STATE_INACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		if (!ev.pulse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		/* Note: larger margin on first pulse since each RC6_UNIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		   is quite short and some hardware takes some time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		   adjust to the signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		if (!eq_margin(ev.duration, RC6_PREFIX_PULSE, RC6_UNIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		data->state = STATE_PREFIX_SPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		data->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case STATE_PREFIX_SPACE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		if (ev.pulse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		if (!eq_margin(ev.duration, RC6_PREFIX_SPACE, RC6_UNIT / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		data->state = STATE_HEADER_BIT_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		data->header = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case STATE_HEADER_BIT_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if (!eq_margin(ev.duration, RC6_BIT_START, RC6_UNIT / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		data->header <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (ev.pulse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			data->header |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		data->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		data->state = STATE_HEADER_BIT_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	case STATE_HEADER_BIT_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (data->count == RC6_HEADER_NBITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			data->state = STATE_TOGGLE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			data->state = STATE_HEADER_BIT_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		decrease_duration(&ev, RC6_BIT_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	case STATE_TOGGLE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		if (!eq_margin(ev.duration, RC6_TOGGLE_START, RC6_UNIT / 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		data->toggle = ev.pulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		data->state = STATE_TOGGLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	case STATE_TOGGLE_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		if (!(data->header & RC6_STARTBIT_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			dev_dbg(&dev->dev, "RC6 invalid start bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		data->state = STATE_BODY_BIT_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		decrease_duration(&ev, RC6_TOGGLE_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		data->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		data->body = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		switch (rc6_mode(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		case RC6_MODE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			data->wanted_bits = RC6_0_NBITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		case RC6_MODE_6A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			data->wanted_bits = RC6_6A_NBITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			dev_dbg(&dev->dev, "RC6 unknown mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	case STATE_BODY_BIT_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		if (eq_margin(ev.duration, RC6_BIT_START, RC6_UNIT / 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			/* Discard LSB's that won't fit in data->body */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			if (data->count++ < CHAR_BIT * sizeof data->body) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				data->body <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				if (ev.pulse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 					data->body |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			data->state = STATE_BODY_BIT_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		} else if (RC6_MODE_6A == rc6_mode(data) && !ev.pulse &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				geq_margin(ev.duration, RC6_SUFFIX_SPACE, RC6_UNIT / 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			data->state = STATE_FINISHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	case STATE_BODY_BIT_END:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		if (data->count == data->wanted_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			data->state = STATE_FINISHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			data->state = STATE_BODY_BIT_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		decrease_duration(&ev, RC6_BIT_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	case STATE_FINISHED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		if (ev.pulse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		switch (rc6_mode(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		case RC6_MODE_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			scancode = data->body;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			toggle = data->toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			protocol = RC_PROTO_RC6_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			dev_dbg(&dev->dev, "RC6(0) scancode 0x%04x (toggle: %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				scancode, toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		case RC6_MODE_6A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			if (data->count > CHAR_BIT * sizeof data->body) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				dev_dbg(&dev->dev, "RC6 too many (%u) data bits\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 					data->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			scancode = data->body;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			switch (data->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			case 20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				protocol = RC_PROTO_RC6_6A_20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 				toggle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			case 24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 				protocol = RC_PROTO_RC6_6A_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				toggle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				switch (scancode & RC6_6A_LCC_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				case RC6_6A_MCE_CC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 				case RC6_6A_KATHREIN_CC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				case RC6_6A_ZOTAC_CC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 					protocol = RC_PROTO_RC6_MCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 					toggle = !!(scancode & RC6_6A_MCE_TOGGLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 					scancode &= ~RC6_6A_MCE_TOGGLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 					break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 					protocol = RC_PROTO_RC6_6A_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 					toggle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 					break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				dev_dbg(&dev->dev, "RC6(6A) unsupported length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			dev_dbg(&dev->dev, "RC6(6A) proto 0x%04x, scancode 0x%08x (toggle: %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				protocol, scancode, toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			dev_dbg(&dev->dev, "RC6 unknown mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		rc_keydown(dev, protocol, scancode, toggle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		data->state = STATE_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	dev_dbg(&dev->dev, "RC6 decode failed at state %i (%uus %s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		data->state, ev.duration, TO_STR(ev.pulse));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	data->state = STATE_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct ir_raw_timings_manchester ir_rc6_timings[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.leader_pulse		= RC6_PREFIX_PULSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.leader_space		= RC6_PREFIX_SPACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.clock			= RC6_UNIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.invert			= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.clock			= RC6_UNIT * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.invert			= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.clock			= RC6_UNIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.invert			= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.trailer_space		= RC6_SUFFIX_SPACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  * ir_rc6_encode() - Encode a scancode as a stream of raw events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  * @protocol:	protocol to encode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  * @scancode:	scancode to encode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  * @events:	array of raw ir events to write into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  * @max:	maximum size of @events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  * Returns:	The number of events written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  *		-ENOBUFS if there isn't enough space in the array to fit the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  *		encoding. In this case all @max events will have been written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)  *		-EINVAL if the scancode is ambiguous or invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int ir_rc6_encode(enum rc_proto protocol, u32 scancode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			 struct ir_raw_event *events, unsigned int max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct ir_raw_event *e = events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (protocol == RC_PROTO_RC6_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		/* Modulate the header (Start Bit & Mode-0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		ret = ir_raw_gen_manchester(&e, max - (e - events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 					    &ir_rc6_timings[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 					    RC6_HEADER_NBITS, (1 << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		/* Modulate Trailer Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		ret = ir_raw_gen_manchester(&e, max - (e - events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 					    &ir_rc6_timings[1], 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		/* Modulate rest of the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		ret = ir_raw_gen_manchester(&e, max - (e - events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 					    &ir_rc6_timings[2], RC6_0_NBITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 					    scancode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		switch (protocol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		case RC_PROTO_RC6_MCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		case RC_PROTO_RC6_6A_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			bits = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		case RC_PROTO_RC6_6A_24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			bits = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		case RC_PROTO_RC6_6A_20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			bits = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		/* Modulate the header (Start Bit & Header-version 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		ret = ir_raw_gen_manchester(&e, max - (e - events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 					    &ir_rc6_timings[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 					    RC6_HEADER_NBITS, (1 << 3 | 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		/* Modulate Trailer Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		ret = ir_raw_gen_manchester(&e, max - (e - events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 					    &ir_rc6_timings[1], 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		/* Modulate rest of the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		ret = ir_raw_gen_manchester(&e, max - (e - events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 					    &ir_rc6_timings[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 					    bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 					    scancode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return e - events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct ir_raw_handler rc6_handler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	.protocols	= RC_PROTO_BIT_RC6_0 | RC_PROTO_BIT_RC6_6A_20 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			  RC_PROTO_BIT_RC6_6A_24 | RC_PROTO_BIT_RC6_6A_32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			  RC_PROTO_BIT_RC6_MCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	.decode		= ir_rc6_decode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	.encode		= ir_rc6_encode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	.carrier	= 36000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.min_timeout	= RC6_SUFFIX_SPACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int __init ir_rc6_decode_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	ir_raw_handler_register(&rc6_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	printk(KERN_INFO "IR RC6 protocol handler initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void __exit ir_rc6_decode_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	ir_raw_handler_unregister(&rc6_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) module_init(ir_rc6_decode_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) module_exit(ir_rc6_decode_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MODULE_DESCRIPTION("RC6 IR protocol decoder");