Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2014 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define IR_ENABLE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define IR_CONFIG		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CNT_LEADS		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CNT_LEADE		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CNT_SLEADE		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CNT0_B			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CNT1_B			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IR_BUSY			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IR_DATAH		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IR_DATAL		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IR_INTM			0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IR_INTS			0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IR_INTC			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IR_START		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define INTMS_SYMBRCV		(BIT(24) | BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define INTMS_TIMEOUT		(BIT(25) | BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define INTMS_OVERFLOW		(BIT(26) | BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define INT_CLR_OVERFLOW	BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define INT_CLR_TIMEOUT		BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define INT_CLR_RCV		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define INT_CLR_RCVTIMEOUT	(BIT(16) | BIT(17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IR_CLK_ENABLE		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IR_CLK_RESET		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* IR_ENABLE register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IR_ENABLE_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IR_ENABLE_EN_EXTRA	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IR_CFG_WIDTH_MASK	0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IR_CFG_WIDTH_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IR_CFG_FORMAT_MASK	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IR_CFG_FORMAT_SHIFT	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IR_CFG_INT_LEVEL_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IR_CFG_INT_LEVEL_SHIFT	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* only support raw mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IR_CFG_MODE_RAW		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IR_CFG_FREQ_MASK	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IR_CFG_FREQ_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define IR_CFG_INT_THRESHOLD	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* symbol start from low to high, symbol stream end at high*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IR_CFG_SYMBOL_FMT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IR_CFG_SYMBOL_MAXWIDTH	0x3e80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IR_HIX5HD2_NAME		"hix5hd2-ir"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* Need to set extra bit for enabling IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define HIX5HD2_FLAG_EXTRA_ENABLE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct hix5hd2_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static const struct hix5hd2_soc_data hix5hd2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.clk_reg = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static const struct hix5hd2_soc_data hi3796cv300_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.clk_reg = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.flags = HIX5HD2_FLAG_EXTRA_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) struct hix5hd2_ir_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int			irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct rc_dev		*rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct regmap		*regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct clk		*clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned long		rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	const struct hix5hd2_soc_data *socdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int hix5hd2_ir_clk_enable(struct hix5hd2_ir_priv *dev, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u32 clk_reg = dev->socdata->clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (dev->regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		regmap_read(dev->regmap, clk_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			val &= ~IR_CLK_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			val |= IR_CLK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			val &= ~IR_CLK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			val |= IR_CLK_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		regmap_write(dev->regmap, clk_reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			ret = clk_prepare_enable(dev->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			clk_disable_unprepare(dev->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline void hix5hd2_ir_enable(struct hix5hd2_ir_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u32 val = IR_ENABLE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (priv->socdata->flags & HIX5HD2_FLAG_EXTRA_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		val |= IR_ENABLE_EN_EXTRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	writel_relaxed(val, priv->base + IR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32 val, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	hix5hd2_ir_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	while (readl_relaxed(priv->base + IR_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			dev_err(priv->dev, "IR_BUSY timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* Now only support raw mode, with symbol start from low to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	rate = DIV_ROUND_CLOSEST(priv->rate, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	val = IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK << IR_CFG_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	val |= IR_CFG_SYMBOL_FMT & IR_CFG_FORMAT_MASK << IR_CFG_FORMAT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	val |= (IR_CFG_INT_THRESHOLD - 1) & IR_CFG_INT_LEVEL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	       << IR_CFG_INT_LEVEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	val |= IR_CFG_MODE_RAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	val |= (rate - 1) & IR_CFG_FREQ_MASK << IR_CFG_FREQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	writel_relaxed(val, priv->base + IR_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	writel_relaxed(0x00, priv->base + IR_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* write arbitrary value to start  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	writel_relaxed(0x01, priv->base + IR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int hix5hd2_ir_open(struct rc_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct hix5hd2_ir_priv *priv = rdev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	ret = hix5hd2_ir_clk_enable(priv, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ret = hix5hd2_ir_config(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		hix5hd2_ir_clk_enable(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void hix5hd2_ir_close(struct rc_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct hix5hd2_ir_priv *priv = rdev->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	hix5hd2_ir_clk_enable(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u32 symb_num, symb_val, symb_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u32 data_l, data_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u32 irq_sr, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct hix5hd2_ir_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	irq_sr = readl_relaxed(priv->base + IR_INTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (irq_sr & INTMS_OVERFLOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		 * we must read IR_DATAL first, then we can clean up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		 * IR_INTS availably since logic would not clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		 * fifo when overflow, drv do the job
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		ir_raw_event_reset(priv->rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		symb_num = readl_relaxed(priv->base + IR_DATAH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		for (i = 0; i < symb_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			readl_relaxed(priv->base + IR_DATAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		dev_info(priv->dev, "overflow, level=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			 IR_CFG_INT_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if ((irq_sr & INTMS_SYMBRCV) || (irq_sr & INTMS_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		struct ir_raw_event ev = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		symb_num = readl_relaxed(priv->base + IR_DATAH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		for (i = 0; i < symb_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			symb_val = readl_relaxed(priv->base + IR_DATAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			data_l = ((symb_val & 0xffff) * 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			data_h =  ((symb_val >> 16) & 0xffff) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			symb_time = (data_l + data_h) / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			ev.duration = data_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			ev.pulse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			ir_raw_event_store(priv->rdev, &ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			if (symb_time < IR_CFG_SYMBOL_MAXWIDTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				ev.duration = data_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				ev.pulse = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				ir_raw_event_store(priv->rdev, &ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				ir_raw_event_set_idle(priv->rdev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		if (irq_sr & INTMS_SYMBRCV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		if (irq_sr & INTMS_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* Empty software fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ir_raw_event_handle(priv->rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct of_device_id hix5hd2_ir_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	{ .compatible = "hisilicon,hix5hd2-ir", &hix5hd2_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	{ .compatible = "hisilicon,hi3796cv300-ir", &hi3796cv300_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MODULE_DEVICE_TABLE(of, hix5hd2_ir_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int hix5hd2_ir_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct rc_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct hix5hd2_ir_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	const char *map_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	of_id = of_match_device(hix5hd2_ir_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (!of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		dev_err(dev, "Unable to initialize IR data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	priv->socdata = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	priv->regmap = syscon_regmap_lookup_by_phandle(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 						       "hisilicon,power-syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (IS_ERR(priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		dev_info(dev, "no power-reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		priv->regmap = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	priv->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	priv->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (priv->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return priv->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (!rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	priv->clock = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (IS_ERR(priv->clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		dev_err(dev, "clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		ret = PTR_ERR(priv->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	ret = clk_prepare_enable(priv->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	priv->rate = clk_get_rate(priv->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	rdev->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	rdev->open = hix5hd2_ir_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	rdev->close = hix5hd2_ir_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	rdev->driver_name = IR_HIX5HD2_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	map_name = of_get_property(node, "linux,rc-map-name", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	rdev->map_name = map_name ?: RC_MAP_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	rdev->device_name = IR_HIX5HD2_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	rdev->input_phys = IR_HIX5HD2_NAME "/input0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	rdev->input_id.bustype = BUS_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	rdev->input_id.vendor = 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	rdev->input_id.product = 0x0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	rdev->input_id.version = 0x0100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	rdev->rx_resolution = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	rdev->timeout = IR_CFG_SYMBOL_MAXWIDTH * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	ret = rc_register_device(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		goto clkerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (devm_request_irq(dev, priv->irq, hix5hd2_ir_rx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			     0, pdev->name, priv) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		dev_err(dev, "IRQ %d register failed\n", priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		goto regerr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	priv->rdev = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) regerr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	rc_unregister_device(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	rdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) clkerr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	clk_disable_unprepare(priv->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	rc_free_device(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	dev_err(dev, "Unable to register device (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int hix5hd2_ir_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct hix5hd2_ir_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	clk_disable_unprepare(priv->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	rc_unregister_device(priv->rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int hix5hd2_ir_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	clk_disable_unprepare(priv->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	hix5hd2_ir_clk_enable(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int hix5hd2_ir_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	ret = hix5hd2_ir_clk_enable(priv, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	ret = clk_prepare_enable(priv->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		hix5hd2_ir_clk_enable(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	hix5hd2_ir_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	writel_relaxed(0x00, priv->base + IR_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	writel_relaxed(0xff, priv->base + IR_INTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	writel_relaxed(0x01, priv->base + IR_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 			 hix5hd2_ir_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct platform_driver hix5hd2_ir_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		.name = IR_HIX5HD2_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		.of_match_table = hix5hd2_ir_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		.pm     = &hix5hd2_ir_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.probe = hix5hd2_ir_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	.remove = hix5hd2_ir_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) module_platform_driver(hix5hd2_ir_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_DESCRIPTION("IR controller driver for hix5hd2 platforms");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MODULE_AUTHOR("Guoxiong Yan <yanguoxiong@huawei.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MODULE_ALIAS("platform:hix5hd2-ir");