^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ImgTec IR Hardware Decoder found in PowerDown Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2010-2014 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _IMG_IR_HW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _IMG_IR_HW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMG_IR_CODETYPE_PULSELEN 0x0 /* Sony */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMG_IR_CODETYPE_PULSEDIST 0x1 /* NEC, Toshiba, Micom, Sharp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMG_IR_CODETYPE_BIPHASE 0x2 /* RC-5/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMG_IR_CODETYPE_2BITPULSEPOS 0x3 /* RC-MM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Timing information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * struct img_ir_control - Decoder control settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @decoden: Primary decoder enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @code_type: Decode type (see IMG_IR_CODETYPE_*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @hdrtog: Detect header toggle symbol after leader symbol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @ldrdec: Don't discard leader if maximum width reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @decodinpol: Decoder input polarity (1=active high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @bitorien: Bit orientation (1=MSB first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @d1validsel: Decoder 2 takes over if it detects valid data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @bitinv: Bit inversion switch (1=don't invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @decodend2: Secondary decoder enable (no leader symbol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @bitoriend2: Bit orientation (1=MSB first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @bitinvd2: Secondary decoder bit inversion switch (1=don't invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct img_ir_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned decoden:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned code_type:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned hdrtog:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned ldrdec:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned decodinpol:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned bitorien:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned d1validsel:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned bitinv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned decodend2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned bitoriend2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned bitinvd2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * struct img_ir_timing_range - range of timing values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @min: Minimum timing value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @max: Maximum timing value (if < @min, this will be set to @min during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * preprocessing step, so it is normally not explicitly initialised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * and is taken care of by the tolerance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct img_ir_timing_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u16 min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u16 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * struct img_ir_symbol_timing - timing data for a symbol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @pulse: Timing range for the length of the pulse in this symbol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @space: Timing range for the length of the space in this symbol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct img_ir_symbol_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct img_ir_timing_range pulse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct img_ir_timing_range space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * struct img_ir_free_timing - timing data for free time symbol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @minlen: Minimum number of bits of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @maxlen: Maximum number of bits of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @ft_min: Minimum free time after message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct img_ir_free_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* measured in bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 minlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u16 ft_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * struct img_ir_timings - Timing values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @ldr: Leader symbol timing data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @s00: Zero symbol timing data for primary decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @s01: One symbol timing data for primary decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @s10: Zero symbol timing data for secondary (no leader symbol) decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @s11: One symbol timing data for secondary (no leader symbol) decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @ft: Free time symbol timing data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct img_ir_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct img_ir_symbol_timing ldr, s00, s01, s10, s11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct img_ir_free_timing ft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * struct img_ir_filter - Filter IR events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @data: Data to match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @mask: Mask of bits to compare.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @minlen: Additional minimum number of bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @maxlen: Additional maximum number of bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct img_ir_filter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u64 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u64 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 minlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * struct img_ir_timing_regvals - Calculated timing register values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @ldr: Leader symbol timing register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @s00: Zero symbol timing register value for primary decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @s01: One symbol timing register value for primary decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @s10: Zero symbol timing register value for secondary decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @s11: One symbol timing register value for secondary decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @ft: Free time symbol timing register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct img_ir_timing_regvals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 ldr, s00, s01, s10, s11, ft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMG_IR_SCANCODE 0 /* new scancode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMG_IR_REPEATCODE 1 /* repeat the previous code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * struct img_ir_scancode_req - Scancode request data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @protocol: Protocol code of received message (defaults to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * RC_PROTO_UNKNOWN).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @scancode: Scan code of received message (must be written by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * handler if IMG_IR_SCANCODE is returned).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @toggle: Toggle bit (defaults to 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct img_ir_scancode_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum rc_proto protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 scancode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 toggle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * struct img_ir_decoder - Decoder settings for an IR protocol.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @type: Protocol types bitmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @tolerance: Timing tolerance as a percentage (default 10%).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @unit: Unit of timings in nanoseconds (default 1 us).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @timings: Primary timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @rtimings: Additional override timings while waiting for repeats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @repeat: Maximum repeat interval (always in milliseconds).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @control: Control flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @scancode: Pointer to function to convert the IR data into a scancode (it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * must be safe to execute in interrupt context).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Returns IMG_IR_SCANCODE to emit new scancode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Returns IMG_IR_REPEATCODE to repeat previous code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Returns -errno (e.g. -EINVAL) on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @filter: Pointer to function to convert scancode filter to raw hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * filter. The minlen and maxlen fields will have been initialised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * to the maximum range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct img_ir_decoder {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* core description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u64 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int tolerance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct img_ir_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct img_ir_timings rtimings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int repeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct img_ir_control control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* scancode logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int (*scancode)(int len, u64 raw, u64 enabled_protocols,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct img_ir_scancode_req *request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int (*filter)(const struct rc_scancode_filter *in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct img_ir_filter *out, u64 protocols);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) extern struct img_ir_decoder img_ir_nec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) extern struct img_ir_decoder img_ir_jvc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) extern struct img_ir_decoder img_ir_sony;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) extern struct img_ir_decoder img_ir_sharp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) extern struct img_ir_decoder img_ir_sanyo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) extern struct img_ir_decoder img_ir_rc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) extern struct img_ir_decoder img_ir_rc6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * struct img_ir_reg_timings - Reg values for decoder timings at clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @ctrl: Processed control register value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @timings: Processed primary timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @rtimings: Processed repeat timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct img_ir_reg_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct img_ir_timing_regvals timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct img_ir_timing_regvals rtimings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct img_ir_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #ifdef CONFIG_IR_IMG_HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) enum img_ir_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) IMG_IR_M_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IMG_IR_M_REPEATING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) IMG_IR_M_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * struct img_ir_priv_hw - Private driver data for hardware decoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @ct_quirks: Quirk bits for each code type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @rdev: Remote control device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @clk_nb: Notifier block for clock notify events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @end_timer: Timer until repeat timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @suspend_timer: Timer to re-enable protocol.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @decoder: Current decoder settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @enabled_protocols: Currently enabled protocols.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @clk_hz: Current core clock rate in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @reg_timings: Timing reg values for decoder at clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @flags: IMG_IR_F_*.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @filters: HW filters (derived from scancode filters).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @mode: Current decode mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @stopping: Indicates that decoder is being taken down and timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * should not be restarted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @suspend_irqen: Saved IRQ enable mask over suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @quirk_suspend_irq: Saved IRQ enable mask over quirk suspend timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct img_ir_priv_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned int ct_quirks[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct rc_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct notifier_block clk_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct timer_list end_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct timer_list suspend_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const struct img_ir_decoder *decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u64 enabled_protocols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long clk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct img_ir_reg_timings reg_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct img_ir_filter filters[RC_FILTER_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) enum img_ir_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) bool stopping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 suspend_irqen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 quirk_suspend_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline bool img_ir_hw_enabled(struct img_ir_priv_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return hw->rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) void img_ir_setup_hw(struct img_ir_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int img_ir_probe_hw(struct img_ir_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) void img_ir_remove_hw(struct img_ir_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int img_ir_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int img_ir_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define img_ir_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define img_ir_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct img_ir_priv_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline bool img_ir_hw_enabled(struct img_ir_priv_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static inline void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static inline void img_ir_setup_hw(struct img_ir_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static inline int img_ir_probe_hw(struct img_ir_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static inline void img_ir_remove_hw(struct img_ir_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define img_ir_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define img_ir_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif /* CONFIG_IR_IMG_HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif /* _IMG_IR_HW_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags