Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Special thanks to Fintek for providing hardware and spec sheets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This driver is based upon the nuvoton, ite and ene drivers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * similar hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* platform driver name to register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define FINTEK_DRIVER_NAME	"fintek-cir"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define FINTEK_DESCRIPTION	"Fintek LPC SuperIO Consumer IR Transceiver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define VENDOR_ID_FINTEK	0x1934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* debugging module parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define fit_pr(level, text, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define fit_dbg(text, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	if (debug) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		printk(KERN_DEBUG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define fit_dbg_verbose(text, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (debug > 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		printk(KERN_DEBUG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define fit_dbg_wake(text, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (debug > 2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		printk(KERN_DEBUG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 			KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TX_BUF_LEN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RX_BUF_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct fintek_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct pnp_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct rc_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	spinlock_t fintek_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* for rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u8 buf[RX_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned int pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		u8 buf[TX_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		unsigned int buf_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		unsigned int cur_buf_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		wait_queue_head_t queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	} tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	/* Config register index/data port pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32 cr_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 cr_dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* hardware I/O settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned long cir_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int cir_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int cir_port_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* hardware id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u8 chip_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u8 chip_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u16 chip_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u8 logical_dev_cir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* hardware features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	bool hw_learning_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	bool hw_tx_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* rx settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	bool learning_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	bool carrier_detect_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		CMD_HEADER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		SUBCMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		CMD_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		PARSE_IRDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	} parser_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u8 cmd, rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	/* carrier period = 1 / frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* buffer packet constants, largely identical to mceusb.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BUF_PULSE_BIT		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BUF_LEN_MASK		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BUF_SAMPLE_MASK		0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BUF_COMMAND_HEADER	0x9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BUF_COMMAND_MASK	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BUF_COMMAND_NULL	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BUF_HW_CMD_HEADER	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BUF_CMD_G_REVISION	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BUF_CMD_S_CARRIER	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BUF_CMD_S_TIMEOUT	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BUF_CMD_SIG_END		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BUF_CMD_S_TXMASK	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BUF_CMD_S_RXSENSOR	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BUF_RSP_PULSE_COUNT	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CIR_SAMPLE_PERIOD	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * Configuration Register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  *  Index Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *  Data Port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CR_INDEX_PORT		0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CR_DATA_PORT		0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Possible alternate values, depends on how the chip is wired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CR_INDEX_PORT2		0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CR_DATA_PORT2		0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * active. 1 = 0x4e, 0 = 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PORT_SEL_PORT_4E_EN	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Extended Function Mode enable/disable magic values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CONFIG_REG_ENABLE	0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CONFIG_REG_DISABLE	0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Chip IDs found in CR_CHIP_ID_{HI,LO} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CHIP_ID_HIGH_F71809U	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CHIP_ID_LOW_F71809U	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * Global control regs we need to care about:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *      Global Control                  def.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  *      Register name           addr    val. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCR_SOFTWARE_RESET	0x02 /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCR_LOGICAL_DEV_NO	0x07 /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCR_CHIP_ID_HI		0x20 /* 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCR_CHIP_ID_LO		0x21 /* 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GCR_VENDOR_ID_HI	0x23 /* 0x19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GCR_VENDOR_ID_LO	0x24 /* 0x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GCR_CONFIG_PORT_SEL	0x25 /* 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GCR_KBMOUSE_WAKEUP	0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LOGICAL_DEV_DISABLE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LOGICAL_DEV_ENABLE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Logical device number of the CIR function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define LOGICAL_DEV_CIR_REV1	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LOGICAL_DEV_CIR_REV2	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* CIR Logical Device (LDN 0x08) config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CIR_CR_COMMAND_INDEX	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CIR_CR_IRCS		0x05 /* Before host writes command to IR, host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 					must set to 1. When host finshes write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 					command to IR, host must clear to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CIR_CR_COMMAND_DATA	0x06 /* Host read or write command data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CIR_CR_CLASS		0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 					0x33 = rx + 1 tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CIR_CR_DEV_EN		0x30 /* bit0 = 1 enables CIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CIR_CR_BASE_ADDR_HI	0x60 /* MSB of CIR IO base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CIR_CR_BASE_ADDR_LO	0x61 /* LSB of CIR IO base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CIR_CR_IRQ_SEL		0x70 /* bits3-0 store CIR IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CIR_CR_PSOUT_STATUS	0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CIR_CR_WAKE_KEY3_ADDR	0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CIR_CR_WAKE_KEY3_CODE	0xf9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CIR_CR_WAKE_KEY3_DC	0xfa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CIR_CR_WAKE_CONTROL	0xfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CIR_CR_WAKE_KEY12_ADDR	0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CIR_CR_WAKE_KEY4_ADDR	0xfd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CIR_CR_WAKE_KEY5_ADDR	0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLASS_RX_ONLY		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLASS_RX_2TX		0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLASS_RX_1TX		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* CIR device registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CIR_STATUS		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CIR_RX_DATA		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CIR_TX_CONTROL		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CIR_TX_DATA		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CIR_CONTROL		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Bits to enable CIR wake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define LOGICAL_DEV_ACPI	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define LDEV_ACPI_WAKE_EN_REG	0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ACPI_WAKE_EN_CIR_BIT	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define LDEV_ACPI_PME_EN_REG	0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define LDEV_ACPI_PME_CLR_REG	0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ACPI_PME_CIR_BIT	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define LDEV_ACPI_STATE_REG	0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ACPI_STATE_CIR_BIT	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * CIR status register (0x00):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  *   7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  *   3 - TX_FINISH (1 when TX finished, write 1 to clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  *   2 - TX_UNDERRUN (1 on TX underrun, write 1 to clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  *   1 - RX_TIMEOUT (1 on RX timeout, write 1 to clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  *   0 - RX_RECEIVE (1 on RX receive, write 1 to clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CIR_STATUS_IRQ_EN	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CIR_STATUS_TX_FINISH	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CIR_STATUS_TX_UNDERRUN	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CIR_STATUS_RX_TIMEOUT	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CIR_STATUS_RX_RECEIVE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CIR_STATUS_IRQ_MASK	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * CIR TX control register (0x02):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  *   7 - TX_START (1 to indicate TX start, auto-cleared when done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  *   6 - TX_END (1 to indicate TX data written to TX fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CIR_TX_CONTROL_TX_START	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CIR_TX_CONTROL_TX_END	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)