^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * driver for ENE KB3926 B/C/D/E/F CIR (also known as ENE0XXX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* hardware address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ENE_STATUS 0 /* hardware status - unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ENE_ADDR_HI 1 /* hi byte of register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ENE_ADDR_LO 2 /* low byte of register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ENE_IO 3 /* read/write window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ENE_IO_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* 8 bytes of samples, divided in 2 packets*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ENE_FW_SAMPLE_SPACE 0x80 /* sample is space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ENE_FW_PACKET_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* first firmware flag register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ENE_FW1 0xF8F8 /* flagr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ENE_FW1_ENABLE 0x01 /* enable fw processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ENE_FW1_LED_ON 0x10 /* turn on a led */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ENE_FW1_IRQ 0x80 /* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* second firmware flag register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ENE_FW2 0xF8F9 /* flagw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ENE_FW2_EMMITER1_CONN 0x10 /* TX emmiter 1 connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ENE_FW2_EMMITER2_CONN 0x20 /* TX emmiter 2 connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* firmware RX pointer for new style buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ENE_FW_RX_POINTER 0xF8FA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* high parts of samples for fan input (8 samples)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ENE_FW_SMPL_BUF_FAN 0xF8FB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ENE_FW_SMPL_BUF_FAN_PLS 0x8000 /* combined sample is pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ENE_FW_SMPL_BUF_FAN_MSK 0x0FFF /* combined sample maximum value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* transmitter ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ENE_GPIOFS1 0xFC01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ENE_GPIOFS1_GPIO0D 0x20 /* enable tx output on GPIO0D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ENE_GPIOFS8 0xFC08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ENE_GPIOFS8_GPIO41 0x02 /* enable tx output on GPIO40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* IRQ registers block (for revision B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ENEB_IRQ 0xFD09 /* IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ENEB_IRQ_STATUS 0xFD80 /* irq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* fan as input settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ENE_FAN_AS_IN1_EN 0xCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ENE_FAN_AS_IN2_EN 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* IRQ registers block (for revision C,D) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ENE_IRQ 0xFE9B /* new irq settings register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ENE_IRQ_MASK 0x0F /* irq number mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ENE_IRQ_UNK_EN 0x10 /* always enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ENE_IRQ_STATUS 0x20 /* irq status and ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* CIR Config register #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ENE_CIRCFG 0xFEC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ENE_CIRCFG_RX_EN 0x01 /* RX enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ENE_CIRCFG_RX_IRQ 0x02 /* Enable hardware interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ENE_CIRCFG_REV_POL 0x04 /* Input polarity reversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ENE_CIRCFG_CARR_DEMOD 0x08 /* Enable carrier demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ENE_CIRCFG_TX_EN 0x10 /* TX enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ENE_CIRCFG_TX_IRQ 0x20 /* Send interrupt on TX done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ENE_CIRCFG_TX_POL_REV 0x40 /* TX polarity reversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ENE_CIRCFG_TX_CARR 0x80 /* send TX carrier or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* CIR config register #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ENE_CIRCFG2 0xFEC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ENE_CIRCFG2_RLC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ENE_CIRCFG2_RC5 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ENE_CIRCFG2_RC6 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ENE_CIRCFG2_NEC 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ENE_CIRCFG2_CARR_DETECT 0x10 /* Enable carrier detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ENE_CIRCFG2_GPIO0A 0x20 /* Use GPIO0A instead of GPIO40 for input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ENE_CIRCFG2_FAST_SAMPL1 0x40 /* Fast leading pulse detection for RC6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ENE_CIRCFG2_FAST_SAMPL2 0x80 /* Fast data detection for RC6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Knobs for protocol decoding - will document when/if will use them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ENE_CIRPF 0xFEC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ENE_CIRHIGH 0xFEC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ENE_CIRBIT 0xFEC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ENE_CIRSTART 0xFEC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ENE_CIRSTART2 0xFEC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Actual register which contains RLC RX data - read by firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ENE_CIRDAT_IN 0xFEC7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* RLC configuration - sample period (1us resolution) + idle mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ENE_CIRRLC_CFG 0xFEC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ENE_CIRRLC_CFG_OVERFLOW 0x80 /* interrupt on overflows if set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ENE_DEFAULT_SAMPLE_PERIOD 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Two byte RLC TX buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ENE_CIRRLC_OUT0 0xFEC9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ENE_CIRRLC_OUT1 0xFECA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ENE_CIRRLC_OUT_PULSE 0x80 /* Transmitted sample is pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ENE_CIRRLC_OUT_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Carrier detect setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Low nibble - number of carrier pulses to average
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * High nibble - number of initial carrier pulses to discard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ENE_CIRCAR_PULS 0xFECB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* detected RX carrier period (resolution: 500 ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ENE_CIRCAR_PRD 0xFECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ENE_CIRCAR_PRD_VALID 0x80 /* data valid content valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* detected RX carrier pulse width (resolution: 500 ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ENE_CIRCAR_HPRD 0xFECD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* TX period (resolution: 500 ns, minimum 2)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ENE_CIRMOD_PRD 0xFECE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ENE_CIRMOD_PRD_POL 0x80 /* TX carrier polarity*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ENE_CIRMOD_PRD_MAX 0x7F /* 15.87 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ENE_CIRMOD_PRD_MIN 0x02 /* 1 Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* TX pulse width (resolution: 500 ns)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ENE_CIRMOD_HPRD 0xFECF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Hardware versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ENE_ECHV 0xFF00 /* hardware revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ENE_PLLFRH 0xFF16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ENE_PLLFRL 0xFF17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ENE_DEFAULT_PLL_FREQ 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ENE_ECSTS 0xFF1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ENE_ECSTS_RSRVD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ENE_ECVER_MAJOR 0xFF1E /* chip version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ENE_ECVER_MINOR 0xFF1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ENE_HW_VER_OLD 0xFD00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ENE_DRIVER_NAME "ene_ir"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ENE_IRQ_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ENE_IRQ_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ENE_HW_B 1 /* 3926B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ENE_HW_C 2 /* 3926C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ENE_HW_D 3 /* 3926D or later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define __dbg(level, format, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (debug >= level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pr_info(format "\n", ## __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define dbg(format, ...) __dbg(1, format, ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define dbg_verbose(format, ...) __dbg(2, format, ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define dbg_regs(format, ...) __dbg(3, format, ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct ene_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct pnp_dev *pnp_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct rc_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* hw IO settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) long hw_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) spinlock_t hw_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* HW features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int hw_revision; /* hardware revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bool hw_use_gpio_0a; /* gpio0a is demodulated input*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bool hw_extra_buffer; /* hardware has 'extra buffer' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool hw_fan_input; /* fan input is IR data source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bool hw_learning_and_tx_capable; /* learning & tx capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int pll_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int buffer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Extra RX buffer location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int extra_buf1_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int extra_buf1_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int extra_buf2_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int extra_buf2_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* HW state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int r_pointer; /* pointer to next sample to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int w_pointer; /* pointer to next sample hw will write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bool rx_fan_input_inuse; /* is fan input in use for rx*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int tx_reg; /* current reg used for TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 saved_conf1; /* saved FEC0 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int tx_sample; /* current sample for TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) bool tx_sample_pulse; /* current sample is pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* TX buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned *tx_buffer; /* input samples buffer*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int tx_pos; /* position in that buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int tx_len; /* current len of tx buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int tx_done; /* done transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* one more sample pending*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct completion tx_complete; /* TX completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct timer_list tx_sim_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* TX settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int tx_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int tx_duty_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int transmitter_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* RX settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) bool learning_mode_enabled; /* learning input enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) bool carrier_detect_enabled; /* carrier detect enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int rx_period_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) bool rx_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int ene_irq_status(struct ene_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void ene_rx_read_hw_pointer(struct ene_device *dev);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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