^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * drivers/media/radio/si4713-i2c.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Property and commands definitions for Si4713 radio transmitter chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2008 Instituto Nokia de Tecnologia - INdT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contact: Eduardo Valentin <eduardo.valentin@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * version 2. This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef SI4713_I2C_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SI4713_I2C_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_data/media/si4713.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SI4713_PRODUCT_NUMBER 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Command Timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DEFAULT_TIMEOUT 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TIMEOUT_SET_PROPERTY 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TIMEOUT_TX_TUNE_POWER 30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TIMEOUT_TX_TUNE 110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TIMEOUT_POWER_UP 200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Command and its arguments definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SI4713_PWUP_CTSIEN (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SI4713_PWUP_GPO2OEN (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SI4713_PWUP_PATCH (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SI4713_PWUP_XOSCEN (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SI4713_PWUP_FUNC_TX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SI4713_PWUP_FUNC_PATCH 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SI4713_PWUP_OPMOD_ANALOG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SI4713_PWUP_OPMOD_DIGITAL 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SI4713_PWUP_NARGS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SI4713_PWUP_NRESP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SI4713_CMD_POWER_UP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SI4713_GETREV_NRESP 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SI4713_CMD_GET_REV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SI4713_PWDN_NRESP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SI4713_CMD_POWER_DOWN 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SI4713_SET_PROP_NARGS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SI4713_SET_PROP_NRESP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SI4713_CMD_SET_PROPERTY 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SI4713_GET_PROP_NARGS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SI4713_GET_PROP_NRESP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SI4713_CMD_GET_PROPERTY 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SI4713_GET_STATUS_NRESP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SI4713_CMD_GET_INT_STATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SI4713_CMD_PATCH_ARGS 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SI4713_CMD_PATCH_DATA 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SI4713_MAX_FREQ 10800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SI4713_MIN_FREQ 7600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SI4713_TXFREQ_NARGS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SI4713_TXFREQ_NRESP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SI4713_CMD_TX_TUNE_FREQ 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SI4713_MAX_POWER 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SI4713_MIN_POWER 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SI4713_MAX_ANTCAP 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SI4713_MIN_ANTCAP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SI4713_TXPWR_NARGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SI4713_TXPWR_NRESP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SI4713_CMD_TX_TUNE_POWER 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SI4713_TXMEA_NARGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SI4713_TXMEA_NRESP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SI4713_CMD_TX_TUNE_MEASURE 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SI4713_INTACK_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SI4713_TXSTATUS_NARGS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SI4713_TXSTATUS_NRESP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SI4713_CMD_TX_TUNE_STATUS 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SI4713_OVERMOD_BIT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SI4713_IALH_BIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SI4713_IALL_BIT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SI4713_ASQSTATUS_NARGS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SI4713_ASQSTATUS_NRESP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SI4713_CMD_TX_ASQ_STATUS 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SI4713_RDSBUFF_MODE_MASK 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SI4713_RDSBUFF_NARGS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SI4713_RDSBUFF_NRESP 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SI4713_CMD_TX_RDS_BUFF 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SI4713_RDSPS_PSID_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SI4713_RDSPS_NARGS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SI4713_RDSPS_NRESP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SI4713_CMD_TX_RDS_PS 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SI4713_CMD_GPO_CTL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SI4713_CMD_GPO_SET 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Bits from status response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SI4713_CTS (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SI4713_ERR (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SI4713_RDS_INT (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SI4713_ASQ_INT (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SI4713_STC_INT (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Property definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SI4713_GPO_IEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SI4713_DIG_INPUT_FORMAT 0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SI4713_DIG_INPUT_SAMPLE_RATE 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SI4713_REFCLK_FREQ 0x0201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SI4713_REFCLK_PRESCALE 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SI4713_TX_COMPONENT_ENABLE 0x2100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SI4713_TX_AUDIO_DEVIATION 0x2101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SI4713_TX_PILOT_DEVIATION 0x2102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SI4713_TX_RDS_DEVIATION 0x2103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SI4713_TX_LINE_INPUT_LEVEL 0x2104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SI4713_TX_LINE_INPUT_MUTE 0x2105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SI4713_TX_PREEMPHASIS 0x2106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SI4713_TX_PILOT_FREQUENCY 0x2107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SI4713_TX_ACOMP_ENABLE 0x2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SI4713_TX_ACOMP_THRESHOLD 0x2201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SI4713_TX_ACOMP_ATTACK_TIME 0x2202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SI4713_TX_ACOMP_RELEASE_TIME 0x2203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SI4713_TX_ACOMP_GAIN 0x2204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SI4713_TX_LIMITER_RELEASE_TIME 0x2205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SI4713_TX_ASQ_INTERRUPT_SOURCE 0x2300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SI4713_TX_ASQ_LEVEL_LOW 0x2301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SI4713_TX_ASQ_DURATION_LOW 0x2302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SI4713_TX_ASQ_LEVEL_HIGH 0x2303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SI4713_TX_ASQ_DURATION_HIGH 0x2304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SI4713_TX_RDS_INTERRUPT_SOURCE 0x2C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SI4713_TX_RDS_PI 0x2C01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SI4713_TX_RDS_PS_MIX 0x2C02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SI4713_TX_RDS_PS_MISC 0x2C03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SI4713_TX_RDS_PS_REPEAT_COUNT 0x2C04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SI4713_TX_RDS_PS_MESSAGE_COUNT 0x2C05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SI4713_TX_RDS_PS_AF 0x2C06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SI4713_TX_RDS_FIFO_SIZE 0x2C07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PREEMPHASIS_USA 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PREEMPHASIS_EU 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PREEMPHASIS_DISABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define FMPE_USA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define FMPE_EU 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define FMPE_DISABLED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define POWER_UP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define POWER_DOWN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MAX_RDS_PTY 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MAX_RDS_DEVIATION 90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * PSNAME is known to be defined as 8 character sized (RDS Spec).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * However, there is receivers which scroll PSNAME 8xN sized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MAX_RDS_PS_NAME 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * MAX_RDS_RADIO_TEXT is known to be defined as 32 (2A group) or 64 (2B group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * character sized (RDS Spec).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * However, there is receivers which scroll them as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MAX_RDS_RADIO_TEXT 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MAX_LIMITER_RELEASE_TIME 102390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MAX_LIMITER_DEVIATION 90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MAX_PILOT_DEVIATION 90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MAX_PILOT_FREQUENCY 19000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MAX_ACOMP_RELEASE_TIME 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MAX_ACOMP_ATTACK_TIME 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MAX_ACOMP_THRESHOLD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MIN_ACOMP_THRESHOLD (-40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MAX_ACOMP_GAIN 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * si4713_device - private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct si4713_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* v4l2_subdev and i2c reference (v4l2_subdev priv data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* private data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct { /* si4713 control cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* This is one big cluster since the mute control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * powers off the device and after unmuting again all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * controls need to be set at once. The only way of doing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * that is by making it one big cluster. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct v4l2_ctrl *mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct v4l2_ctrl *rds_ps_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct v4l2_ctrl *rds_radio_text;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct v4l2_ctrl *rds_pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct v4l2_ctrl *rds_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct v4l2_ctrl *rds_pty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct v4l2_ctrl *rds_compressed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct v4l2_ctrl *rds_art_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct v4l2_ctrl *rds_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct v4l2_ctrl *rds_ta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct v4l2_ctrl *rds_tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct v4l2_ctrl *rds_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct v4l2_ctrl *rds_dyn_pty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct v4l2_ctrl *rds_alt_freqs_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct v4l2_ctrl *rds_alt_freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct v4l2_ctrl *compression_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct v4l2_ctrl *compression_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct v4l2_ctrl *compression_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct v4l2_ctrl *compression_attack_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct v4l2_ctrl *compression_release_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct v4l2_ctrl *pilot_tone_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct v4l2_ctrl *pilot_tone_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct v4l2_ctrl *pilot_tone_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct v4l2_ctrl *limiter_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct v4l2_ctrl *limiter_deviation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct v4l2_ctrl *limiter_release_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct v4l2_ctrl *tune_preemphasis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct v4l2_ctrl *tune_pwr_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct v4l2_ctrl *tune_ant_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct completion work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct regulator *vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct regulator *vio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct gpio_desc *gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct platform_device *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 power_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 rds_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 preemphasis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 tune_rnl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct radio_si4713_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct i2c_client *subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif /* ifndef SI4713_I2C_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags