^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/media/radio/si470x/radio-si470x.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for radios with Silicon Labs Si470x FM Radio Receivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2009 Tobias Lorenz <tobias.lorenz@gmx.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* driver definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DRIVER_NAME "radio-si470x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* kernel includes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Register Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RADIO_REGISTER_SIZE 2 /* 16 register bit width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RADIO_REGISTER_NUM 16 /* DEVICEID ... RDSD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RDS_REGISTER_NUM 6 /* STATUSRSSI ... RDSD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DEVICEID 0 /* Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DEVICEID_PN 0xf000 /* bits 15..12: Part Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DEVICEID_MFGID 0x0fff /* bits 11..00: Manufacturer ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SI_CHIPID 1 /* Chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SI_CHIPID_REV 0xfc00 /* bits 15..10: Chip Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SI_CHIPID_DEV 0x0200 /* bits 09..09: Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SI_CHIPID_FIRMWARE 0x01ff /* bits 08..00: Firmware Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define POWERCFG 2 /* Power Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define POWERCFG_DSMUTE 0x8000 /* bits 15..15: Softmute Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define POWERCFG_DMUTE 0x4000 /* bits 14..14: Mute Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define POWERCFG_MONO 0x2000 /* bits 13..13: Mono Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define POWERCFG_RDSM 0x0800 /* bits 11..11: RDS Mode (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define POWERCFG_SKMODE 0x0400 /* bits 10..10: Seek Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define POWERCFG_SEEKUP 0x0200 /* bits 09..09: Seek Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define POWERCFG_SEEK 0x0100 /* bits 08..08: Seek */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define POWERCFG_DISABLE 0x0040 /* bits 06..06: Powerup Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define POWERCFG_ENABLE 0x0001 /* bits 00..00: Powerup Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CHANNEL 3 /* Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CHANNEL_TUNE 0x8000 /* bits 15..15: Tune */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CHANNEL_CHAN 0x03ff /* bits 09..00: Channel Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SYSCONFIG1 4 /* System Configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SYSCONFIG1_RDSIEN 0x8000 /* bits 15..15: RDS Interrupt Enable (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SYSCONFIG1_STCIEN 0x4000 /* bits 14..14: Seek/Tune Complete Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SYSCONFIG1_RDS 0x1000 /* bits 12..12: RDS Enable (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SYSCONFIG1_DE 0x0800 /* bits 11..11: De-emphasis (0=75us 1=50us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SYSCONFIG1_AGCD 0x0400 /* bits 10..10: AGC Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SYSCONFIG1_BLNDADJ 0x00c0 /* bits 07..06: Stereo/Mono Blend Level Adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SYSCONFIG1_GPIO3 0x0030 /* bits 05..04: General Purpose I/O 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SYSCONFIG1_GPIO2 0x000c /* bits 03..02: General Purpose I/O 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SYSCONFIG1_GPIO2_DIS 0x0000 /* Disable GPIO 2 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SYSCONFIG1_GPIO2_INT 0x0004 /* Enable STC/RDS interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SYSCONFIG1_GPIO1 0x0003 /* bits 01..00: General Purpose I/O 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SYSCONFIG2 5 /* System Configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SYSCONFIG2_SEEKTH 0xff00 /* bits 15..08: RSSI Seek Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SYSCONFIG2_BAND 0x00c0 /* bits 07..06: Band Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SYSCONFIG2_SPACE 0x0030 /* bits 05..04: Channel Spacing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SYSCONFIG2_VOLUME 0x000f /* bits 03..00: Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SYSCONFIG3 6 /* System Configuration 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SYSCONFIG3_SMUTER 0xc000 /* bits 15..14: Softmute Attack/Recover Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SYSCONFIG3_SMUTEA 0x3000 /* bits 13..12: Softmute Attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SYSCONFIG3_SKSNR 0x00f0 /* bits 07..04: Seek SNR Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SYSCONFIG3_SKCNT 0x000f /* bits 03..00: Seek FM Impulse Detection Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEST1 7 /* Test 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEST1_AHIZEN 0x4000 /* bits 14..14: Audio High-Z Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEST2 8 /* Test 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* TEST2 only contains reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BOOTCONFIG 9 /* Boot Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* BOOTCONFIG only contains reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STATUSRSSI 10 /* Status RSSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define STATUSRSSI_RDSR 0x8000 /* bits 15..15: RDS Ready (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define STATUSRSSI_STC 0x4000 /* bits 14..14: Seek/Tune Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STATUSRSSI_SF 0x2000 /* bits 13..13: Seek Fail/Band Limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STATUSRSSI_AFCRL 0x1000 /* bits 12..12: AFC Rail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define STATUSRSSI_RDSS 0x0800 /* bits 11..11: RDS Synchronized (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define STATUSRSSI_BLERA 0x0600 /* bits 10..09: RDS Block A Errors (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define STATUSRSSI_ST 0x0100 /* bits 08..08: Stereo Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define STATUSRSSI_RSSI 0x00ff /* bits 07..00: RSSI (Received Signal Strength Indicator) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define READCHAN 11 /* Read Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define READCHAN_BLERB 0xc000 /* bits 15..14: RDS Block D Errors (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define READCHAN_BLERC 0x3000 /* bits 13..12: RDS Block C Errors (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define READCHAN_BLERD 0x0c00 /* bits 11..10: RDS Block B Errors (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define READCHAN_READCHAN 0x03ff /* bits 09..00: Read Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RDSA 12 /* RDSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RDSA_RDSA 0xffff /* bits 15..00: RDS Block A Data (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RDSB 13 /* RDSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RDSB_RDSB 0xffff /* bits 15..00: RDS Block B Data (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RDSC 14 /* RDSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RDSC_RDSC 0xffff /* bits 15..00: RDS Block C Data (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RDSD 15 /* RDSD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RDSD_RDSD 0xffff /* bits 15..00: RDS Block D Data (Si4701 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * General Driver Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * si470x_device - private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct si470x_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_device v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct video_device videodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Silabs internal registers (0..15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned short registers[RADIO_REGISTER_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* RDS receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) wait_queue_head_t read_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct mutex lock; /* buffer locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned char *buffer; /* size is always multiple of three */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int rd_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int wr_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bool status_rssi_auto_update; /* Does RSSI get updated automatic? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* si470x ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int (*get_register)(struct si470x_device *radio, int regnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int (*set_register)(struct si470x_device *radio, int regnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int (*fops_open)(struct file *file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int (*fops_release)(struct file *file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int (*vidioc_querycap)(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct v4l2_capability *capability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #if IS_ENABLED(CONFIG_USB_SI470X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* reference to USB and video device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct usb_device *usbdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct usb_interface *intf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) char *usb_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Interrupt endpoint handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) char *int_in_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct usb_endpoint_descriptor *int_in_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct urb *int_in_urb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int int_in_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* scratch page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned char software_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned char hardware_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #if IS_ENABLED(CONFIG_I2C_SI470X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct gpio_desc *gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Firmware Versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RADIO_FW_VERSION 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Frequency Multiplicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * The frequency is set in units of 62.5 Hz when using V4L2_TUNER_CAP_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * 62.5 kHz otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * The tuner is able to have a channel spacing of 50, 100 or 200 kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * tuner->capability is therefore set to V4L2_TUNER_CAP_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * The FREQ_MUL is then: 1 MHz / 62.5 Hz = 16000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define FREQ_MUL (1000000 / 62.5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Common Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) extern const struct video_device si470x_viddev_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) extern const struct v4l2_ctrl_ops si470x_ctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int si470x_disconnect_check(struct si470x_device *radio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int si470x_set_freq(struct si470x_device *radio, unsigned int freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int si470x_start(struct si470x_device *radio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int si470x_stop(struct si470x_device *radio);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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