Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * saa7706.c Philips SAA7706H Car Radio DSP driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2009 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DRIVER_NAME "saa7706h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* the I2C memory map looks like this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	$1C00 - $FFFF Not Used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	$2200 - $3FFF Reserved YRAM (DSP2) space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	$2000 - $21FF YRAM (DSP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	$1FF0 - $1FFF Hardware Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	$1280 - $1FEF Reserved XRAM (DSP2) space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	$1000 - $127F XRAM (DSP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	$0FFF        DSP CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	$0A00 - $0FFE Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	$0980 - $09FF Reserved YRAM (DSP1) space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	$0800 - $097F YRAM (DSP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	$0200 - $07FF Not Used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	$0180 - $01FF Reserved XRAM (DSP1) space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	$0000 - $017F XRAM (DSP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SAA7706H_REG_CTRL		0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SAA7706H_CTRL_BYP_PLL		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SAA7706H_CTRL_PLL_DIV_MASK	0x003e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SAA7706H_CTRL_PLL3_62975MHZ	0x003e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SAA7706H_CTRL_DSP_TURBO		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SAA7706H_CTRL_PC_RESET_DSP1	0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SAA7706H_CTRL_PC_RESET_DSP2	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SAA7706H_CTRL_DSP1_ROM_EN_MASK	0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SAA7706H_CTRL_DSP1_FUNC_PROM	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SAA7706H_CTRL_DSP2_ROM_EN_MASK	0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SAA7706H_CTRL_DSP2_FUNC_PROM	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SAA7706H_CTRL_DIG_SIL_INTERPOL	0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SAA7706H_REG_EVALUATION			0x1ff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SAA7706H_EVAL_DISABLE_CHARGE_PUMP	0x000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SAA7706H_EVAL_DCS_CLOCK			0x000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SAA7706H_EVAL_GNDRC1_ENABLE		0x000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SAA7706H_EVAL_GNDRC2_ENABLE		0x000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SAA7706H_REG_CL_GEN1			0x1ff3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SAA7706H_CL_GEN1_MIN_LOOPGAIN_MASK	0x00000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SAA7706H_CL_GEN1_LOOPGAIN_MASK		0x0000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SAA7706H_CL_GEN1_COARSE_RATION		0xffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SAA7706H_REG_CL_GEN2			0x1ff4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SAA7706H_CL_GEN2_WSEDGE_FALLING		0x000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SAA7706H_CL_GEN2_STOP_VCO		0x000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SAA7706H_CL_GEN2_FRERUN			0x000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SAA7706H_CL_GEN2_ADAPTIVE		0x000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SAA7706H_CL_GEN2_FINE_RATIO_MASK	0x0ffff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SAA7706H_REG_CL_GEN4		0x1ff6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SAA7706H_CL_GEN4_BYPASS_PLL1	0x001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SAA7706H_CL_GEN4_PLL1_DIV_MASK	0x03e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SAA7706H_CL_GEN4_DSP1_TURBO	0x040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SAA7706H_REG_SEL	0x1ff7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SAA7706H_SEL_DSP2_SRCA_MASK	0x000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SAA7706H_SEL_DSP2_FMTA_MASK	0x000031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SAA7706H_SEL_DSP2_SRCB_MASK	0x0001c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SAA7706H_SEL_DSP2_FMTB_MASK	0x000e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SAA7706H_SEL_DSP1_SRC_MASK	0x003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SAA7706H_SEL_DSP1_FMT_MASK	0x01c003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define SAA7706H_SEL_SPDIF2		0x020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define SAA7706H_SEL_HOST_IO_FMT_MASK	0x1c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define SAA7706H_SEL_EN_HOST_IO		0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SAA7706H_REG_IAC		0x1ff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SAA7706H_REG_CLK_SET		0x1ff9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SAA7706H_REG_CLK_COEFF		0x1ffa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SAA7706H_REG_INPUT_SENS		0x1ffb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SAA7706H_INPUT_SENS_RDS_VOL_MASK	0x0003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SAA7706H_INPUT_SENS_FM_VOL_MASK		0x00fc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SAA7706H_INPUT_SENS_FM_MPX		0x01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SAA7706H_INPUT_SENS_OFF_FILTER_A_EN	0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define SAA7706H_INPUT_SENS_OFF_FILTER_B_EN	0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SAA7706H_REG_PHONE_NAV_AUDIO	0x1ffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SAA7706H_REG_IO_CONF_DSP2	0x1ffd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define SAA7706H_REG_STATUS_DSP2	0x1ffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SAA7706H_REG_PC_DSP2		0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SAA7706H_DSP1_MOD0	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define SAA7706H_DSP1_ROM_VER	0x097f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SAA7706H_DSP2_MPTR0	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SAA7706H_DSP1_MODPNTR	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SAA7706H_DSP2_XMEM_CONTLLCW	0x113e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SAA7706H_DSP2_XMEM_BUSAMP	0x114a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SAA7706H_DSP2_XMEM_FDACPNTR	0x11f9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SAA7706H_DSP2_XMEM_IIS1PNTR	0x11fb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SAA7706H_DSP2_YMEM_PVGA		0x212a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SAA7706H_DSP2_YMEM_PVAT1	0x212b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SAA7706H_DSP2_YMEM_PVAT		0x212c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SAA7706H_DSP2_YMEM_ROM_VER	0x21ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SUPPORTED_DSP1_ROM_VER		0x667
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct saa7706h_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned muted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline struct saa7706h_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return container_of(sd, struct saa7706h_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int saa7706h_i2c_send(struct i2c_client *client, const u8 *data, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int err = i2c_master_send(client, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (err == len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return err > 0 ? -EIO : err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int saa7706h_i2c_transfer(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int err = i2c_transfer(client->adapter, msgs, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (err == num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return err > 0 ? -EIO : err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int saa7706h_set_reg24(struct v4l2_subdev *sd, u16 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u8 buf[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	buf[pos++] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	buf[pos++] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	buf[pos++] = val >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	buf[pos++] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	buf[pos++] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return saa7706h_i2c_send(client, buf, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int saa7706h_set_reg24_err(struct v4l2_subdev *sd, u16 reg, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	int *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return *err ? *err : saa7706h_set_reg24(sd, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int saa7706h_set_reg16(struct v4l2_subdev *sd, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	int pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	buf[pos++] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	buf[pos++] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	buf[pos++] = val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	buf[pos++] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return saa7706h_i2c_send(client, buf, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int saa7706h_set_reg16_err(struct v4l2_subdev *sd, u16 reg, u16 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return *err ? *err : saa7706h_set_reg16(sd, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int saa7706h_get_reg16(struct v4l2_subdev *sd, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u8 regaddr[] = {reg >> 8, reg};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 					{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 						.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 						.len = sizeof(regaddr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 						.buf = regaddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 					},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 					{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 						.addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 						.flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 						.len = sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 						.buf = buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 					}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	err = saa7706h_i2c_transfer(client, msg, ARRAY_SIZE(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return buf[0] << 8 | buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int saa7706h_unmute(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct saa7706h_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	err = saa7706h_set_reg16_err(sd, SAA7706H_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		SAA7706H_CTRL_PLL3_62975MHZ | SAA7706H_CTRL_PC_RESET_DSP1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		SAA7706H_CTRL_PC_RESET_DSP2, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* newer versions of the chip requires a small sleep after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	err = saa7706h_set_reg16_err(sd, SAA7706H_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		SAA7706H_CTRL_PLL3_62975MHZ, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_EVALUATION, 0, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_CL_GEN1, 0x040022, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_CL_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		SAA7706H_CL_GEN2_WSEDGE_FALLING, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_CL_GEN4, 0x024080, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_SEL, 0x200080, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_IAC, 0xf4caed, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_CLK_SET, 0x124334, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_CLK_COEFF, 0x004a1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_INPUT_SENS, 0x0071c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_PHONE_NAV_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		0x0e22ff, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_IO_CONF_DSP2, 0x001ff8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_STATUS_DSP2, 0x080003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	err = saa7706h_set_reg24_err(sd, SAA7706H_REG_PC_DSP2, 0x000004, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	err = saa7706h_set_reg16_err(sd, SAA7706H_DSP1_MOD0, 0x0c6c, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	err = saa7706h_set_reg24_err(sd, SAA7706H_DSP2_MPTR0, 0x000b4b, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	err = saa7706h_set_reg24_err(sd, SAA7706H_DSP1_MODPNTR, 0x000600, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	err = saa7706h_set_reg24_err(sd, SAA7706H_DSP1_MODPNTR, 0x0000c0, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	err = saa7706h_set_reg24_err(sd, SAA7706H_DSP2_XMEM_CONTLLCW, 0x000819,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	err = saa7706h_set_reg24_err(sd, SAA7706H_DSP2_XMEM_CONTLLCW, 0x00085a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	err = saa7706h_set_reg24_err(sd, SAA7706H_DSP2_XMEM_BUSAMP, 0x7fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	err = saa7706h_set_reg24_err(sd, SAA7706H_DSP2_XMEM_FDACPNTR, 0x2000cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	err = saa7706h_set_reg24_err(sd, SAA7706H_DSP2_XMEM_IIS1PNTR, 0x2000cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	err = saa7706h_set_reg16_err(sd, SAA7706H_DSP2_YMEM_PVGA, 0x0f80, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	err = saa7706h_set_reg16_err(sd, SAA7706H_DSP2_YMEM_PVAT1, 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	err = saa7706h_set_reg16_err(sd, SAA7706H_DSP2_YMEM_PVAT, 0x0800, &err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	err = saa7706h_set_reg24_err(sd, SAA7706H_DSP2_XMEM_CONTLLCW, 0x000905,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		&err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		state->muted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int saa7706h_mute(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct saa7706h_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	err = saa7706h_set_reg16(sd, SAA7706H_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		SAA7706H_CTRL_PLL3_62975MHZ | SAA7706H_CTRL_PC_RESET_DSP1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		SAA7706H_CTRL_PC_RESET_DSP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		state->muted = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int saa7706h_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct saa7706h_state *state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		container_of(ctrl->handler, struct saa7706h_state, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	case V4L2_CID_AUDIO_MUTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			return saa7706h_mute(&state->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return saa7706h_unmute(&state->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct v4l2_ctrl_ops saa7706h_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.s_ctrl = saa7706h_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct v4l2_subdev_ops empty_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)  * Generic i2c probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)  * concerning the addresses: i2c wants 7 bit (without the r/w bit), so '>>1'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int saa7706h_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			  const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct saa7706h_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	/* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	v4l_info(client, "chip found @ 0x%02x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	state = kzalloc(sizeof(struct saa7706h_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	v4l2_i2c_subdev_init(sd, client, &empty_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	v4l2_ctrl_handler_init(&state->hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	v4l2_ctrl_new_std(&state->hdl, &saa7706h_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			V4L2_CID_AUDIO_MUTE, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	sd->ctrl_handler = &state->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	err = state->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	/* check the rom versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	err = saa7706h_get_reg16(sd, SAA7706H_DSP1_ROM_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (err != SUPPORTED_DSP1_ROM_VER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		v4l2_warn(sd, "Unknown DSP1 ROM code version: 0x%x\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	state->muted = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	/* startup in a muted state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	err = saa7706h_mute(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	kfree(to_state(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	printk(KERN_ERR DRIVER_NAME ": Failed to probe: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int saa7706h_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	struct saa7706h_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	saa7706h_mute(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	kfree(to_state(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct i2c_device_id saa7706h_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	{DRIVER_NAME, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_DEVICE_TABLE(i2c, saa7706h_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static struct i2c_driver saa7706h_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		.name	= DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.probe		= saa7706h_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.remove		= saa7706h_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.id_table	= saa7706h_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) module_i2c_driver(saa7706h_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MODULE_DESCRIPTION("SAA7706H Car Radio DSP driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MODULE_AUTHOR("Mocean Laboratories");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MODULE_LICENSE("GPL v2");