^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i.MX Pixel Pipeline (PXP) mem-to-mem scaler/CSC/rotator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 Pengutronix, Philipp Zabel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on vim2m
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Pawel Osciak, <pawel@osciak.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Marek Szyprowski, <m.szyprowski@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-mem2mem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/videobuf2-dma-contig.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "imx-pxp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static unsigned int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) module_param(debug, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODULE_PARM_DESC(debug, "activates debug info");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MIN_W 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MIN_H 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MAX_W 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MAX_H 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ALIGN_W 3 /* 8x8 pixel blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ALIGN_H 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Flags that indicate a format can be used for capture/output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MEM2MEM_CAPTURE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MEM2MEM_OUTPUT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MEM2MEM_NAME "pxp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Flags that indicate processing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MEM2MEM_HFLIP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MEM2MEM_VFLIP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define dprintk(dev, fmt, arg...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) v4l2_dbg(1, debug, &dev->v4l2_dev, "%s: " fmt, __func__, ## arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct pxp_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Types the format can be used for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct pxp_fmt formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .fourcc = V4L2_PIX_FMT_XBGR32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .depth = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Both capture and output format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .fourcc = V4L2_PIX_FMT_ABGR32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .depth = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Capture-only format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .types = MEM2MEM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .fourcc = V4L2_PIX_FMT_BGR24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .depth = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .types = MEM2MEM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .fourcc = V4L2_PIX_FMT_RGB565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .fourcc = V4L2_PIX_FMT_RGB555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .fourcc = V4L2_PIX_FMT_RGB444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .fourcc = V4L2_PIX_FMT_VUYA32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .depth = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .types = MEM2MEM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .fourcc = V4L2_PIX_FMT_VUYX32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .depth = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .fourcc = V4L2_PIX_FMT_UYVY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .fourcc = V4L2_PIX_FMT_YUYV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Output-only format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .types = MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .fourcc = V4L2_PIX_FMT_VYUY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .fourcc = V4L2_PIX_FMT_YVYU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .types = MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .fourcc = V4L2_PIX_FMT_GREY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .depth = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .fourcc = V4L2_PIX_FMT_Y4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .depth = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .fourcc = V4L2_PIX_FMT_NV16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .fourcc = V4L2_PIX_FMT_NV12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .depth = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .fourcc = V4L2_PIX_FMT_NV21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .depth = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .fourcc = V4L2_PIX_FMT_NV61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .fourcc = V4L2_PIX_FMT_YUV422P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .types = MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .fourcc = V4L2_PIX_FMT_YUV420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .depth = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .types = MEM2MEM_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define NUM_FORMATS ARRAY_SIZE(formats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Per-queue, driver-specific private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pxp_q_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int bytesperline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int sizeimage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct pxp_fmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum v4l2_ycbcr_encoding ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum v4l2_quantization quant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) V4L2_M2M_SRC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) V4L2_M2M_DST = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct pxp_fmt *find_format(struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct pxp_fmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for (k = 0; k < NUM_FORMATS; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) fmt = &formats[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (fmt->fourcc == f->fmt.pix.pixelformat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (k == NUM_FORMATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return &formats[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct pxp_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct v4l2_device v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct video_device vfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) atomic_t num_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct mutex dev_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spinlock_t irqlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct v4l2_m2m_dev *m2m_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct pxp_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct v4l2_fh fh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct pxp_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Abort requested by m2m */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int aborting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Processing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 alpha_component;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) enum v4l2_colorspace colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enum v4l2_xfer_func xfer_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Source and destination queue data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct pxp_q_data q_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline struct pxp_ctx *file2ctx(struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return container_of(file->private_data, struct pxp_ctx, fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct pxp_q_data *get_q_data(struct pxp_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) enum v4l2_buf_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return &ctx->q_data[V4L2_M2M_SRC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return &ctx->q_data[V4L2_M2M_DST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static u32 pxp_v4l2_pix_fmt_to_ps_format(u32 v4l2_pix_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) switch (v4l2_pix_fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case V4L2_PIX_FMT_XBGR32: return BV_PXP_PS_CTRL_FORMAT__RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case V4L2_PIX_FMT_RGB555: return BV_PXP_PS_CTRL_FORMAT__RGB555;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case V4L2_PIX_FMT_RGB444: return BV_PXP_PS_CTRL_FORMAT__RGB444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case V4L2_PIX_FMT_RGB565: return BV_PXP_PS_CTRL_FORMAT__RGB565;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case V4L2_PIX_FMT_VUYX32: return BV_PXP_PS_CTRL_FORMAT__YUV1P444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case V4L2_PIX_FMT_UYVY: return BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case V4L2_PIX_FMT_YUYV: return BM_PXP_PS_CTRL_WB_SWAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case V4L2_PIX_FMT_VYUY: return BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case V4L2_PIX_FMT_YVYU: return BM_PXP_PS_CTRL_WB_SWAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case V4L2_PIX_FMT_GREY: return BV_PXP_PS_CTRL_FORMAT__Y8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case V4L2_PIX_FMT_Y4: return BV_PXP_PS_CTRL_FORMAT__Y4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case V4L2_PIX_FMT_NV16: return BV_PXP_PS_CTRL_FORMAT__YUV2P422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case V4L2_PIX_FMT_NV12: return BV_PXP_PS_CTRL_FORMAT__YUV2P420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case V4L2_PIX_FMT_NV21: return BV_PXP_PS_CTRL_FORMAT__YVU2P420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case V4L2_PIX_FMT_NV61: return BV_PXP_PS_CTRL_FORMAT__YVU2P422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case V4L2_PIX_FMT_YUV422P: return BV_PXP_PS_CTRL_FORMAT__YUV422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case V4L2_PIX_FMT_YUV420: return BV_PXP_PS_CTRL_FORMAT__YUV420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static u32 pxp_v4l2_pix_fmt_to_out_format(u32 v4l2_pix_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) switch (v4l2_pix_fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case V4L2_PIX_FMT_XBGR32: return BV_PXP_OUT_CTRL_FORMAT__RGB888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case V4L2_PIX_FMT_ABGR32: return BV_PXP_OUT_CTRL_FORMAT__ARGB8888;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case V4L2_PIX_FMT_BGR24: return BV_PXP_OUT_CTRL_FORMAT__RGB888P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Missing V4L2 pixel formats for ARGB1555 and ARGB4444 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case V4L2_PIX_FMT_RGB555: return BV_PXP_OUT_CTRL_FORMAT__RGB555;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case V4L2_PIX_FMT_RGB444: return BV_PXP_OUT_CTRL_FORMAT__RGB444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case V4L2_PIX_FMT_RGB565: return BV_PXP_OUT_CTRL_FORMAT__RGB565;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case V4L2_PIX_FMT_VUYA32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case V4L2_PIX_FMT_VUYX32: return BV_PXP_OUT_CTRL_FORMAT__YUV1P444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case V4L2_PIX_FMT_UYVY: return BV_PXP_OUT_CTRL_FORMAT__UYVY1P422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case V4L2_PIX_FMT_VYUY: return BV_PXP_OUT_CTRL_FORMAT__VYUY1P422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case V4L2_PIX_FMT_GREY: return BV_PXP_OUT_CTRL_FORMAT__Y8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case V4L2_PIX_FMT_Y4: return BV_PXP_OUT_CTRL_FORMAT__Y4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case V4L2_PIX_FMT_NV16: return BV_PXP_OUT_CTRL_FORMAT__YUV2P422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case V4L2_PIX_FMT_NV12: return BV_PXP_OUT_CTRL_FORMAT__YUV2P420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case V4L2_PIX_FMT_NV61: return BV_PXP_OUT_CTRL_FORMAT__YVU2P422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case V4L2_PIX_FMT_NV21: return BV_PXP_OUT_CTRL_FORMAT__YVU2P420;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static bool pxp_v4l2_pix_fmt_is_yuv(u32 v4l2_pix_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) switch (v4l2_pix_fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case V4L2_PIX_FMT_VUYA32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case V4L2_PIX_FMT_VUYX32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case V4L2_PIX_FMT_UYVY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case V4L2_PIX_FMT_YUYV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case V4L2_PIX_FMT_VYUY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case V4L2_PIX_FMT_YVYU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case V4L2_PIX_FMT_NV16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case V4L2_PIX_FMT_NV12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case V4L2_PIX_FMT_NV61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case V4L2_PIX_FMT_NV21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case V4L2_PIX_FMT_YUV420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case V4L2_PIX_FMT_YUV422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case V4L2_PIX_FMT_GREY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case V4L2_PIX_FMT_Y4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void pxp_setup_csc(struct pxp_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct pxp_dev *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum v4l2_ycbcr_encoding ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) enum v4l2_quantization quantization;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) !pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * CSC1 YUV/YCbCr to RGB conversion is implemented as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * |R| |C0 0 C1| |Y + Yoffset |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * |G| = |C0 C3 C2| * |Cb + UVoffset|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * |B| |C0 C4 0 | |Cr + UVoffset|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * Results are clamped to 0..255.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * BT.601 limited range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * |R| |1.1644 0.0000 1.5960| |Y - 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * |G| = |1.1644 -0.3917 -0.8129| * |Cb - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * |B| |1.1644 2.0172 0.0000| |Cr - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const u32 csc1_coef_bt601_lim[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) BM_PXP_CSC1_COEF0_YCBCR_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) BF_PXP_CSC1_COEF1_C1(0x198) | /* 1.5938 (-0.23 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) BF_PXP_CSC1_COEF1_C4(0x204), /* 2.0156 (-0.16 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) BF_PXP_CSC1_COEF2_C2(0x730) | /* -0.8125 (+0.04 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) BF_PXP_CSC1_COEF2_C3(0x79c), /* -0.3906 (+0.11 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * BT.601 full range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * |R| |1.0000 0.0000 1.4020| |Y + 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * |G| = |1.0000 -0.3441 -0.7141| * |Cb - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * |B| |1.0000 1.7720 0.0000| |Cr - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const u32 csc1_coef_bt601_full[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) BM_PXP_CSC1_COEF0_YCBCR_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) BF_PXP_CSC1_COEF0_Y_OFFSET(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) BF_PXP_CSC1_COEF1_C1(0x166) | /* 1.3984 (-0.36 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) BF_PXP_CSC1_COEF1_C4(0x1c5), /* 1.7695 (-0.25 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) BF_PXP_CSC1_COEF2_C2(0x74a) | /* -0.7109 (+0.32 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) BF_PXP_CSC1_COEF2_C3(0x7a8), /* -0.3438 (+0.04 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Rec.709 limited range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * |R| |1.1644 0.0000 1.7927| |Y - 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * |G| = |1.1644 -0.2132 -0.5329| * |Cb - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * |B| |1.1644 2.1124 0.0000| |Cr - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const u32 csc1_coef_rec709_lim[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) BM_PXP_CSC1_COEF0_YCBCR_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) BF_PXP_CSC1_COEF1_C1(0x1ca) | /* 1.7891 (-0.37 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) BF_PXP_CSC1_COEF1_C4(0x21c), /* 2.1094 (-0.30 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) BF_PXP_CSC1_COEF2_C2(0x778) | /* -0.5312 (+0.16 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) BF_PXP_CSC1_COEF2_C3(0x7ca), /* -0.2109 (+0.23 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Rec.709 full range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * |R| |1.0000 0.0000 1.5748| |Y + 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * |G| = |1.0000 -0.1873 -0.4681| * |Cb - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * |B| |1.0000 1.8556 0.0000| |Cr - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const u32 csc1_coef_rec709_full[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) BM_PXP_CSC1_COEF0_YCBCR_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BF_PXP_CSC1_COEF0_Y_OFFSET(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) BF_PXP_CSC1_COEF1_C1(0x193) | /* 1.5742 (-0.06 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) BF_PXP_CSC1_COEF1_C4(0x1db), /* 1.8555 (-0.01 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) BF_PXP_CSC1_COEF2_C2(0x789) | /* -0.4648 (+0.33 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) BF_PXP_CSC1_COEF2_C3(0x7d1), /* -0.1836 (+0.37 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * BT.2020 limited range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * |R| |1.1644 0.0000 1.6787| |Y - 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * |G| = |1.1644 -0.1874 -0.6505| * |Cb - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * |B| |1.1644 2.1418 0.0000| |Cr - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const u32 csc1_coef_bt2020_lim[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) BM_PXP_CSC1_COEF0_YCBCR_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) BF_PXP_CSC1_COEF1_C1(0x1ad) | /* 1.6758 (-0.29 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) BF_PXP_CSC1_COEF1_C4(0x224), /* 2.1406 (-0.11 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) BF_PXP_CSC1_COEF2_C2(0x75a) | /* -0.6484 (+0.20 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) BF_PXP_CSC1_COEF2_C3(0x7d1), /* -0.1836 (+0.38 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * BT.2020 full range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * |R| |1.0000 0.0000 1.4746| |Y + 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * |G| = |1.0000 -0.1646 -0.5714| * |Cb - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * |B| |1.0000 1.8814 0.0000| |Cr - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const u32 csc1_coef_bt2020_full[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) BM_PXP_CSC1_COEF0_YCBCR_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) BF_PXP_CSC1_COEF0_Y_OFFSET(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) BF_PXP_CSC1_COEF1_C1(0x179) | /* 1.4727 (-0.19 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) BF_PXP_CSC1_COEF1_C4(0x1e1), /* 1.8789 (-0.25 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) BF_PXP_CSC1_COEF2_C2(0x76e) | /* -0.5703 (+0.11 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) BF_PXP_CSC1_COEF2_C3(0x7d6), /* -0.1641 (+0.05 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * SMPTE 240m limited range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * |R| |1.1644 0.0000 1.7937| |Y - 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * |G| = |1.1644 -0.2565 -0.5427| * |Cb - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * |B| |1.1644 2.0798 0.0000| |Cr - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const u32 csc1_coef_smpte240m_lim[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) BM_PXP_CSC1_COEF0_YCBCR_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) BF_PXP_CSC1_COEF1_C1(0x1cb) | /* 1.7930 (-0.07 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) BF_PXP_CSC1_COEF1_C4(0x214), /* 2.0781 (-0.17 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) BF_PXP_CSC1_COEF2_C2(0x776) | /* -0.5391 (+0.36 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) BF_PXP_CSC1_COEF2_C3(0x7bf), /* -0.2539 (+0.26 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * SMPTE 240m full range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * |R| |1.0000 0.0000 1.5756| |Y + 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * |G| = |1.0000 -0.2253 -0.4767| * |Cb - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * |B| |1.0000 1.8270 0.0000| |Cr - 128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const u32 csc1_coef_smpte240m_full[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) BM_PXP_CSC1_COEF0_YCBCR_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) BF_PXP_CSC1_COEF0_Y_OFFSET(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) BF_PXP_CSC1_COEF1_C1(0x193) | /* 1.5742 (-0.14 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) BF_PXP_CSC1_COEF1_C4(0x1d3), /* 1.8242 (-0.28 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) BF_PXP_CSC1_COEF2_C2(0x786) | /* -0.4766 (+0.01 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) BF_PXP_CSC1_COEF2_C3(0x7c7), /* -0.2227 (+0.26 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) const u32 *csc1_coef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) quantization = ctx->q_data[V4L2_M2M_SRC].quant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) csc1_coef = csc1_coef_bt601_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) csc1_coef = csc1_coef_bt601_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) csc1_coef = csc1_coef_rec709_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) csc1_coef = csc1_coef_rec709_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else if (ycbcr_enc == V4L2_YCBCR_ENC_BT2020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) csc1_coef = csc1_coef_bt2020_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) csc1_coef = csc1_coef_bt2020_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) csc1_coef = csc1_coef_smpte240m_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) csc1_coef = csc1_coef_smpte240m_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) writel(csc1_coef[0], dev->mmio + HW_PXP_CSC1_COEF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) writel(csc1_coef[1], dev->mmio + HW_PXP_CSC1_COEF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) writel(csc1_coef[2], dev->mmio + HW_PXP_CSC1_COEF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) writel(BM_PXP_CSC1_COEF0_BYPASS, dev->mmio + HW_PXP_CSC1_COEF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * CSC2 RGB to YUV/YCbCr conversion is implemented as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * |Y | |A1 A2 A3| |R| |D1|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * |Cb| = |B1 B2 B3| * |G| + |D2|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * |Cr| |C1 C2 C3| |B| |D3|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Results are clamped to 0..255.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * BT.601 limited range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * |Y | | 0.2568 0.5041 0.0979| |R| |16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * |Cb| = |-0.1482 -0.2910 0.4392| * |G| + |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * |Cr| | 0.4392 0.4392 -0.3678| |B| |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const u32 csc2_coef_bt601_lim[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) BF_PXP_CSC2_COEF0_A2(0x081) | /* 0.5039 (-0.02 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) BF_PXP_CSC2_COEF0_A1(0x041), /* 0.2539 (-0.29 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) BF_PXP_CSC2_COEF1_B1(0x7db) | /* -0.1445 (+0.37 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) BF_PXP_CSC2_COEF1_A3(0x019), /* 0.0977 (-0.02 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) BF_PXP_CSC2_COEF2_B2(0x7b6), /* -0.2891 (+0.20 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) BF_PXP_CSC2_COEF3_C2(0x7a2) | /* -0.3672 (+0.06 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) BF_PXP_CSC2_COEF4_D1(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) BF_PXP_CSC2_COEF4_C3(0x7ee), /* -0.0703 (+0.11 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) BF_PXP_CSC2_COEF5_D3(128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) BF_PXP_CSC2_COEF5_D2(128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * BT.601 full range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * |Y | | 0.2990 0.5870 0.1140| |R| |0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * |Cb| = |-0.1687 -0.3313 0.5000| * |G| + |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * |Cr| | 0.5000 0.5000 -0.4187| |B| |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const u32 csc2_coef_bt601_full[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) BF_PXP_CSC2_COEF0_A2(0x096) | /* 0.5859 (-0.11 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) BF_PXP_CSC2_COEF0_A1(0x04c), /* 0.2969 (-0.21 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) BF_PXP_CSC2_COEF1_B1(0x7d5) | /* -0.1680 (+0.07 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) BF_PXP_CSC2_COEF1_A3(0x01d), /* 0.1133 (-0.07 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) BF_PXP_CSC2_COEF2_B2(0x7ac), /* -0.3281 (+0.32 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) BF_PXP_CSC2_COEF3_C2(0x795) | /* -0.4180 (+0.07 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) BF_PXP_CSC2_COEF4_D1(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) BF_PXP_CSC2_COEF4_C3(0x7ec), /* -0.0781 (+0.32 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) BF_PXP_CSC2_COEF5_D3(128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) BF_PXP_CSC2_COEF5_D2(128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * Rec.709 limited range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * |Y | | 0.1826 0.6142 0.0620| |R| |16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * |Cb| = |-0.1007 -0.3385 0.4392| * |G| + |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * |Cr| | 0.4392 0.4392 -0.3990| |B| |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const u32 csc2_coef_rec709_lim[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) BF_PXP_CSC2_COEF0_A2(0x09d) | /* 0.6133 (-0.09 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) BF_PXP_CSC2_COEF0_A1(0x02e), /* 0.1797 (-0.29 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) BF_PXP_CSC2_COEF1_B1(0x7e7) | /* -0.0977 (+0.30 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) BF_PXP_CSC2_COEF1_A3(0x00f), /* 0.0586 (-0.34 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) BF_PXP_CSC2_COEF2_B2(0x7aa), /* -0.3359 (+0.26 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) BF_PXP_CSC2_COEF3_C2(0x79a) | /* -0.3984 (+0.05 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) BF_PXP_CSC2_COEF4_D1(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) BF_PXP_CSC2_COEF4_C3(0x7f6), /* -0.0391 (+0.12 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) BF_PXP_CSC2_COEF5_D3(128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) BF_PXP_CSC2_COEF5_D2(128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * Rec.709 full range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * |Y | | 0.2126 0.7152 0.0722| |R| |0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * |Cb| = |-0.1146 -0.3854 0.5000| * |G| + |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * |Cr| | 0.5000 0.5000 -0.4542| |B| |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const u32 csc2_coef_rec709_full[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) BF_PXP_CSC2_COEF0_A2(0x0b7) | /* 0.7148 (-0.04 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) BF_PXP_CSC2_COEF0_A1(0x036), /* 0.2109 (-0.17 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) BF_PXP_CSC2_COEF1_B1(0x7e3) | /* -0.1133 (+0.13 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) BF_PXP_CSC2_COEF1_A3(0x012), /* 0.0703 (-0.19 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) BF_PXP_CSC2_COEF2_B2(0x79e), /* -0.3828 (+0.26 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) BF_PXP_CSC2_COEF3_C2(0x78c) | /* -0.4531 (+0.11 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) BF_PXP_CSC2_COEF4_D1(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) BF_PXP_CSC2_COEF4_C3(0x7f5), /* -0.0430 (+0.28 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) BF_PXP_CSC2_COEF5_D3(128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) BF_PXP_CSC2_COEF5_D2(128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * BT.2020 limited range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * |Y | | 0.2256 0.5823 0.0509| |R| |16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * |Cb| = |-0.1226 -0.3166 0.4392| * |G| + |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * |Cr| | 0.4392 0.4392 -0.4039| |B| |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const u32 csc2_coef_bt2020_lim[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) BF_PXP_CSC2_COEF0_A2(0x095) | /* 0.5820 (-0.03 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) BF_PXP_CSC2_COEF0_A1(0x039), /* 0.2227 (-0.30 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) BF_PXP_CSC2_COEF1_B1(0x7e1) | /* -0.1211 (+0.15 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) BF_PXP_CSC2_COEF1_A3(0x00d), /* 0.0508 (-0.01 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) BF_PXP_CSC2_COEF2_B2(0x7af), /* -0.3164 (+0.02 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) BF_PXP_CSC2_COEF3_C2(0x799) | /* -0.4023 (+0.16 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) BF_PXP_CSC2_COEF4_D1(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) BF_PXP_CSC2_COEF4_C3(0x7f7), /* -0.0352 (+0.02 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) BF_PXP_CSC2_COEF5_D3(128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) BF_PXP_CSC2_COEF5_D2(128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * BT.2020 full range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * |Y | | 0.2627 0.6780 0.0593| |R| |0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * |Cb| = |-0.1396 -0.3604 0.5000| * |G| + |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * |Cr| | 0.5000 0.5000 -0.4598| |B| |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const u32 csc2_coef_bt2020_full[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) BF_PXP_CSC2_COEF0_A2(0x0ad) | /* 0.6758 (-0.22 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) BF_PXP_CSC2_COEF0_A1(0x043), /* 0.2617 (-0.10 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) BF_PXP_CSC2_COEF1_B1(0x7dd) | /* -0.1367 (+0.29 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) BF_PXP_CSC2_COEF1_A3(0x00f), /* 0.0586 (-0.07 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) BF_PXP_CSC2_COEF2_B2(0x7a4), /* -0.3594 (+0.10 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) BF_PXP_CSC2_COEF3_C2(0x78b) | /* -0.4570 (+0.28 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) BF_PXP_CSC2_COEF4_D1(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) BF_PXP_CSC2_COEF4_C3(0x7f6), /* -0.0391 (+0.11 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) BF_PXP_CSC2_COEF5_D3(128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) BF_PXP_CSC2_COEF5_D2(128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * SMPTE 240m limited range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * |Y | | 0.1821 0.6020 0.0747| |R| |16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * |Cb| = |-0.1019 -0.3373 0.4392| * |G| + |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * |Cr| | 0.4392 0.4392 -0.3909| |B| |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const u32 csc2_coef_smpte240m_lim[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) BF_PXP_CSC2_COEF0_A2(0x09a) | /* 0.6016 (-0.05 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) BF_PXP_CSC2_COEF0_A1(0x02e), /* 0.1797 (-0.24 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) BF_PXP_CSC2_COEF1_B1(0x7e6) | /* -0.1016 (+0.03 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) BF_PXP_CSC2_COEF1_A3(0x013), /* 0.0742 (-0.05 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) BF_PXP_CSC2_COEF2_B2(0x7aa), /* -0.3359 (+0.14 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) BF_PXP_CSC2_COEF3_C2(0x79c) | /* -0.3906 (+0.03 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) BF_PXP_CSC2_COEF4_D1(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) BF_PXP_CSC2_COEF4_C3(0x7f4), /* -0.0469 (+0.14 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) BF_PXP_CSC2_COEF5_D3(128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) BF_PXP_CSC2_COEF5_D2(128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * SMPTE 240m full range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * |Y | | 0.2120 0.7010 0.0870| |R| |0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * |Cb| = |-0.1160 -0.3840 0.5000| * |G| + |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * |Cr| | 0.5000 0.5000 -0.4450| |B| |128|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static const u32 csc2_coef_smpte240m_full[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) BF_PXP_CSC2_COEF0_A2(0x0b3) | /* 0.6992 (-0.18 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) BF_PXP_CSC2_COEF0_A1(0x036), /* 0.2109 (-0.11 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) BF_PXP_CSC2_COEF1_B1(0x7e3) | /* -0.1133 (+0.27 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) BF_PXP_CSC2_COEF1_A3(0x016), /* 0.0859 (-0.11 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) BF_PXP_CSC2_COEF2_B2(0x79e), /* -0.3828 (+0.12 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) BF_PXP_CSC2_COEF3_C2(0x78f) | /* -0.4414 (+0.36 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) BF_PXP_CSC2_COEF4_D1(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) BF_PXP_CSC2_COEF4_C3(0x7f2), /* -0.0547 (+0.03 %) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) BF_PXP_CSC2_COEF5_D3(128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) BF_PXP_CSC2_COEF5_D2(128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) const u32 *csc2_coef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 csc2_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ycbcr_enc = ctx->q_data[V4L2_M2M_DST].ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) quantization = ctx->q_data[V4L2_M2M_DST].quant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) csc2_coef = csc2_coef_bt601_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) csc2_coef = csc2_coef_bt601_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) csc2_coef = csc2_coef_rec709_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) csc2_coef = csc2_coef_rec709_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } else if (ycbcr_enc == V4L2_YCBCR_ENC_BT2020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) csc2_coef = csc2_coef_bt2020_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) csc2_coef = csc2_coef_bt2020_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) csc2_coef = csc2_coef_smpte240m_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) csc2_coef = csc2_coef_smpte240m_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (quantization == V4L2_QUANTIZATION_FULL_RANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) BP_PXP_CSC2_CTRL_CSC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) BP_PXP_CSC2_CTRL_CSC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) writel(csc2_ctrl, dev->mmio + HW_PXP_CSC2_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) writel(csc2_coef[0], dev->mmio + HW_PXP_CSC2_COEF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) writel(csc2_coef[1], dev->mmio + HW_PXP_CSC2_COEF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) writel(csc2_coef[2], dev->mmio + HW_PXP_CSC2_COEF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) writel(csc2_coef[3], dev->mmio + HW_PXP_CSC2_COEF3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) writel(csc2_coef[4], dev->mmio + HW_PXP_CSC2_COEF4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) writel(csc2_coef[5], dev->mmio + HW_PXP_CSC2_COEF5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) writel(BM_PXP_CSC2_CTRL_BYPASS, dev->mmio + HW_PXP_CSC2_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int pxp_start(struct pxp_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct vb2_v4l2_buffer *out_vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct pxp_dev *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct pxp_q_data *q_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u32 src_width, src_height, src_stride, src_fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u32 dst_width, dst_height, dst_stride, dst_fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dma_addr_t p_in, p_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 ctrl, out_ctrl, out_buf, out_buf2, out_pitch, out_lrc, out_ps_ulc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u32 out_ps_lrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u32 ps_ctrl, ps_buf, ps_ubuf, ps_vbuf, ps_pitch, ps_scale, ps_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 as_ulc, as_lrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u32 y_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u32 decx, decy, xscale, yscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) src_width = ctx->q_data[V4L2_M2M_SRC].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dst_width = ctx->q_data[V4L2_M2M_DST].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) src_height = ctx->q_data[V4L2_M2M_SRC].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dst_height = ctx->q_data[V4L2_M2M_DST].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) src_stride = ctx->q_data[V4L2_M2M_SRC].bytesperline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dst_stride = ctx->q_data[V4L2_M2M_DST].bytesperline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) src_fourcc = ctx->q_data[V4L2_M2M_SRC].fmt->fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dst_fourcc = ctx->q_data[V4L2_M2M_DST].fmt->fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) p_in = vb2_dma_contig_plane_dma_addr(&in_vb->vb2_buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) p_out = vb2_dma_contig_plane_dma_addr(&out_vb->vb2_buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (!p_in || !p_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) v4l2_err(&dev->v4l2_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "Acquiring DMA addresses of buffers failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) out_vb->sequence =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE)->sequence++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) in_vb->sequence = q_data->sequence++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) out_vb->vb2_buf.timestamp = in_vb->vb2_buf.timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (in_vb->flags & V4L2_BUF_FLAG_TIMECODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) out_vb->timecode = in_vb->timecode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) out_vb->field = in_vb->field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) out_vb->flags = in_vb->flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) (V4L2_BUF_FLAG_TIMECODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) V4L2_BUF_FLAG_KEYFRAME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) V4L2_BUF_FLAG_PFRAME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) V4L2_BUF_FLAG_BFRAME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) V4L2_BUF_FLAG_TSTAMP_SRC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Rotation disabled, 8x8 block size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ctrl = BF_PXP_CTRL_VFLIP0(!!(ctx->mode & MEM2MEM_VFLIP)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) BF_PXP_CTRL_HFLIP0(!!(ctx->mode & MEM2MEM_HFLIP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Always write alpha value as V4L2_CID_ALPHA_COMPONENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) out_ctrl = BF_PXP_OUT_CTRL_ALPHA(ctx->alpha_component) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) BF_PXP_OUT_CTRL_ALPHA_OUTPUT(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pxp_v4l2_pix_fmt_to_out_format(dst_fourcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) out_buf = p_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) switch (dst_fourcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case V4L2_PIX_FMT_NV12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case V4L2_PIX_FMT_NV21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case V4L2_PIX_FMT_NV16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) case V4L2_PIX_FMT_NV61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) out_buf2 = out_buf + dst_stride * dst_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) out_buf2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) out_pitch = BF_PXP_OUT_PITCH_PITCH(dst_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) out_lrc = BF_PXP_OUT_LRC_X(dst_width - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) BF_PXP_OUT_LRC_Y(dst_height - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* PS covers whole output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) out_ps_ulc = BF_PXP_OUT_PS_ULC_X(0) | BF_PXP_OUT_PS_ULC_Y(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) out_ps_lrc = BF_PXP_OUT_PS_LRC_X(dst_width - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) BF_PXP_OUT_PS_LRC_Y(dst_height - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* no AS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) as_ulc = BF_PXP_OUT_AS_ULC_X(1) | BF_PXP_OUT_AS_ULC_Y(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) as_lrc = BF_PXP_OUT_AS_LRC_X(0) | BF_PXP_OUT_AS_LRC_Y(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) decx = (src_width <= dst_width) ? 0 : ilog2(src_width / dst_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) decy = (src_height <= dst_height) ? 0 : ilog2(src_height / dst_height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ps_ctrl = BF_PXP_PS_CTRL_DECX(decx) | BF_PXP_PS_CTRL_DECY(decy) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pxp_v4l2_pix_fmt_to_ps_format(src_fourcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ps_buf = p_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) y_size = src_stride * src_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) switch (src_fourcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case V4L2_PIX_FMT_YUV420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ps_ubuf = ps_buf + y_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ps_vbuf = ps_ubuf + y_size / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) case V4L2_PIX_FMT_YUV422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ps_ubuf = ps_buf + y_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ps_vbuf = ps_ubuf + y_size / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) case V4L2_PIX_FMT_NV12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case V4L2_PIX_FMT_NV21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) case V4L2_PIX_FMT_NV16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) case V4L2_PIX_FMT_NV61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ps_ubuf = ps_buf + y_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ps_vbuf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case V4L2_PIX_FMT_GREY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case V4L2_PIX_FMT_Y4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ps_ubuf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* In grayscale mode, ps_vbuf contents are reused as CbCr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ps_vbuf = 0x8080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ps_ubuf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ps_vbuf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ps_pitch = BF_PXP_PS_PITCH_PITCH(src_stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (decx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) xscale = (src_width >> decx) * 0x1000 / dst_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) switch (src_fourcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case V4L2_PIX_FMT_UYVY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case V4L2_PIX_FMT_YUYV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case V4L2_PIX_FMT_VYUY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case V4L2_PIX_FMT_YVYU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case V4L2_PIX_FMT_NV16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case V4L2_PIX_FMT_NV12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) case V4L2_PIX_FMT_NV21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case V4L2_PIX_FMT_NV61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) case V4L2_PIX_FMT_YUV422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case V4L2_PIX_FMT_YUV420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * This avoids sampling past the right edge for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * horizontally chroma subsampled formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) xscale = (src_width - 2) * 0x1000 / (dst_width - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) xscale = (src_width - 1) * 0x1000 / (dst_width - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (decy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) yscale = (src_height >> decy) * 0x1000 / dst_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) yscale = (src_height - 1) * 0x1000 / (dst_height - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ps_scale = BF_PXP_PS_SCALE_YSCALE(yscale) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) BF_PXP_PS_SCALE_XSCALE(xscale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ps_offset = BF_PXP_PS_OFFSET_YOFFSET(0) | BF_PXP_PS_OFFSET_XOFFSET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) writel(ctrl, dev->mmio + HW_PXP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* skip STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) writel(out_ctrl, dev->mmio + HW_PXP_OUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) writel(out_buf, dev->mmio + HW_PXP_OUT_BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) writel(out_buf2, dev->mmio + HW_PXP_OUT_BUF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) writel(out_pitch, dev->mmio + HW_PXP_OUT_PITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) writel(out_lrc, dev->mmio + HW_PXP_OUT_LRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) writel(out_ps_ulc, dev->mmio + HW_PXP_OUT_PS_ULC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) writel(out_ps_lrc, dev->mmio + HW_PXP_OUT_PS_LRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) writel(as_ulc, dev->mmio + HW_PXP_OUT_AS_ULC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) writel(as_lrc, dev->mmio + HW_PXP_OUT_AS_LRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) writel(ps_ctrl, dev->mmio + HW_PXP_PS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) writel(ps_buf, dev->mmio + HW_PXP_PS_BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) writel(ps_ubuf, dev->mmio + HW_PXP_PS_UBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) writel(ps_vbuf, dev->mmio + HW_PXP_PS_VBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) writel(ps_pitch, dev->mmio + HW_PXP_PS_PITCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) writel(0x00ffffff, dev->mmio + HW_PXP_PS_BACKGROUND_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) writel(ps_scale, dev->mmio + HW_PXP_PS_SCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) writel(ps_offset, dev->mmio + HW_PXP_PS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* disable processed surface color keying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) writel(0x00ffffff, dev->mmio + HW_PXP_PS_CLRKEYLOW_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) writel(0x00000000, dev->mmio + HW_PXP_PS_CLRKEYHIGH_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* disable alpha surface color keying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) writel(0x00ffffff, dev->mmio + HW_PXP_AS_CLRKEYLOW_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) writel(0x00000000, dev->mmio + HW_PXP_AS_CLRKEYHIGH_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* setup CSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) pxp_setup_csc(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* bypass LUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) writel(BM_PXP_LUT_CTRL_BYPASS, dev->mmio + HW_PXP_LUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) writel(BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(1)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(0)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev->mmio + HW_PXP_DATA_PATH_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) writel(BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dev->mmio + HW_PXP_DATA_PATH_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) writel(0xffff, dev->mmio + HW_PXP_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* ungate, enable PS/AS/OUT and PXP operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) writel(BM_PXP_CTRL_IRQ_ENABLE, dev->mmio + HW_PXP_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) writel(BM_PXP_CTRL_ENABLE | BM_PXP_CTRL_ENABLE_CSC2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) BM_PXP_CTRL_ENABLE_LUT | BM_PXP_CTRL_ENABLE_ROTATE0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) BM_PXP_CTRL_ENABLE_PS_AS_OUT, dev->mmio + HW_PXP_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static void pxp_job_finish(struct pxp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct pxp_ctx *curr_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct vb2_v4l2_buffer *src_vb, *dst_vb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) curr_ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (curr_ctx == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) pr_err("Instance released before the end of transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) spin_lock_irqsave(&dev->irqlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) spin_unlock_irqrestore(&dev->irqlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dprintk(curr_ctx->dev, "Finishing transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) v4l2_m2m_job_finish(dev->m2m_dev, curr_ctx->fh.m2m_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * mem2mem callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static void pxp_device_run(void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct pxp_ctx *ctx = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct vb2_v4l2_buffer *src_buf, *dst_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) pxp_start(ctx, src_buf, dst_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static int pxp_job_ready(void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct pxp_ctx *ctx = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dprintk(ctx->dev, "Not enough buffers available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static void pxp_job_abort(void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct pxp_ctx *ctx = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* Will cancel the transaction in the next interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ctx->aborting = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static irqreturn_t pxp_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct pxp_dev *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) stat = readl(dev->mmio + HW_PXP_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (stat & BM_PXP_STAT_IRQ0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* we expect x = 0, y = height, irq0 = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (stat & ~(BM_PXP_STAT_BLOCKX | BM_PXP_STAT_BLOCKY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) BM_PXP_STAT_IRQ0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) writel(BM_PXP_STAT_IRQ0, dev->mmio + HW_PXP_STAT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) pxp_job_finish(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 irq = readl(dev->mmio + HW_PXP_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dprintk(dev, "%s: irq = 0x%08x\n", __func__, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) writel(irq, dev->mmio + HW_PXP_IRQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * video ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static int pxp_querycap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct v4l2_capability *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) strscpy(cap->driver, MEM2MEM_NAME, sizeof(cap->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) strscpy(cap->card, MEM2MEM_NAME, sizeof(cap->card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) snprintf(cap->bus_info, sizeof(cap->bus_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) "platform:%s", MEM2MEM_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static int pxp_enum_fmt(struct v4l2_fmtdesc *f, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int i, num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct pxp_fmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) for (i = 0; i < NUM_FORMATS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (formats[i].types & type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* index-th format of type type found ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (num == f->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * Correct type but haven't reached our index yet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * just increment per-type index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ++num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (i < NUM_FORMATS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Format found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) fmt = &formats[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) f->pixelformat = fmt->fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* Format not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static int pxp_enum_fmt_vid_cap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct v4l2_fmtdesc *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return pxp_enum_fmt(f, MEM2MEM_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static int pxp_enum_fmt_vid_out(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct v4l2_fmtdesc *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return pxp_enum_fmt(f, MEM2MEM_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static int pxp_g_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct vb2_queue *vq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct pxp_q_data *q_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (!vq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) q_data = get_q_data(ctx, f->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) f->fmt.pix.width = q_data->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) f->fmt.pix.height = q_data->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) f->fmt.pix.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) f->fmt.pix.pixelformat = q_data->fmt->fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) f->fmt.pix.bytesperline = q_data->bytesperline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) f->fmt.pix.sizeimage = q_data->sizeimage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) f->fmt.pix.colorspace = ctx->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) f->fmt.pix.xfer_func = ctx->xfer_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) f->fmt.pix.ycbcr_enc = q_data->ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) f->fmt.pix.quantization = q_data->quant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static int pxp_g_fmt_vid_out(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return pxp_g_fmt(file2ctx(file), f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static int pxp_g_fmt_vid_cap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return pxp_g_fmt(file2ctx(file), f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static inline u32 pxp_bytesperline(struct pxp_fmt *fmt, u32 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) switch (fmt->fourcc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) case V4L2_PIX_FMT_YUV420:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) case V4L2_PIX_FMT_NV12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) case V4L2_PIX_FMT_NV21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) case V4L2_PIX_FMT_YUV422P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) case V4L2_PIX_FMT_NV16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) case V4L2_PIX_FMT_NV61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return (width * fmt->depth) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static inline u32 pxp_sizeimage(struct pxp_fmt *fmt, u32 width, u32 height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return (fmt->depth * width * height) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static int pxp_try_fmt(struct v4l2_format *f, struct pxp_fmt *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W, ALIGN_W,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) &f->fmt.pix.height, MIN_H, MAX_H, ALIGN_H, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) f->fmt.pix.bytesperline = pxp_bytesperline(fmt, f->fmt.pix.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) f->fmt.pix.sizeimage = pxp_sizeimage(fmt, f->fmt.pix.width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) f->fmt.pix.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) f->fmt.pix.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) pxp_fixup_colorimetry_cap(struct pxp_ctx *ctx, u32 dst_fourcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) enum v4l2_ycbcr_encoding *ycbcr_enc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) enum v4l2_quantization *quantization)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) bool dst_is_yuv = pxp_v4l2_pix_fmt_is_yuv(dst_fourcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dst_is_yuv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * There is no support for conversion between different YCbCr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * encodings or between RGB limited and full range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) *ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) *quantization = ctx->q_data[V4L2_M2M_SRC].quant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) *ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(ctx->colorspace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) *quantization = V4L2_MAP_QUANTIZATION_DEFAULT(!dst_is_yuv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ctx->colorspace,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) *ycbcr_enc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int pxp_try_fmt_vid_cap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct pxp_fmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct pxp_ctx *ctx = file2ctx(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) fmt = find_format(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (!fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) f->fmt.pix.pixelformat = formats[0].fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) fmt = find_format(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (!(fmt->types & MEM2MEM_CAPTURE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) v4l2_err(&ctx->dev->v4l2_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) "Fourcc format (0x%08x) invalid.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) f->fmt.pix.pixelformat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) f->fmt.pix.colorspace = ctx->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) f->fmt.pix.xfer_func = ctx->xfer_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pxp_fixup_colorimetry_cap(ctx, fmt->fourcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) &f->fmt.pix.ycbcr_enc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) &f->fmt.pix.quantization);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return pxp_try_fmt(f, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static int pxp_try_fmt_vid_out(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct pxp_fmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct pxp_ctx *ctx = file2ctx(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) fmt = find_format(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (!fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) f->fmt.pix.pixelformat = formats[0].fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) fmt = find_format(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (!(fmt->types & MEM2MEM_OUTPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) v4l2_err(&ctx->dev->v4l2_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) "Fourcc format (0x%08x) invalid.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) f->fmt.pix.pixelformat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (!f->fmt.pix.colorspace)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return pxp_try_fmt(f, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static int pxp_s_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct pxp_q_data *q_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct vb2_queue *vq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (!vq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) q_data = get_q_data(ctx, f->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (!q_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (vb2_is_busy(vq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) q_data->fmt = find_format(f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) q_data->width = f->fmt.pix.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) q_data->height = f->fmt.pix.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) q_data->bytesperline = f->fmt.pix.bytesperline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) q_data->sizeimage = f->fmt.pix.sizeimage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dprintk(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static int pxp_s_fmt_vid_cap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct pxp_ctx *ctx = file2ctx(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ret = pxp_try_fmt_vid_cap(file, priv, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ret = pxp_s_fmt(file2ctx(file), f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ctx->q_data[V4L2_M2M_DST].ycbcr_enc = f->fmt.pix.ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ctx->q_data[V4L2_M2M_DST].quant = f->fmt.pix.quantization;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static int pxp_s_fmt_vid_out(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct pxp_ctx *ctx = file2ctx(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ret = pxp_try_fmt_vid_out(file, priv, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ret = pxp_s_fmt(file2ctx(file), f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ctx->colorspace = f->fmt.pix.colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ctx->xfer_func = f->fmt.pix.xfer_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ctx->q_data[V4L2_M2M_SRC].ycbcr_enc = f->fmt.pix.ycbcr_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ctx->q_data[V4L2_M2M_SRC].quant = f->fmt.pix.quantization;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) pxp_fixup_colorimetry_cap(ctx, ctx->q_data[V4L2_M2M_DST].fmt->fourcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) &ctx->q_data[V4L2_M2M_DST].ycbcr_enc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) &ctx->q_data[V4L2_M2M_DST].quant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static int pxp_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct pxp_ctx *ctx =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) container_of(ctrl->handler, struct pxp_ctx, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) ctx->mode |= MEM2MEM_HFLIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ctx->mode &= ~MEM2MEM_HFLIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ctx->mode |= MEM2MEM_VFLIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ctx->mode &= ~MEM2MEM_VFLIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) case V4L2_CID_ALPHA_COMPONENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ctx->alpha_component = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) v4l2_err(&ctx->dev->v4l2_dev, "Invalid control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static const struct v4l2_ctrl_ops pxp_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .s_ctrl = pxp_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static const struct v4l2_ioctl_ops pxp_ioctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .vidioc_querycap = pxp_querycap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .vidioc_enum_fmt_vid_cap = pxp_enum_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .vidioc_g_fmt_vid_cap = pxp_g_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .vidioc_try_fmt_vid_cap = pxp_try_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .vidioc_s_fmt_vid_cap = pxp_s_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .vidioc_enum_fmt_vid_out = pxp_enum_fmt_vid_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .vidioc_g_fmt_vid_out = pxp_g_fmt_vid_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .vidioc_try_fmt_vid_out = pxp_try_fmt_vid_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .vidioc_s_fmt_vid_out = pxp_s_fmt_vid_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .vidioc_streamon = v4l2_m2m_ioctl_streamon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * Queue operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static int pxp_queue_setup(struct vb2_queue *vq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) unsigned int *nbuffers, unsigned int *nplanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) unsigned int sizes[], struct device *alloc_devs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct pxp_ctx *ctx = vb2_get_drv_priv(vq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct pxp_q_data *q_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) unsigned int size, count = *nbuffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) q_data = get_q_data(ctx, vq->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) size = q_data->sizeimage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) *nbuffers = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (*nplanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return sizes[0] < size ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) *nplanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) sizes[0] = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) dprintk(ctx->dev, "get %d buffer(s) of size %d each.\n", count, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static int pxp_buf_prepare(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct pxp_dev *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct pxp_q_data *q_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) q_data = get_q_data(ctx, vb->vb2_queue->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (vbuf->field == V4L2_FIELD_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) vbuf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (vbuf->field != V4L2_FIELD_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dprintk(dev, "%s field isn't supported\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) dprintk(dev, "%s data will not fit into plane (%lu < %lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) __func__, vb2_plane_size(vb, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) (long)q_data->sizeimage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) vb2_set_plane_payload(vb, 0, q_data->sizeimage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static void pxp_buf_queue(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int pxp_start_streaming(struct vb2_queue *q, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct pxp_ctx *ctx = vb2_get_drv_priv(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct pxp_q_data *q_data = get_q_data(ctx, q->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) q_data->sequence = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static void pxp_stop_streaming(struct vb2_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct pxp_ctx *ctx = vb2_get_drv_priv(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct vb2_v4l2_buffer *vbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (V4L2_TYPE_IS_OUTPUT(q->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (vbuf == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) spin_lock_irqsave(&ctx->dev->irqlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) spin_unlock_irqrestore(&ctx->dev->irqlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static const struct vb2_ops pxp_qops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .queue_setup = pxp_queue_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .buf_prepare = pxp_buf_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .buf_queue = pxp_buf_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .start_streaming = pxp_start_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .stop_streaming = pxp_stop_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .wait_prepare = vb2_ops_wait_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .wait_finish = vb2_ops_wait_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static int queue_init(void *priv, struct vb2_queue *src_vq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) struct vb2_queue *dst_vq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct pxp_ctx *ctx = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) src_vq->drv_priv = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) src_vq->ops = &pxp_qops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) src_vq->mem_ops = &vb2_dma_contig_memops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) src_vq->lock = &ctx->dev->dev_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) src_vq->dev = ctx->dev->v4l2_dev.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) ret = vb2_queue_init(src_vq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) dst_vq->drv_priv = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) dst_vq->ops = &pxp_qops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dst_vq->mem_ops = &vb2_dma_contig_memops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) dst_vq->lock = &ctx->dev->dev_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) dst_vq->dev = ctx->dev->v4l2_dev.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return vb2_queue_init(dst_vq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * File operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static int pxp_open(struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct pxp_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct pxp_ctx *ctx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct v4l2_ctrl_handler *hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (mutex_lock_interruptible(&dev->dev_mutex))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (!ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) goto open_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) v4l2_fh_init(&ctx->fh, video_devdata(file));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) file->private_data = &ctx->fh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) hdl = &ctx->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) v4l2_ctrl_handler_init(hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_ALPHA_COMPONENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) 0, 255, 1, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) rc = hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) goto open_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ctx->fh.ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) v4l2_ctrl_handler_setup(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) ctx->q_data[V4L2_M2M_SRC].fmt = &formats[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ctx->q_data[V4L2_M2M_SRC].width = 640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ctx->q_data[V4L2_M2M_SRC].height = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ctx->q_data[V4L2_M2M_SRC].bytesperline =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) pxp_bytesperline(&formats[0], 640);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ctx->q_data[V4L2_M2M_SRC].sizeimage =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) pxp_sizeimage(&formats[0], 640, 480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ctx->q_data[V4L2_M2M_DST] = ctx->q_data[V4L2_M2M_SRC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) ctx->colorspace = V4L2_COLORSPACE_REC709;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (IS_ERR(ctx->fh.m2m_ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) rc = PTR_ERR(ctx->fh.m2m_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) v4l2_fh_exit(&ctx->fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) goto open_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) v4l2_fh_add(&ctx->fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) atomic_inc(&dev->num_inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) dprintk(dev, "Created instance: %p, m2m_ctx: %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ctx, ctx->fh.m2m_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) open_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) mutex_unlock(&dev->dev_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static int pxp_release(struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) struct pxp_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) struct pxp_ctx *ctx = file2ctx(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) dprintk(dev, "Releasing instance %p\n", ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) v4l2_fh_del(&ctx->fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) v4l2_fh_exit(&ctx->fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) v4l2_ctrl_handler_free(&ctx->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) mutex_lock(&dev->dev_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) mutex_unlock(&dev->dev_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) kfree(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) atomic_dec(&dev->num_inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static const struct v4l2_file_operations pxp_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .open = pxp_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .release = pxp_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .poll = v4l2_m2m_fop_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .unlocked_ioctl = video_ioctl2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .mmap = v4l2_m2m_fop_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static const struct video_device pxp_videodev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .name = MEM2MEM_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .vfl_dir = VFL_DIR_M2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .fops = &pxp_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .ioctl_ops = &pxp_ioctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .minor = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .release = video_device_release_empty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static const struct v4l2_m2m_ops m2m_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .device_run = pxp_device_run,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .job_ready = pxp_job_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .job_abort = pxp_job_abort,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static int pxp_soft_reset(struct pxp_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) ret = readl_poll_timeout(dev->mmio + HW_PXP_CTRL, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) val & BM_PXP_CTRL_CLKGATE, 0, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static int pxp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct pxp_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) struct video_device *vfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) dev->clk = devm_clk_get(&pdev->dev, "axi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (IS_ERR(dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ret = PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) dev_err(&pdev->dev, "Failed to get clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) dev->mmio = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (IS_ERR(dev->mmio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) ret = PTR_ERR(dev->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) dev_err(&pdev->dev, "Failed to map register space: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) spin_lock_init(&dev->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, pxp_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) IRQF_ONESHOT, dev_name(&pdev->dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) ret = clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ret = pxp_soft_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) dev_err(&pdev->dev, "PXP reset timeout: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) atomic_set(&dev->num_inst, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) mutex_init(&dev->dev_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) dev->vfd = pxp_videodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) vfd = &dev->vfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) vfd->lock = &dev->dev_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) vfd->v4l2_dev = &dev->v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) video_set_drvdata(vfd, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) snprintf(vfd->name, sizeof(vfd->name), "%s", pxp_videodev.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) v4l2_info(&dev->v4l2_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) "Device registered as /dev/video%d\n", vfd->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (IS_ERR(dev->m2m_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ret = PTR_ERR(dev->m2m_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) goto err_v4l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) goto err_m2m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) err_m2m:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) v4l2_m2m_release(dev->m2m_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) err_v4l2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) v4l2_device_unregister(&dev->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) clk_disable_unprepare(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static int pxp_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) struct pxp_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) clk_disable_unprepare(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) v4l2_info(&dev->v4l2_dev, "Removing " MEM2MEM_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) video_unregister_device(&dev->vfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) v4l2_m2m_release(dev->m2m_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) v4l2_device_unregister(&dev->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static const struct of_device_id pxp_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) { .compatible = "fsl,imx6ull-pxp", .data = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) MODULE_DEVICE_TABLE(of, pxp_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static struct platform_driver pxp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .probe = pxp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .remove = pxp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .name = MEM2MEM_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .of_match_table = of_match_ptr(pxp_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) module_platform_driver(pxp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) MODULE_DESCRIPTION("i.MX PXP mem2mem scaler/CSC/rotator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) MODULE_AUTHOR("Philipp Zabel <kernel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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