^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * budget-av.c: driver for the SAA7146 based Budget DVB cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * with analog video in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Compiled from various sources by Michael Hunold <michael@mihu.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * CI interface support (c) 2004 Olivier Gournet <ogournet@anevia.com> &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Andrew de Quincey <adq_dvb@lidskialf.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2002 Ralph Metzler <rjkm@metzlerbros.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 1999-2002 Ralph Metzler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * & Marcus Metzler for convergence integrated media GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * the project's page is at https://linuxtv.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "budget.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "stv0299.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "stb0899_drv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "stb0899_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "stb0899_cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "tda8261.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "tda8261_cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "tda1002x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "tda1004x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "tua6100.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "dvb-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/drv-intf/saa7146_vv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <media/dvb_ca_en50221.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DEBICICAM 0x02420000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SLOTSTATUS_NONE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SLOTSTATUS_PRESENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SLOTSTATUS_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SLOTSTATUS_READY 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SLOTSTATUS_OCCUPIED (SLOTSTATUS_PRESENT|SLOTSTATUS_RESET|SLOTSTATUS_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct budget_av {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct budget budget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct video_device vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int cur_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int has_saa7113;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct tasklet_struct ciintf_irq_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int slot_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct dvb_ca_en50221 ca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 reinitialise_demod:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int ciintf_slot_shutdown(struct dvb_ca_en50221 *ca, int slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* GPIO Connections:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 0 - Vcc/Reset (Reset is controlled by capacitor). Resets the frontend *AS WELL*!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 1 - CI memory select 0=>IO memory, 1=>Attribute Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 2 - CI Card Enable (Active Low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 3 - CI Card Detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * INITIALIZATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static u8 i2c_readreg(struct i2c_adapter *i2c, u8 id, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 mm1[] = { 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 mm2[] = { 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) msgs[0].addr = msgs[1].addr = id / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mm1[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) msgs[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) msgs[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) msgs[0].buf = mm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) msgs[1].buf = mm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) i2c_transfer(i2c, msgs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return mm2[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int i2c_readregs(struct i2c_adapter *i2c, u8 id, u8 reg, u8 * buf, u8 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 mm1[] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct i2c_msg msgs[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {.addr = id / 2,.flags = 0,.buf = mm1,.len = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {.addr = id / 2,.flags = I2C_M_RD,.buf = buf,.len = len}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (i2c_transfer(i2c, msgs, 2) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int i2c_writereg(struct i2c_adapter *i2c, u8 id, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 msg[2] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct i2c_msg msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) msgs.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) msgs.addr = id / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) msgs.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) msgs.buf = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return i2c_transfer(i2c, &msgs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int ciintf_read_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct budget_av *budget_av = (struct budget_av *) ca->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) saa7146_setgpio(budget_av->budget.dev, 1, SAA7146_GPIO_OUTHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) result = ttpci_budget_debiread(&budget_av->budget, DEBICICAM, address & 0xfff, 1, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (result == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ciintf_slot_shutdown(ca, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pr_info("cam ejected 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int ciintf_write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct budget_av *budget_av = (struct budget_av *) ca->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) saa7146_setgpio(budget_av->budget.dev, 1, SAA7146_GPIO_OUTHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) result = ttpci_budget_debiwrite(&budget_av->budget, DEBICICAM, address & 0xfff, 1, value, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (result == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ciintf_slot_shutdown(ca, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pr_info("cam ejected 2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int ciintf_read_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct budget_av *budget_av = (struct budget_av *) ca->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) saa7146_setgpio(budget_av->budget.dev, 1, SAA7146_GPIO_OUTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) result = ttpci_budget_debiread(&budget_av->budget, DEBICICAM, address & 3, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (result == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ciintf_slot_shutdown(ca, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pr_info("cam ejected 3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int ciintf_write_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct budget_av *budget_av = (struct budget_av *) ca->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) saa7146_setgpio(budget_av->budget.dev, 1, SAA7146_GPIO_OUTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) result = ttpci_budget_debiwrite(&budget_av->budget, DEBICICAM, address & 3, 1, value, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (result == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ciintf_slot_shutdown(ca, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pr_info("cam ejected 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int ciintf_slot_reset(struct dvb_ca_en50221 *ca, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct budget_av *budget_av = (struct budget_av *) ca->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct saa7146_dev *saa = budget_av->budget.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dprintk(1, "ciintf_slot_reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) budget_av->slot_status = SLOTSTATUS_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) saa7146_setgpio(saa, 2, SAA7146_GPIO_OUTHI); /* disable card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) saa7146_setgpio(saa, 0, SAA7146_GPIO_OUTHI); /* Vcc off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) msleep(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) saa7146_setgpio(saa, 0, SAA7146_GPIO_OUTLO); /* Vcc on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) msleep(20); /* 20 ms Vcc settling time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) saa7146_setgpio(saa, 2, SAA7146_GPIO_OUTLO); /* enable card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* reinitialise the frontend if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (budget_av->reinitialise_demod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dvb_frontend_reinitialise(budget_av->budget.dvb_frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int ciintf_slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct budget_av *budget_av = (struct budget_av *) ca->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct saa7146_dev *saa = budget_av->budget.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dprintk(1, "ciintf_slot_shutdown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) budget_av->slot_status = SLOTSTATUS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int ciintf_slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct budget_av *budget_av = (struct budget_av *) ca->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct saa7146_dev *saa = budget_av->budget.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dprintk(1, "ciintf_slot_ts_enable: %d\n", budget_av->slot_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int ciintf_poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct budget_av *budget_av = (struct budget_av *) ca->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct saa7146_dev *saa = budget_av->budget.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (slot != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* test the card detect line - needs to be done carefully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * since it never goes high for some CAMs on this interface (e.g. topuptv) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (budget_av->slot_status == SLOTSTATUS_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) saa7146_setgpio(saa, 3, SAA7146_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (saa7146_read(saa, PSR) & MASK_06) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (budget_av->slot_status == SLOTSTATUS_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) budget_av->slot_status = SLOTSTATUS_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pr_info("cam inserted A\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* We also try and read from IO memory to work round the above detection bug. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * there is no CAM, we will get a timeout. Only done if there is no cam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * present, since this test actually breaks some cams :(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * if the CI interface is not open, we also do the above test since we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * don't care if the cam has problems - we'll be resetting it on open() anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if ((budget_av->slot_status == SLOTSTATUS_NONE) || (!open)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) saa7146_setgpio(budget_av->budget.dev, 1, SAA7146_GPIO_OUTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) result = ttpci_budget_debiread(&budget_av->budget, DEBICICAM, 0, 1, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if ((result >= 0) && (budget_av->slot_status == SLOTSTATUS_NONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) budget_av->slot_status = SLOTSTATUS_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pr_info("cam inserted B\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (budget_av->slot_status != SLOTSTATUS_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ciintf_slot_shutdown(ca, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pr_info("cam ejected 5\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* read from attribute memory in reset/ready state to know when the CAM is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (budget_av->slot_status == SLOTSTATUS_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) result = ciintf_read_attribute_mem(ca, slot, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (result == 0x1d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) budget_av->slot_status = SLOTSTATUS_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* work out correct return code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (budget_av->slot_status != SLOTSTATUS_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (budget_av->slot_status & SLOTSTATUS_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return DVB_CA_EN50221_POLL_CAM_PRESENT | DVB_CA_EN50221_POLL_CAM_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return DVB_CA_EN50221_POLL_CAM_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int ciintf_init(struct budget_av *budget_av)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct saa7146_dev *saa = budget_av->budget.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) memset(&budget_av->ca, 0, sizeof(struct dvb_ca_en50221));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) saa7146_setgpio(saa, 0, SAA7146_GPIO_OUTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) saa7146_setgpio(saa, 2, SAA7146_GPIO_OUTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Enable DEBI pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) saa7146_write(saa, MC1, MASK_27 | MASK_11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* register CI interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) budget_av->ca.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) budget_av->ca.read_attribute_mem = ciintf_read_attribute_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) budget_av->ca.write_attribute_mem = ciintf_write_attribute_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) budget_av->ca.read_cam_control = ciintf_read_cam_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) budget_av->ca.write_cam_control = ciintf_write_cam_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) budget_av->ca.slot_reset = ciintf_slot_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) budget_av->ca.slot_shutdown = ciintf_slot_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) budget_av->ca.slot_ts_enable = ciintf_slot_ts_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) budget_av->ca.poll_slot_status = ciintf_poll_slot_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) budget_av->ca.data = budget_av;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) budget_av->budget.ci_present = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) budget_av->slot_status = SLOTSTATUS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if ((result = dvb_ca_en50221_init(&budget_av->budget.dvb_adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) &budget_av->ca, 0, 1)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pr_err("ci initialisation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pr_info("ci interface initialised\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) saa7146_write(saa, MC1, MASK_27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void ciintf_deinit(struct budget_av *budget_av)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct saa7146_dev *saa = budget_av->budget.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) saa7146_setgpio(saa, 0, SAA7146_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) saa7146_setgpio(saa, 1, SAA7146_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) saa7146_setgpio(saa, 2, SAA7146_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) saa7146_setgpio(saa, 3, SAA7146_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* release the CA device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dvb_ca_en50221_release(&budget_av->ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* disable DEBI pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) saa7146_write(saa, MC1, MASK_27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const u8 saa7113_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x01, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0x02, 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x03, 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0x04, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x05, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x06, 0xeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0x07, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0x08, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x09, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 0x0a, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0x0b, 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0x0c, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0x0d, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 0x0e, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x0f, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x10, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x11, 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0x12, 0x7b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0x13, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x15, 0x00, 0x16, 0x00, 0x17, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0x57, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 0x40, 0x82, 0x58, 0x00, 0x59, 0x54, 0x5a, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x5b, 0x83, 0x5e, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int saa7113_init(struct budget_av *budget_av)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct budget *budget = &budget_av->budget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct saa7146_dev *saa = budget->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) const u8 *data = saa7113_tab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) saa7146_setgpio(saa, 0, SAA7146_GPIO_OUTHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (i2c_writereg(&budget->i2c_adap, 0x4a, 0x01, 0x08) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dprintk(1, "saa7113 not found on KNC card\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dprintk(1, "saa7113 detected and initializing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) while (*data != 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) i2c_writereg(&budget->i2c_adap, 0x4a, *data, *(data + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) data += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dprintk(1, "saa7113 status=%02x\n", i2c_readreg(&budget->i2c_adap, 0x4a, 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int saa7113_setinput(struct budget_av *budget_av, int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct budget *budget = &budget_av->budget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (1 != budget_av->has_saa7113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (input == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) i2c_writereg(&budget->i2c_adap, 0x4a, 0x02, 0xc7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) i2c_writereg(&budget->i2c_adap, 0x4a, 0x09, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) } else if (input == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) i2c_writereg(&budget->i2c_adap, 0x4a, 0x02, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) i2c_writereg(&budget->i2c_adap, 0x4a, 0x09, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) budget_av->cur_input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int philips_su1278_ty_ci_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u8 aclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u8 bclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 m1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) aclk = 0xb5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (srate < 2000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) bclk = 0x86;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) else if (srate < 5000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bclk = 0x89;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) else if (srate < 15000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) bclk = 0x8f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) else if (srate < 45000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) bclk = 0x95;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) m1 = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (srate < 4000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) m1 = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) stv0299_writereg(fe, 0x13, aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) stv0299_writereg(fe, 0x14, bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) stv0299_writereg(fe, 0x0f, 0x80 | m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int philips_su1278_ty_ci_tuner_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct budget *budget = (struct budget *) fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct i2c_msg msg = {.addr = 0x61,.flags = 0,.buf = buf,.len = sizeof(buf) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if ((c->frequency < 950000) || (c->frequency > 2150000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) div = (c->frequency + (125 - 1)) / 125; /* round correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) buf[0] = (div >> 8) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) buf[1] = div & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) buf[3] = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (c->symbol_rate < 4000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) buf[3] |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (c->frequency < 1250000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) buf[3] |= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) else if (c->frequency < 1550000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) buf[3] |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) else if (c->frequency < 2050000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) buf[3] |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) else if (c->frequency < 2150000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) buf[3] |= 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (i2c_transfer(&budget->i2c_adap, &msg, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static u8 typhoon_cinergy1200s_inittab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 0x01, 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0x02, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 0x03, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0x06, 0x40, /* DAC not used, set to high impendance mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0x07, 0x00, /* DAC LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 0x08, 0x40, /* DiSEqC off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 0x09, 0x00, /* FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 0x10, 0x3f, // AGC2 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x11, 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 0x12, 0xb9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0x15, 0xc9, // lock detector threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 0x16, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x17, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0x18, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0x19, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0x1a, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0x1f, 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0x20, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0x21, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 0x22, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 0x23, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 0x28, 0x00, // out imp: normal out type: parallel FEC mode:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0x29, 0x1e, // 1/2 threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0x2a, 0x14, // 2/3 threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 0x2b, 0x0f, // 3/4 threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 0x2c, 0x09, // 5/6 threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 0x2d, 0x05, // 7/8 threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0x2e, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 0x31, 0x1f, // test all FECs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 0x32, 0x19, // viterbi and synchro search
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0x33, 0xfc, // rs control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0x34, 0x93, // error control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 0x0f, 0x92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 0xff, 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const struct stv0299_config typhoon_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .demod_address = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .inittab = typhoon_cinergy1200s_inittab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .mclk = 88000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .invert = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .skip_reinit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .lock_output = STV0299_LOCKOUTPUT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .volt13_op0_op1 = STV0299_VOLT13_OP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .min_delay_ms = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .set_symbol_rate = philips_su1278_ty_ci_set_symbol_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const struct stv0299_config cinergy_1200s_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .demod_address = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .inittab = typhoon_cinergy1200s_inittab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .mclk = 88000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .invert = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .skip_reinit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .lock_output = STV0299_LOCKOUTPUT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .volt13_op0_op1 = STV0299_VOLT13_OP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .min_delay_ms = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .set_symbol_rate = philips_su1278_ty_ci_set_symbol_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const struct stv0299_config cinergy_1200s_1894_0010_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .demod_address = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .inittab = typhoon_cinergy1200s_inittab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .mclk = 88000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .invert = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .skip_reinit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .lock_output = STV0299_LOCKOUTPUT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .volt13_op0_op1 = STV0299_VOLT13_OP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .min_delay_ms = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .set_symbol_rate = philips_su1278_ty_ci_set_symbol_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int philips_cu1216_tuner_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct budget *budget = (struct budget *) fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct i2c_msg msg = {.addr = 0x60,.flags = 0,.buf = buf,.len = sizeof(buf) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define CU1216_IF 36125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define TUNER_MUL 62500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u32 div = (c->frequency + CU1216_IF + TUNER_MUL / 2) / TUNER_MUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) buf[0] = (div >> 8) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) buf[1] = div & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) buf[2] = 0xce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) buf[3] = (c->frequency < 150000000 ? 0x01 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) c->frequency < 445000000 ? 0x02 : 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) buf[4] = 0xde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) buf[5] = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (i2c_transfer(&budget->i2c_adap, &msg, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* wait for the pll lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) msg.flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) msg.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) for (i = 0; i < 20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (i2c_transfer(&budget->i2c_adap, &msg, 1) == 1 && (buf[0] & 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* switch the charge pump to the lower current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) msg.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) msg.buf = &buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) buf[2] &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (i2c_transfer(&budget->i2c_adap, &msg, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct tda1002x_config philips_cu1216_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .demod_address = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .invert = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static struct tda1002x_config philips_cu1216_config_altaddress = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .demod_address = 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .invert = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static struct tda10023_config philips_cu1216_tda10023_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .demod_address = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .invert = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int philips_tu1216_tuner_init(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct budget *budget = (struct budget *) fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) // setup PLL configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (i2c_transfer(&budget->i2c_adap, &tuner_msg, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int philips_tu1216_tuner_set_params(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct dtv_frontend_properties *c = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct budget *budget = (struct budget *) fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 tuner_buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tuner_buf,.len =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) sizeof(tuner_buf) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int tuner_frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u8 band, cp, filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) // determine charge pump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) tuner_frequency = c->frequency + 36166000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (tuner_frequency < 87000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) else if (tuner_frequency < 130000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) cp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) else if (tuner_frequency < 160000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) cp = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) else if (tuner_frequency < 200000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) cp = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) else if (tuner_frequency < 290000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) cp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) else if (tuner_frequency < 420000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) cp = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) else if (tuner_frequency < 480000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) cp = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) else if (tuner_frequency < 620000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) cp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) else if (tuner_frequency < 830000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) cp = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) else if (tuner_frequency < 895000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) cp = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) // determine band
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (c->frequency < 49000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) else if (c->frequency < 161000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) band = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) else if (c->frequency < 444000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) band = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) else if (c->frequency < 861000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) band = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) // setup PLL filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) switch (c->bandwidth_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case 6000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) filter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case 7000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) filter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case 8000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) filter = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) // calculate divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) // ((36166000+((1000000/6)/2)) + Finput)/(1000000/6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) tuner_frequency = (((c->frequency / 1000) * 6) + 217496) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) // setup tuner buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) tuner_buf[0] = (tuner_frequency >> 8) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) tuner_buf[1] = tuner_frequency & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) tuner_buf[2] = 0xca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) tuner_buf[3] = (cp << 5) | (filter << 3) | band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (fe->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) fe->ops.i2c_gate_ctrl(fe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (i2c_transfer(&budget->i2c_adap, &tuner_msg, 1) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static int philips_tu1216_request_firmware(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) const struct firmware **fw, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct budget *budget = (struct budget *) fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return request_firmware(fw, name, &budget->dev->pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static struct tda1004x_config philips_tu1216_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .demod_address = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .invert = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .invert_oclk = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .xtal_freq = TDA10046_XTAL_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .agc_config = TDA10046_AGC_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .if_freq = TDA10046_FREQ_3617,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .request_firmware = philips_tu1216_request_firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static u8 philips_sd1878_inittab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 0x01, 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 0x02, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 0x03, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 0x04, 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 0x05, 0x35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 0x06, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 0x07, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 0x08, 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 0x09, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 0x0C, 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 0x0D, 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 0x0E, 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 0x10, 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 0x11, 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 0x12, 0xb9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 0x15, 0xc9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 0x16, 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 0x17, 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 0x18, 0x59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 0x19, 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 0x1a, 0xfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 0x1c, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 0x1d, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 0x1e, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 0x1f, 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 0x20, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 0x21, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 0x22, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) 0x23, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) 0x28, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 0x29, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 0x2a, 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 0x2b, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 0x2c, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) 0x2d, 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 0x31, 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 0x32, 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 0x33, 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 0x34, 0x93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 0xff, 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int philips_sd1878_ci_set_symbol_rate(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 srate, u32 ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u8 aclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u8 bclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u8 m1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) aclk = 0xb5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (srate < 2000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) bclk = 0x86;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) else if (srate < 5000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) bclk = 0x89;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) else if (srate < 15000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) bclk = 0x8f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) else if (srate < 45000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) bclk = 0x95;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) m1 = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (srate < 4000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) m1 = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) stv0299_writereg(fe, 0x0e, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) stv0299_writereg(fe, 0x0f, 0x94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) stv0299_writereg(fe, 0x10, 0x39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) stv0299_writereg(fe, 0x13, aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) stv0299_writereg(fe, 0x14, bclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) stv0299_writereg(fe, 0x15, 0xc9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) stv0299_writereg(fe, 0x0f, 0x80 | m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static const struct stv0299_config philips_sd1878_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .demod_address = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .inittab = philips_sd1878_inittab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .mclk = 88000000UL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .invert = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .skip_reinit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .lock_output = STV0299_LOCKOUTPUT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .volt13_op0_op1 = STV0299_VOLT13_OP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .min_delay_ms = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .set_symbol_rate = philips_sd1878_ci_set_symbol_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* KNC1 DVB-S (STB0899) Inittab */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const struct stb0899_s1_reg knc1_stb0899_s1_init_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) { STB0899_DEV_ID , 0x81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) { STB0899_DISCNTRL1 , 0x32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) { STB0899_DISCNTRL2 , 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) { STB0899_DISRX_ST0 , 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) { STB0899_DISRX_ST1 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) { STB0899_DISPARITY , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) { STB0899_DISSTATUS , 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) { STB0899_DISF22 , 0x8c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) { STB0899_DISF22RX , 0x9a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) { STB0899_SYSREG , 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) { STB0899_ACRPRESC , 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) { STB0899_ACRDIV1 , 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) { STB0899_ACRDIV2 , 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) { STB0899_DACR1 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) { STB0899_DACR2 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) { STB0899_OUTCFG , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) { STB0899_MODECFG , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) { STB0899_IRQSTATUS_3 , 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) { STB0899_IRQSTATUS_2 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) { STB0899_IRQSTATUS_1 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) { STB0899_IRQSTATUS_0 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) { STB0899_IRQMSK_3 , 0xf3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) { STB0899_IRQMSK_2 , 0xfc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) { STB0899_IRQMSK_1 , 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) { STB0899_IRQMSK_0 , 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) { STB0899_IRQCFG , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { STB0899_I2CCFG , 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) { STB0899_I2CRPT , 0x58 }, /* Repeater=8, Stop=disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) { STB0899_IOPVALUE5 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) { STB0899_IOPVALUE4 , 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) { STB0899_IOPVALUE3 , 0xc9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) { STB0899_IOPVALUE2 , 0x90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) { STB0899_IOPVALUE1 , 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) { STB0899_IOPVALUE0 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) { STB0899_GPIO00CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) { STB0899_GPIO01CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) { STB0899_GPIO02CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) { STB0899_GPIO03CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) { STB0899_GPIO04CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) { STB0899_GPIO05CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) { STB0899_GPIO06CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) { STB0899_GPIO07CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) { STB0899_GPIO08CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) { STB0899_GPIO09CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) { STB0899_GPIO10CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) { STB0899_GPIO11CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) { STB0899_GPIO12CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) { STB0899_GPIO13CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) { STB0899_GPIO14CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) { STB0899_GPIO15CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) { STB0899_GPIO16CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) { STB0899_GPIO17CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) { STB0899_GPIO18CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) { STB0899_GPIO19CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) { STB0899_GPIO20CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) { STB0899_SDATCFG , 0xb8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) { STB0899_SCLTCFG , 0xba },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) { STB0899_AGCRFCFG , 0x08 }, /* 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) { STB0899_GPIO22 , 0x82 }, /* AGCBB2CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) { STB0899_GPIO21 , 0x91 }, /* AGCBB1CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) { STB0899_DIRCLKCFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) { STB0899_CLKOUT27CFG , 0x7e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) { STB0899_STDBYCFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) { STB0899_CS0CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) { STB0899_CS1CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) { STB0899_DISEQCOCFG , 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { STB0899_GPIO32CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { STB0899_GPIO33CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) { STB0899_GPIO34CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) { STB0899_GPIO35CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) { STB0899_GPIO36CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) { STB0899_GPIO37CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) { STB0899_GPIO38CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) { STB0899_GPIO39CFG , 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) { STB0899_NCOARSE , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) { STB0899_SYNTCTRL , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) { STB0899_FILTCTRL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) { STB0899_SYSCTRL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) { STB0899_STOPCLK1 , 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) { STB0899_STOPCLK2 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) { STB0899_INTBUFSTATUS , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) { STB0899_INTBUFCTRL , 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) { 0xffff , 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const struct stb0899_s1_reg knc1_stb0899_s1_init_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) { STB0899_DEMOD , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) { STB0899_RCOMPC , 0xc9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) { STB0899_AGC1CN , 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) { STB0899_AGC1REF , 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) { STB0899_RTC , 0x7a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) { STB0899_TMGCFG , 0x4e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) { STB0899_AGC2REF , 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { STB0899_TLSR , 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) { STB0899_CFD , 0xee },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) { STB0899_ACLC , 0x87 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) { STB0899_BCLC , 0x94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) { STB0899_EQON , 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) { STB0899_LDT , 0xdd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) { STB0899_LDT2 , 0xc9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) { STB0899_EQUALREF , 0xb4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) { STB0899_TMGRAMP , 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) { STB0899_TMGTHD , 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) { STB0899_IDCCOMP , 0xfb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) { STB0899_QDCCOMP , 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) { STB0899_POWERI , 0x3b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) { STB0899_POWERQ , 0x3d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) { STB0899_RCOMP , 0x81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) { STB0899_AGCIQIN , 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) { STB0899_AGC2I1 , 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) { STB0899_AGC2I2 , 0xf5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) { STB0899_TLIR , 0x25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) { STB0899_RTF , 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) { STB0899_DSTATUS , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) { STB0899_LDI , 0xca },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) { STB0899_CFRM , 0xf1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) { STB0899_CFRL , 0xf3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) { STB0899_NIRM , 0x2a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) { STB0899_NIRL , 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) { STB0899_ISYMB , 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) { STB0899_QSYMB , 0xfa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) { STB0899_SFRH , 0x2f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) { STB0899_SFRM , 0x68 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) { STB0899_SFRL , 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) { STB0899_SFRUPH , 0x2f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) { STB0899_SFRUPM , 0x68 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) { STB0899_SFRUPL , 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) { STB0899_EQUAI1 , 0xfd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) { STB0899_EQUAQ1 , 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) { STB0899_EQUAI2 , 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) { STB0899_EQUAQ2 , 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) { STB0899_EQUAI3 , 0xdf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) { STB0899_EQUAQ3 , 0xfa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) { STB0899_EQUAI4 , 0x37 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) { STB0899_EQUAQ4 , 0x0d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) { STB0899_EQUAI5 , 0xbd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) { STB0899_EQUAQ5 , 0xf7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) { STB0899_DSTATUS2 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) { STB0899_VSTATUS , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) { STB0899_VERROR , 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) { STB0899_IQSWAP , 0x2a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) { STB0899_ECNT1M , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) { STB0899_ECNT1L , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) { STB0899_ECNT2M , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) { STB0899_ECNT2L , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) { STB0899_ECNT3M , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) { STB0899_ECNT3L , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) { STB0899_FECAUTO1 , 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) { STB0899_FECM , 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) { STB0899_VTH12 , 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) { STB0899_VTH23 , 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) { STB0899_VTH34 , 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) { STB0899_VTH56 , 0x4e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) { STB0899_VTH67 , 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) { STB0899_VTH78 , 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) { STB0899_PRVIT , 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) { STB0899_VITSYNC , 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) { STB0899_RSULC , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) { STB0899_TSULC , 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) { STB0899_RSLLC , 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) { STB0899_TSLPL , 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) { STB0899_TSCFGH , 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) { STB0899_TSCFGM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) { STB0899_TSCFGL , 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) { STB0899_TSOUT , 0x4d }, /* 0x0d for CAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) { STB0899_RSSYNCDEL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) { STB0899_TSINHDELH , 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { STB0899_TSINHDELM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) { STB0899_TSINHDELL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) { STB0899_TSLLSTKM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) { STB0899_TSLLSTKL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) { STB0899_TSULSTKM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) { STB0899_TSULSTKL , 0xab },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) { STB0899_PCKLENUL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) { STB0899_PCKLENLL , 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) { STB0899_RSPCKLEN , 0xcc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) { STB0899_TSSTATUS , 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) { STB0899_ERRCTRL1 , 0xb6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) { STB0899_ERRCTRL2 , 0x96 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) { STB0899_ERRCTRL3 , 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) { STB0899_DMONMSK1 , 0x27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) { STB0899_DMONMSK0 , 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) { STB0899_DEMAPVIT , 0x5c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) { STB0899_PLPARM , 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { STB0899_PDELCTRL , 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) { STB0899_PDELCTRL2 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) { STB0899_BBHCTRL1 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) { STB0899_BBHCTRL2 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) { STB0899_HYSTTHRESH , 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) { STB0899_MATCSTM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) { STB0899_MATCSTL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) { STB0899_UPLCSTM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) { STB0899_UPLCSTL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) { STB0899_DFLCSTM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) { STB0899_DFLCSTL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) { STB0899_SYNCCST , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) { STB0899_SYNCDCSTM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) { STB0899_SYNCDCSTL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) { STB0899_ISI_ENTRY , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) { STB0899_ISI_BIT_EN , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) { STB0899_MATSTRM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) { STB0899_MATSTRL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) { STB0899_UPLSTRM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) { STB0899_UPLSTRL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) { STB0899_DFLSTRM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) { STB0899_DFLSTRL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) { STB0899_SYNCSTR , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) { STB0899_SYNCDSTRM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) { STB0899_SYNCDSTRL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) { STB0899_CFGPDELSTATUS1 , 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) { STB0899_CFGPDELSTATUS2 , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) { STB0899_BBFERRORM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) { STB0899_BBFERRORL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) { STB0899_UPKTERRORM , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) { STB0899_UPKTERRORL , 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) { 0xffff , 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* STB0899 demodulator config for the KNC1 and clones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static struct stb0899_config knc1_dvbs2_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .init_dev = knc1_stb0899_s1_init_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .init_s2_demod = stb0899_s2_init_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .init_s1_demod = knc1_stb0899_s1_init_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .init_s2_fec = stb0899_s2_init_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .init_tst = stb0899_s1_init_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .postproc = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .demod_address = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) // .ts_output_mode = STB0899_OUT_PARALLEL, /* types = SERIAL/PARALLEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .block_sync_mode = STB0899_SYNC_FORCED, /* DSS, SYNC_FORCED/UNSYNCED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) // .ts_pfbit_toggle = STB0899_MPEG_NORMAL, /* DirecTV, MPEG toggling seq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .xtal_freq = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .inversion = IQ_SWAP_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .lo_clk = 76500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .hi_clk = 90000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .esno_ave = STB0899_DVBS2_ESNO_AVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .esno_quant = STB0899_DVBS2_ESNO_QUANT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .avframes_coarse = STB0899_DVBS2_AVFRAMES_COARSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .avframes_fine = STB0899_DVBS2_AVFRAMES_FINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .miss_threshold = STB0899_DVBS2_MISS_THRESHOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .uwp_threshold_acq = STB0899_DVBS2_UWP_THRESHOLD_ACQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .uwp_threshold_track = STB0899_DVBS2_UWP_THRESHOLD_TRACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .uwp_threshold_sof = STB0899_DVBS2_UWP_THRESHOLD_SOF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .sof_search_timeout = STB0899_DVBS2_SOF_SEARCH_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .btr_nco_bits = STB0899_DVBS2_BTR_NCO_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .btr_gain_shift_offset = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .crl_nco_bits = STB0899_DVBS2_CRL_NCO_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .ldpc_max_iter = STB0899_DVBS2_LDPC_MAX_ITER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .tuner_get_frequency = tda8261_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .tuner_set_frequency = tda8261_set_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .tuner_set_bandwidth = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .tuner_get_bandwidth = tda8261_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .tuner_set_rfsiggain = NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * SD1878/SHA tuner config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * 1F, Single I/P, Horizontal mount, High Sensitivity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static const struct tda8261_config sd1878c_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) // .name = "SD1878/SHA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .addr = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .step_size = TDA8261_STEP_1000 /* kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static u8 read_pwm(struct budget_av *budget_av)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u8 b = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) u8 pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct i2c_msg msg[] = { {.addr = 0x50,.flags = 0,.buf = &b,.len = 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {.addr = 0x50,.flags = I2C_M_RD,.buf = &pwm,.len = 1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if ((i2c_transfer(&budget_av->budget.i2c_adap, msg, 2) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) || (pwm == 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) pwm = 0x48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define SUBID_DVBS_KNC1 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define SUBID_DVBS_KNC1_PLUS 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define SUBID_DVBS_TYPHOON 0x4f56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define SUBID_DVBS_CINERGY1200 0x1154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define SUBID_DVBS_CYNERGY1200N 0x1155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define SUBID_DVBS_TV_STAR 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define SUBID_DVBS_TV_STAR_PLUS_X4 0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define SUBID_DVBS_TV_STAR_CI 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define SUBID_DVBS2_KNC1 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define SUBID_DVBS2_KNC1_OEM 0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define SUBID_DVBS_EASYWATCH_1 0x001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define SUBID_DVBS_EASYWATCH_2 0x001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define SUBID_DVBS2_EASYWATCH 0x001d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define SUBID_DVBS_EASYWATCH 0x001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define SUBID_DVBC_EASYWATCH 0x002a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define SUBID_DVBC_EASYWATCH_MK3 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define SUBID_DVBC_KNC1 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define SUBID_DVBC_KNC1_PLUS 0x0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define SUBID_DVBC_KNC1_MK3 0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define SUBID_DVBC_KNC1_TDA10024 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define SUBID_DVBC_KNC1_PLUS_MK3 0x0023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define SUBID_DVBC_CINERGY1200 0x1156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define SUBID_DVBC_CINERGY1200_MK3 0x1176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define SUBID_DVBT_EASYWATCH 0x003a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define SUBID_DVBT_KNC1_PLUS 0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define SUBID_DVBT_KNC1 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define SUBID_DVBT_CINERGY1200 0x1157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static void frontend_init(struct budget_av *budget_av)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct saa7146_dev * saa = budget_av->budget.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct dvb_frontend * fe = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Enable / PowerON Frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) saa7146_setgpio(saa, 0, SAA7146_GPIO_OUTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* Wait for PowerON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* additional setup necessary for the PLUS cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) switch (saa->pci->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) case SUBID_DVBS_KNC1_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) case SUBID_DVBC_KNC1_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) case SUBID_DVBT_KNC1_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) case SUBID_DVBC_EASYWATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) case SUBID_DVBC_KNC1_PLUS_MK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) case SUBID_DVBS2_KNC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) case SUBID_DVBS2_KNC1_OEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) case SUBID_DVBS2_EASYWATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) switch (saa->pci->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) case SUBID_DVBS_KNC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * maybe that setting is needed for other dvb-s cards as well,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * but so far it has been only confirmed for this type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) budget_av->reinitialise_demod = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case SUBID_DVBS_KNC1_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) case SUBID_DVBS_EASYWATCH_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (saa->pci->subsystem_vendor == 0x1894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) fe = dvb_attach(stv0299_attach, &cinergy_1200s_1894_0010_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) &budget_av->budget.i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dvb_attach(tua6100_attach, fe, 0x60, &budget_av->budget.i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) fe = dvb_attach(stv0299_attach, &typhoon_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) &budget_av->budget.i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) fe->ops.tuner_ops.set_params = philips_su1278_ty_ci_tuner_set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) case SUBID_DVBS_TV_STAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) case SUBID_DVBS_TV_STAR_PLUS_X4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) case SUBID_DVBS_TV_STAR_CI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) case SUBID_DVBS_CYNERGY1200N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) case SUBID_DVBS_EASYWATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) case SUBID_DVBS_EASYWATCH_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) fe = dvb_attach(stv0299_attach, &philips_sd1878_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) &budget_av->budget.i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dvb_attach(dvb_pll_attach, fe, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) &budget_av->budget.i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) DVB_PLL_PHILIPS_SD1878_TDA8261);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) case SUBID_DVBS_TYPHOON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) fe = dvb_attach(stv0299_attach, &typhoon_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) &budget_av->budget.i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) fe->ops.tuner_ops.set_params = philips_su1278_ty_ci_tuner_set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) case SUBID_DVBS2_KNC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) case SUBID_DVBS2_KNC1_OEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) case SUBID_DVBS2_EASYWATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) budget_av->reinitialise_demod = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if ((fe = dvb_attach(stb0899_attach, &knc1_dvbs2_config, &budget_av->budget.i2c_adap)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dvb_attach(tda8261_attach, fe, &sd1878c_config, &budget_av->budget.i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) case SUBID_DVBS_CINERGY1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) fe = dvb_attach(stv0299_attach, &cinergy_1200s_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) &budget_av->budget.i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) fe->ops.tuner_ops.set_params = philips_su1278_ty_ci_tuner_set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) case SUBID_DVBC_KNC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) case SUBID_DVBC_KNC1_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) case SUBID_DVBC_CINERGY1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) case SUBID_DVBC_EASYWATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) budget_av->reinitialise_demod = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) budget_av->budget.dev->i2c_bitrate = SAA7146_I2C_BUS_BIT_RATE_240;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) fe = dvb_attach(tda10021_attach, &philips_cu1216_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) &budget_av->budget.i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) read_pwm(budget_av));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (fe == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) fe = dvb_attach(tda10021_attach, &philips_cu1216_config_altaddress,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) &budget_av->budget.i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) read_pwm(budget_av));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) fe->ops.tuner_ops.set_params = philips_cu1216_tuner_set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) case SUBID_DVBC_EASYWATCH_MK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) case SUBID_DVBC_CINERGY1200_MK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) case SUBID_DVBC_KNC1_MK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) case SUBID_DVBC_KNC1_TDA10024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) case SUBID_DVBC_KNC1_PLUS_MK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) budget_av->reinitialise_demod = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) budget_av->budget.dev->i2c_bitrate = SAA7146_I2C_BUS_BIT_RATE_240;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) fe = dvb_attach(tda10023_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) &philips_cu1216_tda10023_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) &budget_av->budget.i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) read_pwm(budget_av));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) fe->ops.tuner_ops.set_params = philips_cu1216_tuner_set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) case SUBID_DVBT_EASYWATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) case SUBID_DVBT_KNC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) case SUBID_DVBT_KNC1_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) case SUBID_DVBT_CINERGY1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) budget_av->reinitialise_demod = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) fe = dvb_attach(tda10046_attach, &philips_tu1216_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) &budget_av->budget.i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) fe->ops.tuner_ops.init = philips_tu1216_tuner_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) fe->ops.tuner_ops.set_params = philips_tu1216_tuner_set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (fe == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) pr_err("A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) saa->pci->vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) saa->pci->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) saa->pci->subsystem_vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) saa->pci->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) budget_av->budget.dvb_frontend = fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (dvb_register_frontend(&budget_av->budget.dvb_adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) budget_av->budget.dvb_frontend)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) pr_err("Frontend registration failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dvb_frontend_detach(budget_av->budget.dvb_frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) budget_av->budget.dvb_frontend = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static void budget_av_irq(struct saa7146_dev *dev, u32 * isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct budget_av *budget_av = (struct budget_av *) dev->ext_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) dprintk(8, "dev: %p, budget_av: %p\n", dev, budget_av);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (*isr & MASK_10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) ttpci_budget_irq10_handler(dev, isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static int budget_av_detach(struct saa7146_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct budget_av *budget_av = (struct budget_av *) dev->ext_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dprintk(2, "dev: %p\n", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (1 == budget_av->has_saa7113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) saa7146_setgpio(dev, 0, SAA7146_GPIO_OUTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) saa7146_unregister_device(&budget_av->vd, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) saa7146_vv_release(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (budget_av->budget.ci_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ciintf_deinit(budget_av);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (budget_av->budget.dvb_frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) dvb_unregister_frontend(budget_av->budget.dvb_frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dvb_frontend_detach(budget_av->budget.dvb_frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) err = ttpci_budget_deinit(&budget_av->budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) kfree(budget_av);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define KNC1_INPUTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static struct v4l2_input knc1_inputs[KNC1_INPUTS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) { 0, "Composite", V4L2_INPUT_TYPE_TUNER, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) V4L2_STD_PAL_BG | V4L2_STD_NTSC_M, 0, V4L2_IN_CAP_STD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) { 1, "S-Video", V4L2_INPUT_TYPE_CAMERA, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) V4L2_STD_PAL_BG | V4L2_STD_NTSC_M, 0, V4L2_IN_CAP_STD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) dprintk(1, "VIDIOC_ENUMINPUT %d\n", i->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (i->index >= KNC1_INPUTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) memcpy(i, &knc1_inputs[i->index], sizeof(struct v4l2_input));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static int vidioc_g_input(struct file *file, void *fh, unsigned int *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct budget_av *budget_av = (struct budget_av *)dev->ext_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) *i = budget_av->cur_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) dprintk(1, "VIDIOC_G_INPUT %d\n", *i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static int vidioc_s_input(struct file *file, void *fh, unsigned int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct budget_av *budget_av = (struct budget_av *)dev->ext_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) dprintk(1, "VIDIOC_S_INPUT %d\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return saa7113_setinput(budget_av, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static struct saa7146_ext_vv vv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static int budget_av_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct budget_av *budget_av;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) u8 *mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) dprintk(2, "dev: %p\n", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (!(budget_av = kzalloc(sizeof(struct budget_av), GFP_KERNEL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) budget_av->has_saa7113 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) budget_av->budget.ci_present = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) dev->ext_priv = budget_av;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) err = ttpci_budget_init(&budget_av->budget, dev, info, THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) adapter_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) kfree(budget_av);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* knc1 initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) saa7146_write(dev, DD1_STREAM_B, 0x04000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) saa7146_write(dev, DD1_INIT, 0x07000600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) saa7146_write(dev, MC2, MASK_09 | MASK_25 | MASK_10 | MASK_26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (saa7113_init(budget_av) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) budget_av->has_saa7113 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) err = saa7146_vv_init(dev, &vv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* fixme: proper cleanup here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ERR("cannot init vv subsystem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) vv_data.vid_ops.vidioc_enum_input = vidioc_enum_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) vv_data.vid_ops.vidioc_g_input = vidioc_g_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) vv_data.vid_ops.vidioc_s_input = vidioc_s_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if ((err = saa7146_register_device(&budget_av->vd, dev, "knc1", VFL_TYPE_VIDEO))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* fixme: proper cleanup here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ERR("cannot register capture v4l2 device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) saa7146_vv_release(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* beware: this modifies dev->vv ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) saa7146_set_hps_source_and_sync(dev, SAA7146_HPS_SOURCE_PORT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) SAA7146_HPS_SYNC_PORT_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) saa7113_setinput(budget_av, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* fixme: find some sane values here... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) saa7146_write(dev, PCI_BT_V1, 0x1c00101f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) mac = budget_av->budget.dvb_adapter.proposed_mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (i2c_readregs(&budget_av->budget.i2c_adap, 0xa0, 0x30, mac, 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) pr_err("KNC1-%d: Could not read MAC from KNC1 card\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) budget_av->budget.dvb_adapter.num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) eth_zero_addr(mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) pr_info("KNC1-%d: MAC addr = %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) budget_av->budget.dvb_adapter.num, mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) budget_av->budget.dvb_adapter.priv = budget_av;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) frontend_init(budget_av);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ciintf_init(budget_av);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ttpci_budget_init_hooks(&budget_av->budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static struct saa7146_standard standard[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {.name = "PAL",.id = V4L2_STD_PAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .v_offset = 0x17,.v_field = 288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .h_offset = 0x14,.h_pixels = 680,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .v_max_out = 576,.h_max_out = 768 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {.name = "NTSC",.id = V4L2_STD_NTSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .v_offset = 0x16,.v_field = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .h_offset = 0x06,.h_pixels = 708,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .v_max_out = 480,.h_max_out = 640, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static struct saa7146_ext_vv vv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .inputs = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .capabilities = 0, // perhaps later: V4L2_CAP_VBI_CAPTURE, but that need tweaking with the saa7113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .stds = &standard[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .num_stds = ARRAY_SIZE(standard),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static struct saa7146_extension budget_extension;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) MAKE_BUDGET_INFO(knc1s, "KNC1 DVB-S", BUDGET_KNC1S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) MAKE_BUDGET_INFO(knc1s2,"KNC1 DVB-S2", BUDGET_KNC1S2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) MAKE_BUDGET_INFO(sates2,"Satelco EasyWatch DVB-S2", BUDGET_KNC1S2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) MAKE_BUDGET_INFO(knc1c, "KNC1 DVB-C", BUDGET_KNC1C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) MAKE_BUDGET_INFO(knc1t, "KNC1 DVB-T", BUDGET_KNC1T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) MAKE_BUDGET_INFO(kncxs, "KNC TV STAR DVB-S", BUDGET_TVSTAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) MAKE_BUDGET_INFO(satewpls, "Satelco EasyWatch DVB-S light", BUDGET_TVSTAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) MAKE_BUDGET_INFO(satewpls1, "Satelco EasyWatch DVB-S light", BUDGET_KNC1S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) MAKE_BUDGET_INFO(satewps, "Satelco EasyWatch DVB-S", BUDGET_KNC1S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) MAKE_BUDGET_INFO(satewplc, "Satelco EasyWatch DVB-C", BUDGET_KNC1CP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) MAKE_BUDGET_INFO(satewcmk3, "Satelco EasyWatch DVB-C MK3", BUDGET_KNC1C_MK3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) MAKE_BUDGET_INFO(satewt, "Satelco EasyWatch DVB-T", BUDGET_KNC1T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) MAKE_BUDGET_INFO(knc1sp, "KNC1 DVB-S Plus", BUDGET_KNC1SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) MAKE_BUDGET_INFO(knc1spx4, "KNC1 DVB-S Plus X4", BUDGET_KNC1SP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) MAKE_BUDGET_INFO(knc1cp, "KNC1 DVB-C Plus", BUDGET_KNC1CP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) MAKE_BUDGET_INFO(knc1cmk3, "KNC1 DVB-C MK3", BUDGET_KNC1C_MK3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) MAKE_BUDGET_INFO(knc1ctda10024, "KNC1 DVB-C TDA10024", BUDGET_KNC1C_TDA10024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) MAKE_BUDGET_INFO(knc1cpmk3, "KNC1 DVB-C Plus MK3", BUDGET_KNC1CP_MK3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) MAKE_BUDGET_INFO(knc1tp, "KNC1 DVB-T Plus", BUDGET_KNC1TP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) MAKE_BUDGET_INFO(cin1200s, "TerraTec Cinergy 1200 DVB-S", BUDGET_CIN1200S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) MAKE_BUDGET_INFO(cin1200sn, "TerraTec Cinergy 1200 DVB-S", BUDGET_CIN1200S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) MAKE_BUDGET_INFO(cin1200c, "Terratec Cinergy 1200 DVB-C", BUDGET_CIN1200C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) MAKE_BUDGET_INFO(cin1200cmk3, "Terratec Cinergy 1200 DVB-C MK3", BUDGET_CIN1200C_MK3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) MAKE_BUDGET_INFO(cin1200t, "Terratec Cinergy 1200 DVB-T", BUDGET_CIN1200T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static const struct pci_device_id pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) MAKE_EXTENSION_PCI(knc1s, 0x1131, 0x4f56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) MAKE_EXTENSION_PCI(knc1s, 0x1131, 0x0010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) MAKE_EXTENSION_PCI(knc1s, 0x1894, 0x0010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) MAKE_EXTENSION_PCI(knc1sp, 0x1131, 0x0011),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) MAKE_EXTENSION_PCI(knc1sp, 0x1894, 0x0011),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0014),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) MAKE_EXTENSION_PCI(knc1spx4, 0x1894, 0x0015),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) MAKE_EXTENSION_PCI(kncxs, 0x1894, 0x0016),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) MAKE_EXTENSION_PCI(knc1s2, 0x1894, 0x0018),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) MAKE_EXTENSION_PCI(knc1s2, 0x1894, 0x0019),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) MAKE_EXTENSION_PCI(sates2, 0x1894, 0x001d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) MAKE_EXTENSION_PCI(satewpls, 0x1894, 0x001e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) MAKE_EXTENSION_PCI(satewpls1, 0x1894, 0x001a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) MAKE_EXTENSION_PCI(satewps, 0x1894, 0x001b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) MAKE_EXTENSION_PCI(satewplc, 0x1894, 0x002a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) MAKE_EXTENSION_PCI(satewcmk3, 0x1894, 0x002c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) MAKE_EXTENSION_PCI(satewt, 0x1894, 0x003a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) MAKE_EXTENSION_PCI(knc1c, 0x1894, 0x0020),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) MAKE_EXTENSION_PCI(knc1cp, 0x1894, 0x0021),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) MAKE_EXTENSION_PCI(knc1cmk3, 0x1894, 0x0022),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) MAKE_EXTENSION_PCI(knc1ctda10024, 0x1894, 0x0028),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) MAKE_EXTENSION_PCI(knc1cpmk3, 0x1894, 0x0023),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) MAKE_EXTENSION_PCI(knc1t, 0x1894, 0x0030),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) MAKE_EXTENSION_PCI(knc1tp, 0x1894, 0x0031),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) MAKE_EXTENSION_PCI(cin1200s, 0x153b, 0x1154),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) MAKE_EXTENSION_PCI(cin1200sn, 0x153b, 0x1155),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) MAKE_EXTENSION_PCI(cin1200c, 0x153b, 0x1156),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) MAKE_EXTENSION_PCI(cin1200cmk3, 0x153b, 0x1176),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) MAKE_EXTENSION_PCI(cin1200t, 0x153b, 0x1157),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .vendor = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) MODULE_DEVICE_TABLE(pci, pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static struct saa7146_extension budget_extension = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .name = "budget_av",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .flags = SAA7146_USE_I2C_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .pci_tbl = pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .attach = budget_av_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .detach = budget_av_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .irq_mask = MASK_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .irq_func = budget_av_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static int __init budget_av_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) return saa7146_register_extension(&budget_extension);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static void __exit budget_av_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) saa7146_unregister_extension(&budget_extension);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) module_init(budget_av_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) module_exit(budget_av_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) MODULE_AUTHOR("Ralph Metzler, Marcus Metzler, Michael Hunold, others");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) MODULE_DESCRIPTION("driver for the SAA7146 based so-called budget PCI DVB w/ analog input and CI-module (e.g. the KNC cards)");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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