^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Original author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ben Collins <bcollins@ubuntu.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Additional work by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * John Brooks <john.brooks@bluecherry.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __SOLO6X10_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __SOLO6X10_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/stringify.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/videobuf2-v4l2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "solo6x10-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef PCI_VENDOR_ID_SOFTLOGIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCI_VENDOR_ID_SOFTLOGIC 0x9413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCI_DEVICE_ID_SOLO6010 0x6010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCI_DEVICE_ID_SOLO6110 0x6110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #ifndef PCI_VENDOR_ID_BLUECHERRY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCI_VENDOR_ID_BLUECHERRY 0x1BB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Neugent Softlogic 6010 based cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCI_DEVICE_ID_NEUSOLO_4 0x4304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCI_DEVICE_ID_NEUSOLO_9 0x4309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_DEVICE_ID_NEUSOLO_16 0x4310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Bluecherry Softlogic 6010 based cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_DEVICE_ID_BC_SOLO_4 0x4E04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_DEVICE_ID_BC_SOLO_9 0x4E09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCI_DEVICE_ID_BC_SOLO_16 0x4E10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Bluecherry Softlogic 6110 based cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCI_DEVICE_ID_BC_6110_4 0x5304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCI_DEVICE_ID_BC_6110_8 0x5308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCI_DEVICE_ID_BC_6110_16 0x5310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif /* Bluecherry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Used in pci_device_id, and solo_dev->type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SOLO_DEV_6010 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SOLO_DEV_6110 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SOLO6X10_NAME "solo6x10"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SOLO_MAX_CHANNELS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SOLO6X10_VERSION "3.0.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * The SOLO6x10 actually has 8 i2c channels, but we only use 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 0 - Techwell chip(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 1 - SAA7128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SOLO_I2C_ADAPTERS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SOLO_I2C_TW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SOLO_I2C_SAA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* DMA Engine setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SOLO_NR_P2M 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SOLO_NR_P2M_DESC 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SOLO_P2M_DESC_SIZE (SOLO_NR_P2M_DESC * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Encoder standard modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SOLO_ENC_MODE_CIF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SOLO_ENC_MODE_HD1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SOLO_ENC_MODE_D1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SOLO_DEFAULT_QP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SOLO_CID_CUSTOM_BASE (V4L2_CID_USER_BASE | 0xf000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define V4L2_CID_MOTION_TRACE (SOLO_CID_CUSTOM_BASE+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define V4L2_CID_OSD_TEXT (SOLO_CID_CUSTOM_BASE+3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Motion thresholds are in a table of 64x64 samples, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * each sample representing 16x16 pixels of the source. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * effect, 44x30 samples are used for NTSC, and 44x36 for PAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * The 5th sample on the 10th row is (10*64)+5 = 645.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Internally it is stored as a 45x45 array (45*16 = 720, which is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * maximum PAL/NTSC width).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SOLO_MOTION_SZ (45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum SOLO_I2C_STATE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) IIC_STATE_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) IIC_STATE_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) IIC_STATE_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) IIC_STATE_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) IIC_STATE_STOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Defined in Table 4-16, Page 68-69 of the 6010 Datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct solo_p2m_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 ext_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct solo_p2m_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int desc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct solo_p2m_desc *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OSD_TEXT_MAX 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct solo_vb2_buf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct vb2_v4l2_buffer vb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum solo_enc_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SOLO_ENC_TYPE_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SOLO_ENC_TYPE_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct solo_enc_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct solo_dev *solo_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* V4L2 Items */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_ctrl *md_thresholds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct video_device *vfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* General accounting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spinlock_t motion_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 mode, gop, qp, interlaced, interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 bw_weight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u16 motion_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bool motion_global;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bool motion_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* OSD buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) char osd_text[OSD_TEXT_MAX + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 osd_buf[SOLO_EOSD_EXT_SIZE_MAX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* VOP stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 vop[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int vop_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 jpeg_header[1024];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int jpeg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum solo_enc_types type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct vb2_queue vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct list_head vidq_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int desc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int desc_nelts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct solo_p2m_desc *desc_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dma_addr_t desc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) spinlock_t av_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* The SOLO6x10 PCI Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct solo_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* General stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int time_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int usec_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int clock_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int nr_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int nr_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 motion_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct v4l2_device v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct gpio_chip gpio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* tw28xx accounting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 tw2865, tw2864, tw2815;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 tw28_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* i2c related items */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct i2c_adapter i2c_adap[SOLO_I2C_ADAPTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) enum SOLO_I2C_STATE i2c_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct mutex i2c_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int i2c_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) wait_queue_head_t i2c_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct i2c_msg *i2c_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int i2c_msg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int i2c_msg_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* P2M DMA Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct solo_p2m_dev p2m_dev[SOLO_NR_P2M];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) atomic_t p2m_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int p2m_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int p2m_timeouts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* V4L2 Display items */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct video_device *vfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int erasing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int frame_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 cur_disp_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) wait_queue_head_t disp_thread_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct v4l2_ctrl_handler disp_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* V4L2 Encoder items */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct solo_enc_dev *v4l2_enc[SOLO_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u16 enc_bw_remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* IDX into hw mp4 encoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 enc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Current video settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 video_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 video_hsize, video_vsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u16 vout_hstart, vout_vstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 vin_hstart, vin_vstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* JPEG Qp setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) spinlock_t jpeg_qp_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 jpeg_qp[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Audio components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct snd_card *snd_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct snd_pcm *snd_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) atomic_t snd_users;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int g723_hw_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* sysfs stuffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int sdram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct bin_attribute sdram_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned int sys_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Ring thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct task_struct *ring_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) wait_queue_head_t ring_thread_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* VOP_HEADER handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void *vh_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dma_addr_t vh_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int vh_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Buffer handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct vb2_queue vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct task_struct *kthread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int old_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct list_head vidq_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static inline u32 solo_reg_read(struct solo_dev *solo_dev, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return readl(solo_dev->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static inline void solo_reg_write(struct solo_dev *solo_dev, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writel(data, solo_dev->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pci_read_config_word(solo_dev->pdev, PCI_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static inline void solo_irq_on(struct solo_dev *dev, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev->irq_mask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) solo_reg_write(dev, SOLO_IRQ_MASK, dev->irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static inline void solo_irq_off(struct solo_dev *dev, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev->irq_mask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) solo_reg_write(dev, SOLO_IRQ_MASK, dev->irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Init/exit routines for subsystems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int solo_disp_init(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void solo_disp_exit(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int solo_gpio_init(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void solo_gpio_exit(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int solo_i2c_init(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) void solo_i2c_exit(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int solo_p2m_init(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void solo_p2m_exit(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int solo_v4l2_init(struct solo_dev *solo_dev, unsigned nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void solo_v4l2_exit(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int solo_enc_init(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void solo_enc_exit(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int solo_enc_v4l2_init(struct solo_dev *solo_dev, unsigned nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void solo_enc_v4l2_exit(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int solo_g723_init(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) void solo_g723_exit(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* ISR's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int solo_i2c_isr(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) void solo_p2m_isr(struct solo_dev *solo_dev, int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void solo_p2m_error_isr(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) void solo_enc_v4l2_isr(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void solo_g723_isr(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void solo_motion_isr(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) void solo_video_in_isr(struct solo_dev *solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* i2c read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 solo_i2c_readbyte(struct solo_dev *solo_dev, int id, u8 addr, u8 off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) void solo_i2c_writebyte(struct solo_dev *solo_dev, int id, u8 addr, u8 off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* P2M DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dma_addr_t dma_addr, u32 ext_addr, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int repeat, u32 ext_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) void *sys_addr, u32 ext_addr, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int repeat, u32 ext_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dma_addr_t dma_addr, u32 ext_addr, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int repeat, u32 ext_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int solo_p2m_dma_desc(struct solo_dev *solo_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct solo_p2m_desc *desc, dma_addr_t desc_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int desc_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Global s_std ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int solo_set_video_type(struct solo_dev *solo_dev, bool is_50hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) void solo_update_mode(struct solo_enc_dev *solo_enc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Set the threshold for motion detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int solo_set_motion_threshold(struct solo_dev *solo_dev, u8 ch, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int solo_set_motion_block(struct solo_dev *solo_dev, u8 ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) const u16 *thresholds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SOLO_DEF_MOT_THRESH 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Write text on OSD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int solo_osd_print(struct solo_enc_dev *solo_enc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* EEPROM commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int solo_eeprom_ewen(struct solo_dev *solo_dev, int w_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) __be16 solo_eeprom_read(struct solo_dev *solo_dev, int loc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int solo_eeprom_write(struct solo_dev *solo_dev, int loc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __be16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* JPEG Qp functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int solo_g_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CHK_FLAGS(v, flags) (((v) & (flags)) == (flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #endif /* __SOLO6X10_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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