^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Original author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ben Collins <bcollins@ubuntu.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Additional work by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * John Brooks <john.brooks@bluecherry.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "solo6x10.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "solo6x10-tw28.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DEFAULT_HDELAY_NTSC (32 - 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DEFAULT_HACTIVE_NTSC (720 + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DEFAULT_VDELAY_NTSC (7 - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DEFAULT_VACTIVE_NTSC (240 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DEFAULT_HDELAY_PAL (32 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DEFAULT_HACTIVE_PAL (864-DEFAULT_HDELAY_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DEFAULT_VDELAY_PAL (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DEFAULT_VACTIVE_PAL (312-DEFAULT_VDELAY_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const u8 tbl_tw2864_ntsc_template[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 0x12, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 0x12, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 0x12, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 0x12, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA3, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 0x00, 0x02, 0x00, 0xcc, 0x00, 0x80, 0x44, 0x50, /* 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 0x22, 0x01, 0xd8, 0xbc, 0xb8, 0x44, 0x38, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0x00, 0x78, 0x72, 0x3e, 0x14, 0xa5, 0xe4, 0x05, /* 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x00, 0x28, 0x44, 0x44, 0xa0, 0x88, 0x5a, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 0x08, 0x08, 0x08, 0x08, 0x1a, 0x1a, 0x1a, 0x1a, /* 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x00, 0x00, 0x00, 0xf0, 0xf0, 0xf0, 0xf0, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0x44, 0x0a, 0x00, 0xff, 0xef, 0xef, 0xef, 0xef, /* 0xb0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0x00, 0x00, 0x55, 0x00, 0xb1, 0xe4, 0x40, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 0x77, 0x77, 0x01, 0x13, 0x57, 0x9b, 0xdf, 0x20, /* 0xd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0x64, 0xa8, 0xec, 0xc1, 0x0f, 0x11, 0x11, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 0x00, 0xe0, 0xbb, 0xbb, 0x00, 0x11, 0x00, 0x00, /* 0xe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 0x11, 0x00, 0x00, 0x11, 0x00, 0x00, 0x11, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0x83, 0xb5, 0x09, 0x78, 0x85, 0x00, 0x01, 0x20, /* 0xf0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x64, 0x11, 0x40, 0xaf, 0xff, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const u8 tbl_tw2864_pal_template[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x18, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x01, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0x18, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x01, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0x18, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x01, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x18, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x01, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA3, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0x00, 0x02, 0x00, 0xcc, 0x00, 0x80, 0x44, 0x50, /* 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0x22, 0x01, 0xd8, 0xbc, 0xb8, 0x44, 0x38, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0x00, 0x78, 0x72, 0x3e, 0x14, 0xa5, 0xe4, 0x05, /* 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0x00, 0x28, 0x44, 0x44, 0xa0, 0x90, 0x5a, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x1a, 0x1a, 0x1a, /* 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 0x00, 0x00, 0x00, 0xf0, 0xf0, 0xf0, 0xf0, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0x44, 0x0a, 0x00, 0xff, 0xef, 0xef, 0xef, 0xef, /* 0xb0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0x00, 0x00, 0x55, 0x00, 0xb1, 0xe4, 0x40, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0x77, 0x77, 0x01, 0x13, 0x57, 0x9b, 0xdf, 0x20, /* 0xd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0x64, 0xa8, 0xec, 0xc1, 0x0f, 0x11, 0x11, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x00, 0xe0, 0xbb, 0xbb, 0x00, 0x11, 0x00, 0x00, /* 0xe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0x11, 0x00, 0x00, 0x11, 0x00, 0x00, 0x11, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0x83, 0xb5, 0x09, 0x00, 0xa0, 0x00, 0x01, 0x20, /* 0xf0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x64, 0x11, 0x40, 0xaf, 0xff, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const u8 tbl_tw2865_ntsc_template[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0x12, 0xff, 0x09, 0xd0, 0x00, 0x00, 0x00, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0x12, 0xff, 0x09, 0xd0, 0x00, 0x00, 0x00, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x12, 0xff, 0x09, 0xd0, 0x00, 0x00, 0x00, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x00, 0xf0, 0x70, 0x48, 0x80, 0x80, 0x00, 0x02, /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0x12, 0xff, 0x09, 0xd0, 0x00, 0x00, 0x00, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x00, 0x00, 0x90, 0x68, 0x00, 0x38, 0x80, 0x80, /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x80, 0x80, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x45, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x08, 0x00, 0x00, 0x01, 0xf1, 0x03, 0xEF, 0x03, /* 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0xE9, 0x03, 0xD9, 0x15, 0x15, 0xE4, 0xA3, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0x00, 0x02, 0x00, 0xCC, 0x00, 0x80, 0x44, 0x50, /* 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0x22, 0x01, 0xD8, 0xBC, 0xB8, 0x44, 0x38, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0x00, 0x78, 0x44, 0x3D, 0x14, 0xA5, 0xE0, 0x05, /* 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0x00, 0x28, 0x44, 0x44, 0xA0, 0x90, 0x52, 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x08, 0x08, 0x08, 0x08, 0x1A, 0x1A, 0x1B, 0x1A, /* 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x00, 0x00, 0x00, 0xF0, 0xF0, 0xF0, 0xF0, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x44, 0x4A, 0x00, 0xFF, 0xEF, 0xEF, 0xEF, 0xEF, /* 0xb0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0xFF, 0xE7, 0xE9, 0xE9, 0xEB, 0xFF, 0xD6, 0xD8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0xD8, 0xD7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0x00, 0x00, 0x55, 0x00, 0xE4, 0x39, 0x00, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x77, 0x77, 0x03, 0x20, 0x57, 0x9b, 0xdf, 0x31, /* 0xd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x64, 0xa8, 0xec, 0xd1, 0x0f, 0x11, 0x11, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x10, 0xC0, 0xAA, 0xAA, 0x00, 0x11, 0x00, 0x00, /* 0xe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x11, 0x00, 0x00, 0x11, 0x00, 0x00, 0x11, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0x83, 0xB5, 0x09, 0x78, 0x85, 0x00, 0x01, 0x20, /* 0xf0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x64, 0x51, 0x40, 0xaf, 0xFF, 0xF0, 0x00, 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const u8 tbl_tw2865_pal_template[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0x11, 0xff, 0x01, 0xc3, 0x00, 0x00, 0x01, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0x11, 0xff, 0x01, 0xc3, 0x00, 0x00, 0x01, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x11, 0xff, 0x01, 0xc3, 0x00, 0x00, 0x01, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x12, /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x11, 0xff, 0x01, 0xc3, 0x00, 0x00, 0x01, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x00, 0x94, 0x90, 0x48, 0x00, 0x38, 0x7F, 0x80, /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x80, 0x80, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0x45, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0x08, 0x00, 0x00, 0x01, 0xf1, 0x03, 0xEF, 0x03, /* 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0xEA, 0x03, 0xD9, 0x15, 0x15, 0xE4, 0xA3, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0x00, 0x02, 0x00, 0xCC, 0x00, 0x80, 0x44, 0x50, /* 0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0x22, 0x01, 0xD8, 0xBC, 0xB8, 0x44, 0x38, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 0x00, 0x78, 0x44, 0x3D, 0x14, 0xA5, 0xE0, 0x05, /* 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0x00, 0x28, 0x44, 0x44, 0xA0, 0x90, 0x52, 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x08, 0x08, 0x08, 0x08, 0x1A, 0x1A, 0x1A, 0x1A, /* 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0x00, 0x00, 0x00, 0xF0, 0xF0, 0xF0, 0xF0, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0x44, 0x4A, 0x00, 0xFF, 0xEF, 0xEF, 0xEF, 0xEF, /* 0xb0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0xFF, 0xE7, 0xE9, 0xE9, 0xE9, 0xFF, 0xD7, 0xD8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0xD9, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 0x00, 0x00, 0x55, 0x00, 0xE4, 0x39, 0x00, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 0x77, 0x77, 0x03, 0x20, 0x57, 0x9b, 0xdf, 0x31, /* 0xd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 0x64, 0xa8, 0xec, 0xd1, 0x0f, 0x11, 0x11, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0x10, 0xC0, 0xAA, 0xAA, 0x00, 0x11, 0x00, 0x00, /* 0xe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0x11, 0x00, 0x00, 0x11, 0x00, 0x00, 0x11, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0x83, 0xB5, 0x09, 0x00, 0xA0, 0x00, 0x01, 0x20, /* 0xf0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 0x64, 0x51, 0x40, 0xaf, 0xFF, 0xF0, 0x00, 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define is_tw286x(__solo, __id) (!(__solo->tw2815 & (1 << __id)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static u8 tw_readbyte(struct solo_dev *solo_dev, int chip_id, u8 tw6x_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 tw_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (is_tw286x(solo_dev, chip_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return solo_i2c_readbyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) TW_CHIP_OFFSET_ADDR(chip_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) tw6x_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return solo_i2c_readbyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) TW_CHIP_OFFSET_ADDR(chip_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tw_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void tw_writebyte(struct solo_dev *solo_dev, int chip_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 tw6x_off, u8 tw_off, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (is_tw286x(solo_dev, chip_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) solo_i2c_writebyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) TW_CHIP_OFFSET_ADDR(chip_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) tw6x_off, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) solo_i2c_writebyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) TW_CHIP_OFFSET_ADDR(chip_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) tw_off, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void tw_write_and_verify(struct solo_dev *solo_dev, u8 addr, u8 off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 rval = solo_i2c_readbyte(solo_dev, SOLO_I2C_TW, addr, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (rval == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) solo_i2c_writebyte(solo_dev, SOLO_I2C_TW, addr, off, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) msleep_interruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* printk("solo6x10/tw28: Error writing register: %02x->%02x [%02x]\n", */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* addr, off, val); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int tw2865_setup(struct solo_dev *solo_dev, u8 dev_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 tbl_tw2865_common[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (solo_dev->video_type == SOLO_VO_FMT_TYPE_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) memcpy(tbl_tw2865_common, tbl_tw2865_pal_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) sizeof(tbl_tw2865_common));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) memcpy(tbl_tw2865_common, tbl_tw2865_ntsc_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sizeof(tbl_tw2865_common));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* ALINK Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (solo_dev->nr_chans == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tbl_tw2865_common[0xd2] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) tbl_tw2865_common[0xcf] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } else if (solo_dev->nr_chans == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tbl_tw2865_common[0xd2] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tbl_tw2865_common[0xcf] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else if (solo_dev->nr_chans == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tbl_tw2865_common[0xd2] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tbl_tw2865_common[0xcf] = 0x83;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else if (dev_addr == TW_CHIP_OFFSET_ADDR(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tbl_tw2865_common[0xcf] = 0x83;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) else if (dev_addr == TW_CHIP_OFFSET_ADDR(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tbl_tw2865_common[0xcf] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (i = 0; i < 0xff; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Skip read only registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case 0xb8 ... 0xc1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case 0xc4 ... 0xc7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 0xfd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) switch (i & ~0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case 0x0c ... 0x0d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tw_write_and_verify(solo_dev, dev_addr, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tbl_tw2865_common[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int tw2864_setup(struct solo_dev *solo_dev, u8 dev_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u8 tbl_tw2864_common[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (solo_dev->video_type == SOLO_VO_FMT_TYPE_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) memcpy(tbl_tw2864_common, tbl_tw2864_pal_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sizeof(tbl_tw2864_common));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) memcpy(tbl_tw2864_common, tbl_tw2864_ntsc_template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) sizeof(tbl_tw2864_common));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (solo_dev->tw2865 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* IRQ Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (solo_dev->nr_chans == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tbl_tw2864_common[0xd2] = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tbl_tw2864_common[0xcf] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else if (solo_dev->nr_chans == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tbl_tw2864_common[0xd2] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (dev_addr == TW_CHIP_OFFSET_ADDR(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tbl_tw2864_common[0xcf] = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) else if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tbl_tw2864_common[0xcf] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) } else if (solo_dev->nr_chans == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tbl_tw2864_common[0xd2] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (dev_addr == TW_CHIP_OFFSET_ADDR(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tbl_tw2864_common[0xcf] = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tbl_tw2864_common[0xcf] = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else if (dev_addr == TW_CHIP_OFFSET_ADDR(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tbl_tw2864_common[0xcf] = 0x43;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) else if (dev_addr == TW_CHIP_OFFSET_ADDR(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) tbl_tw2864_common[0xcf] = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* ALINK Mode. Assumes that the first tw28xx is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * 2865 and these are in cascade. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i <= 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) tbl_tw2864_common[0x08 | i << 4] = 0x12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (solo_dev->nr_chans == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) tbl_tw2864_common[0xd2] = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) tbl_tw2864_common[0xcf] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } else if (solo_dev->nr_chans == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) tbl_tw2864_common[0xd2] = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tbl_tw2864_common[0xcf] = 0x83;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) else if (dev_addr == TW_CHIP_OFFSET_ADDR(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tbl_tw2864_common[0xcf] = 0x83;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else if (dev_addr == TW_CHIP_OFFSET_ADDR(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) tbl_tw2864_common[0xcf] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) for (i = 0; i < 0xff; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Skip read only registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case 0xb8 ... 0xc1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case 0xfd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) switch (i & ~0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case 0x0c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case 0x0d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) tw_write_and_verify(solo_dev, dev_addr, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tbl_tw2864_common[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int tw2815_setup(struct solo_dev *solo_dev, u8 dev_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 tbl_ntsc_tw2815_common[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0x00, 0xc8, 0x20, 0xd0, 0x06, 0xf0, 0x08, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x80, 0x80, 0x80, 0x02, 0x06, 0x00, 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 tbl_pal_tw2815_common[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 0x00, 0x88, 0x20, 0xd0, 0x05, 0x20, 0x28, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0x80, 0x80, 0x80, 0x82, 0x06, 0x00, 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 tbl_tw2815_sfr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0x00, 0x00, 0x00, 0xc0, 0x45, 0xa0, 0xd0, 0x2f, /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x64, 0x80, 0x80, 0x82, 0x82, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 0x00, 0x0f, 0x05, 0x00, 0x00, 0x80, 0x06, 0x00, /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0x00, 0x00, 0x00, 0xff, 0x8f, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0x88, 0x88, 0xc0, 0x00, 0x20, 0x64, 0xa8, 0xec, /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x31, 0x75, 0xb9, 0xfd, 0x00, 0x00, 0x88, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 0x88, 0x11, 0x00, 0x88, 0x88, 0x00, /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 *tbl_tw2815_common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) tbl_ntsc_tw2815_common[0x06] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Horizontal Delay Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tbl_ntsc_tw2815_common[0x02] = DEFAULT_HDELAY_NTSC & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tbl_ntsc_tw2815_common[0x06] |= 0x03 & (DEFAULT_HDELAY_NTSC >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Horizontal Active Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) tbl_ntsc_tw2815_common[0x03] = DEFAULT_HACTIVE_NTSC & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) tbl_ntsc_tw2815_common[0x06] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ((0x03 & (DEFAULT_HACTIVE_NTSC >> 8)) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Vertical Delay Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) tbl_ntsc_tw2815_common[0x04] = DEFAULT_VDELAY_NTSC & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tbl_ntsc_tw2815_common[0x06] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ((0x01 & (DEFAULT_VDELAY_NTSC >> 8)) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Vertical Active Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) tbl_ntsc_tw2815_common[0x05] = DEFAULT_VACTIVE_NTSC & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) tbl_ntsc_tw2815_common[0x06] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ((0x01 & (DEFAULT_VACTIVE_NTSC >> 8)) << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) tbl_pal_tw2815_common[0x06] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Horizontal Delay Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) tbl_pal_tw2815_common[0x02] = DEFAULT_HDELAY_PAL & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) tbl_pal_tw2815_common[0x06] |= 0x03 & (DEFAULT_HDELAY_PAL >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Horizontal Active Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) tbl_pal_tw2815_common[0x03] = DEFAULT_HACTIVE_PAL & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) tbl_pal_tw2815_common[0x06] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ((0x03 & (DEFAULT_HACTIVE_PAL >> 8)) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Vertical Delay Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) tbl_pal_tw2815_common[0x04] = DEFAULT_VDELAY_PAL & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) tbl_pal_tw2815_common[0x06] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ((0x01 & (DEFAULT_VDELAY_PAL >> 8)) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Vertical Active Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) tbl_pal_tw2815_common[0x05] = DEFAULT_VACTIVE_PAL & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) tbl_pal_tw2815_common[0x06] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ((0x01 & (DEFAULT_VACTIVE_PAL >> 8)) << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) tbl_tw2815_common =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) (solo_dev->video_type == SOLO_VO_FMT_TYPE_NTSC) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) tbl_ntsc_tw2815_common : tbl_pal_tw2815_common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Dual ITU-R BT.656 format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) tbl_tw2815_common[0x0d] |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Audio configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) tbl_tw2815_sfr[0x62 - 0x40] &= ~(3 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (solo_dev->nr_chans == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tbl_tw2815_sfr[0x63 - 0x40] |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tbl_tw2815_sfr[0x62 - 0x40] |= 3 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } else if (solo_dev->nr_chans == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) tbl_tw2815_sfr[0x63 - 0x40] |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (dev_addr == TW_CHIP_OFFSET_ADDR(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) tbl_tw2815_sfr[0x62 - 0x40] |= 1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) tbl_tw2815_sfr[0x62 - 0x40] |= 2 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } else if (solo_dev->nr_chans == 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) tbl_tw2815_sfr[0x63 - 0x40] |= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (dev_addr == TW_CHIP_OFFSET_ADDR(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tbl_tw2815_sfr[0x62 - 0x40] |= 1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) else if (dev_addr == TW_CHIP_OFFSET_ADDR(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) tbl_tw2815_sfr[0x62 - 0x40] |= 0 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) else if (dev_addr == TW_CHIP_OFFSET_ADDR(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) tbl_tw2815_sfr[0x62 - 0x40] |= 0 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) else if (dev_addr == TW_CHIP_OFFSET_ADDR(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) tbl_tw2815_sfr[0x62 - 0x40] |= 2 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Output mode of R_ADATM pin (0 mixing, 1 record) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* tbl_tw2815_sfr[0x63 - 0x40] |= 0 << 2; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* 8KHz, used to be 16KHz, but changed for remote client compat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) tbl_tw2815_sfr[0x62 - 0x40] |= 0 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) tbl_tw2815_sfr[0x6c - 0x40] |= 0 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Playback of right channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) tbl_tw2815_sfr[0x6c - 0x40] |= 1 << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Reserved value (XXX ??) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tbl_tw2815_sfr[0x5c - 0x40] |= 1 << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Analog output gain and mix ratio playback on full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) tbl_tw2815_sfr[0x70 - 0x40] |= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Select playback audio and mute all except */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) tbl_tw2815_sfr[0x71 - 0x40] |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) tbl_tw2815_sfr[0x6d - 0x40] |= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* End of audio configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) for (ch = 0; ch < 4; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tbl_tw2815_common[0x0d] &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) switch (ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) tbl_tw2815_common[0x0d] |= 0x21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) tbl_tw2815_common[0x0d] |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) tbl_tw2815_common[0x0d] |= 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) tbl_tw2815_common[0x0d] |= 0x22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) for (i = 0; i < 0x0f; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (i == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) continue; /* read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) solo_i2c_writebyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_addr, (ch * 0x10) + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) tbl_tw2815_common[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) for (i = 0x40; i < 0x76; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Skip read-only and nop registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (i == 0x40 || i == 0x59 || i == 0x5a ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) i == 0x5d || i == 0x5e || i == 0x5f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) solo_i2c_writebyte(solo_dev, SOLO_I2C_TW, dev_addr, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) tbl_tw2815_sfr[i - 0x40]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define FIRST_ACTIVE_LINE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define LAST_ACTIVE_LINE 0x0102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static void saa712x_write_regs(struct solo_dev *dev, const u8 *vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int start, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) for (; start < n; start++, vals++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Skip read-only registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) switch (start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* case 0x00 ... 0x25: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case 0x2e ... 0x37:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case 0x60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case 0x7d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) solo_i2c_writebyte(dev, SOLO_I2C_SAA, 0x46, start, *vals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SAA712x_reg7c (0x80 | ((LAST_ACTIVE_LINE & 0x100) >> 2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) | ((FIRST_ACTIVE_LINE & 0x100) >> 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void saa712x_setup(struct solo_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) const int reg_start = 0x26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const u8 saa7128_regs_ntsc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* :0x26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0x0d, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* :0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0x59, 0x1d, 0x75, 0x3f, 0x06, 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* :0x2e XXX: read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* :0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 0x1a, 0x1a, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* :0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 0x00, 0x00, 0x00, 0x68, 0x10, 0x97, 0x4c, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x9b, 0x93, 0x9f, 0xff, 0x7c, 0x34, 0x3f, 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* :0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0x3f, 0x83, 0x83, 0x80, 0x0d, 0x0f, 0xc3, 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 0x02, 0x80, 0x71, 0x77, 0xa7, 0x67, 0x66, 0x2e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* :0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0x7b, 0x11, 0x4f, 0x1f, 0x7c, 0xf0, 0x21, 0x77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0x41, 0x88, 0x41, 0x52, 0xed, 0x10, 0x10, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* :0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0x41, 0xc3, 0x00, 0x3e, 0xb8, 0x02, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0x00, 0x00, FIRST_ACTIVE_LINE, LAST_ACTIVE_LINE & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) SAA712x_reg7c, 0x00, 0xff, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }, saa7128_regs_pal[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* :0x26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 0x0d, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* :0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0xe1, 0x1d, 0x75, 0x3f, 0x06, 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* :0x2e XXX: read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* :0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 0x1a, 0x1a, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* :0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0x00, 0x00, 0x00, 0x68, 0x10, 0x97, 0x4c, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0x9b, 0x93, 0x9f, 0xff, 0x7c, 0x34, 0x3f, 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* :0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 0x3f, 0x83, 0x83, 0x80, 0x0d, 0x0f, 0xc3, 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 0x02, 0x80, 0x0f, 0x77, 0xa7, 0x67, 0x66, 0x2e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* :0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 0x7b, 0x02, 0x35, 0xcb, 0x8a, 0x09, 0x2a, 0x77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 0x41, 0x88, 0x41, 0x52, 0xf1, 0x10, 0x20, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* :0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 0x41, 0xc3, 0x00, 0x3e, 0xb8, 0x02, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0x00, 0x00, 0x12, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) SAA712x_reg7c | 0x40, 0x00, 0xff, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (dev->video_type == SOLO_VO_FMT_TYPE_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) saa712x_write_regs(dev, saa7128_regs_pal, reg_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) sizeof(saa7128_regs_pal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) saa712x_write_regs(dev, saa7128_regs_ntsc, reg_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sizeof(saa7128_regs_ntsc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int solo_tw28_init(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) solo_dev->tw28_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Detect techwell chip type(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) for (i = 0; i < solo_dev->nr_chans / 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) value = solo_i2c_readbyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) TW_CHIP_OFFSET_ADDR(i), 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) switch (value >> 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case 0x18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) solo_dev->tw2865 |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) solo_dev->tw28_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case 0x0c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case 0x0d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) solo_dev->tw2864 |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) solo_dev->tw28_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) value = solo_i2c_readbyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) TW_CHIP_OFFSET_ADDR(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0x59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if ((value >> 3) == 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) solo_dev->tw2815 |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) solo_dev->tw28_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (solo_dev->tw28_cnt != (solo_dev->nr_chans >> 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_err(&solo_dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "Could not initialize any techwell chips\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) saa712x_setup(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) for (i = 0; i < solo_dev->tw28_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if ((solo_dev->tw2865 & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) tw2865_setup(solo_dev, TW_CHIP_OFFSET_ADDR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else if ((solo_dev->tw2864 & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tw2864_setup(solo_dev, TW_CHIP_OFFSET_ADDR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) tw2815_setup(solo_dev, TW_CHIP_OFFSET_ADDR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * We accessed the video status signal in the Techwell chip through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * iic/i2c because the video status reported by register REG_VI_STATUS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * (address 0x012C) of the SOLO6010 chip doesn't give the correct video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * status signal values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int tw28_get_video_status(struct solo_dev *solo_dev, u8 ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u8 val, chip_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Get the right chip and on-chip channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) chip_num = ch / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ch %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) val = tw_readbyte(solo_dev, chip_num, TW286x_AV_STAT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) TW_AV_STAT_ADDR) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return val & (1 << ch) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Status of audio from up to 4 techwell chips are combined into 1 variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * See techwell datasheet for details. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u16 tw28_get_audio_status(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u16 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) for (i = 0; i < solo_dev->tw28_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) val = (tw_readbyte(solo_dev, i, TW286x_AV_STAT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) TW_AV_STAT_ADDR) & 0xf0) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) status |= val << (i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) bool tw28_has_sharpness(struct solo_dev *solo_dev, u8 ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return is_tw286x(solo_dev, ch / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int tw28_set_ctrl_val(struct solo_dev *solo_dev, u32 ctrl, u8 ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) s32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) char sval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u8 chip_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Get the right chip and on-chip channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) chip_num = ch / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ch %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (val > 255 || val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) switch (ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case V4L2_CID_SHARPNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Only 286x has sharpness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (is_tw286x(solo_dev, chip_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u8 v = solo_i2c_readbyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) TW_CHIP_OFFSET_ADDR(chip_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) TW286x_SHARPNESS(chip_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) v &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) v |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) solo_i2c_writebyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) TW_CHIP_OFFSET_ADDR(chip_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) TW286x_SHARPNESS(chip_num), v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (is_tw286x(solo_dev, chip_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) sval = val - 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) sval = (char)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) tw_writebyte(solo_dev, chip_num, TW286x_HUE_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) TW_HUE_ADDR(ch), sval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* 286x chips have a U and V component for saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (is_tw286x(solo_dev, chip_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) solo_i2c_writebyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) TW_CHIP_OFFSET_ADDR(chip_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) TW286x_SATURATIONU_ADDR(ch), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) tw_writebyte(solo_dev, chip_num, TW286x_SATURATIONV_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) TW_SATURATION_ADDR(ch), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) tw_writebyte(solo_dev, chip_num, TW286x_CONTRAST_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) TW_CONTRAST_ADDR(ch), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (is_tw286x(solo_dev, chip_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) sval = val - 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) sval = (char)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) tw_writebyte(solo_dev, chip_num, TW286x_BRIGHTNESS_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) TW_BRIGHTNESS_ADDR(ch), sval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) int tw28_get_ctrl_val(struct solo_dev *solo_dev, u32 ctrl, u8 ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) s32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u8 rval, chip_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Get the right chip and on-chip channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) chip_num = ch / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ch %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) switch (ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) case V4L2_CID_SHARPNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Only 286x has sharpness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (is_tw286x(solo_dev, chip_num)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) rval = solo_i2c_readbyte(solo_dev, SOLO_I2C_TW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) TW_CHIP_OFFSET_ADDR(chip_num),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) TW286x_SHARPNESS(chip_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) *val = rval & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) rval = tw_readbyte(solo_dev, chip_num, TW286x_HUE_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) TW_HUE_ADDR(ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (is_tw286x(solo_dev, chip_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *val = (s32)((char)rval) + 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) *val = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) *val = tw_readbyte(solo_dev, chip_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) TW286x_SATURATIONU_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) TW_SATURATION_ADDR(ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) *val = tw_readbyte(solo_dev, chip_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) TW286x_CONTRAST_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) TW_CONTRAST_ADDR(ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) rval = tw_readbyte(solo_dev, chip_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) TW286x_BRIGHTNESS_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) TW_BRIGHTNESS_ADDR(ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (is_tw286x(solo_dev, chip_num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *val = (s32)((char)rval) + 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) *val = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * For audio output volume, the output channel is only 1. In this case we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * don't need to offset TW_CHIP_OFFSET_ADDR. The TW_CHIP_OFFSET_ADDR used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * is the base address of the techwell chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) void tw2815_Set_AudioOutVol(struct solo_dev *solo_dev, unsigned int u_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) unsigned int chip_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) chip_num = (solo_dev->nr_chans - 1) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) val = tw_readbyte(solo_dev, chip_num, TW286x_AUDIO_OUTPUT_VOL_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) TW_AUDIO_OUTPUT_VOL_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u_val = (val & 0x0f) | (u_val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) tw_writebyte(solo_dev, chip_num, TW286x_AUDIO_OUTPUT_VOL_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) TW_AUDIO_OUTPUT_VOL_ADDR, u_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u8 tw28_get_audio_gain(struct solo_dev *solo_dev, u8 ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u8 chip_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Get the right chip and on-chip channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) chip_num = ch / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ch %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) val = tw_readbyte(solo_dev, chip_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) TW286x_AUDIO_INPUT_GAIN_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) TW_AUDIO_INPUT_GAIN_ADDR(ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return (ch % 2) ? (val >> 4) : (val & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) void tw28_set_audio_gain(struct solo_dev *solo_dev, u8 ch, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u8 old_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u8 chip_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Get the right chip and on-chip channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) chip_num = ch / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ch %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) old_val = tw_readbyte(solo_dev, chip_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) TW286x_AUDIO_INPUT_GAIN_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) TW_AUDIO_INPUT_GAIN_ADDR(ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) val = (old_val & ((ch % 2) ? 0x0f : 0xf0)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ((ch % 2) ? (val << 4) : val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) tw_writebyte(solo_dev, chip_num, TW286x_AUDIO_INPUT_GAIN_ADDR(ch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) TW_AUDIO_INPUT_GAIN_ADDR(ch), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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