^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Original author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ben Collins <bcollins@ubuntu.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Additional work by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * John Brooks <john.brooks@bluecherry.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __SOLO6X10_REGISTERS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __SOLO6X10_REGISTERS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "solo6x10-offsets.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Global 6010 system configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SOLO_SYS_CFG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SOLO_SYS_CFG_FOUT_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SOLO_SYS_CFG_PLL_BYPASS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SOLO_SYS_CFG_PLL_PWDN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SOLO_SYS_CFG_OUTDIV(__n) (((__n) & 0x003) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SOLO_SYS_CFG_FEEDBACKDIV(__n) (((__n) & 0x1ff) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SOLO_SYS_CFG_INPUTDIV(__n) (((__n) & 0x01f) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SOLO_SYS_CFG_CLOCK_DIV 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SOLO_SYS_CFG_NCLK_DELAY(__n) (((__n) & 0x003) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SOLO_SYS_CFG_PCLK_DELAY(__n) (((__n) & 0x00f) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SOLO_SYS_CFG_SDRAM64BIT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SOLO_SYS_CFG_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SOLO_DMA_CTRL 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* 0=16/32MB, 1=32/64MB, 2=64/128MB, 3=128/256MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SOLO_DMA_CTRL_SDRAM_SIZE(n) ((n)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SOLO_DMA_CTRL_SDRAM_CLK_INVERT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SOLO_DMA_CTRL_STROBE_SELECT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SOLO_DMA_CTRL_READ_DATA_SELECT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SOLO_DMA_CTRL_READ_CLK_SELECT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Some things we set in this are undocumented. Why Softlogic?!?! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SOLO_DMA_CTRL1 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SOLO_SYS_VCLK 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SOLO_VCLK_INVERT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* 0=sys_clk/4, 1=sys_clk/2, 2=clk_in/2 of system input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SOLO_VCLK_SELECT(n) ((n)<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SOLO_VCLK_VIN1415_DELAY(n) ((n)<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SOLO_VCLK_VIN1213_DELAY(n) ((n)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SOLO_VCLK_VIN1011_DELAY(n) ((n)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SOLO_VCLK_VIN0809_DELAY(n) ((n)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SOLO_VCLK_VIN0607_DELAY(n) ((n)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SOLO_VCLK_VIN0405_DELAY(n) ((n)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SOLO_VCLK_VIN0203_DELAY(n) ((n)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SOLO_VCLK_VIN0001_DELAY(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SOLO_IRQ_STAT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SOLO_IRQ_MASK 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SOLO_IRQ_P2M(n) BIT((n) + 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SOLO_IRQ_GPIO BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SOLO_IRQ_VIDEO_LOSS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SOLO_IRQ_VIDEO_IN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SOLO_IRQ_MOTION BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SOLO_IRQ_ATA_CMD BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SOLO_IRQ_ATA_DIR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SOLO_IRQ_PCI_ERR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SOLO_IRQ_PS2_1 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SOLO_IRQ_PS2_0 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SOLO_IRQ_SPI BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SOLO_IRQ_IIC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SOLO_IRQ_UART(n) BIT((n) + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SOLO_IRQ_G723 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SOLO_IRQ_DECODER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SOLO_IRQ_ENCODER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SOLO_CHIP_OPTION 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SOLO_CHIP_ID_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SOLO_PLL_CONFIG 0x0020 /* 6110 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SOLO_EEPROM_CTRL 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SOLO_EEPROM_ACCESS_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SOLO_EEPROM_CS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SOLO_EEPROM_CLK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SOLO_EEPROM_DO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SOLO_EEPROM_DI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SOLO_EEPROM_ENABLE (SOLO_EEPROM_ACCESS_EN | SOLO_EEPROM_CS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SOLO_PCI_ERR 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SOLO_PCI_ERR_FATAL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SOLO_PCI_ERR_PARITY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SOLO_PCI_ERR_TARGET 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SOLO_PCI_ERR_TIMEOUT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SOLO_PCI_ERR_P2M 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SOLO_PCI_ERR_ATA 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SOLO_PCI_ERR_P2M_DESC 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SOLO_PCI_ERR_FSM0(__s) (((__s) >> 16) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SOLO_PCI_ERR_FSM1(__s) (((__s) >> 20) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SOLO_PCI_ERR_FSM2(__s) (((__s) >> 24) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SOLO_P2M_BASE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SOLO_P2M_CONFIG(n) (0x0080 + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SOLO_P2M_DMA_INTERVAL(n) ((n)<<6)/* N*32 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SOLO_P2M_CSC_BYTE_REORDER BIT(5) /* BGR -> RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* 0:r=[14:10] g=[9:5] b=[4:0], 1:r=[15:11] g=[10:5] b=[4:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SOLO_P2M_CSC_16BIT_565 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SOLO_P2M_UV_SWAP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SOLO_P2M_PCI_MASTER_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SOLO_P2M_DESC_INTR_OPT BIT(1) /* 1:Empty, 0:Each */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SOLO_P2M_DESC_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SOLO_P2M_DES_ADR(n) (0x0084 + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SOLO_P2M_DESC_ID(n) (0x0088 + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SOLO_P2M_UPDATE_ID(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SOLO_P2M_STATUS(n) (0x008C + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SOLO_P2M_COMMAND_DONE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SOLO_P2M_CURRENT_ID(stat) (0xff & (stat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SOLO_P2M_CONTROL(n) (0x0090 + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SOLO_P2M_PCI_INC(n) ((n)<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SOLO_P2M_REPEAT(n) ((n)<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* 0:512, 1:256, 2:128, 3:64, 4:32, 5:128(2page) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SOLO_P2M_BURST_SIZE(n) ((n)<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SOLO_P2M_BURST_512 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SOLO_P2M_BURST_256 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SOLO_P2M_BURST_128 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SOLO_P2M_BURST_64 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SOLO_P2M_BURST_32 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SOLO_P2M_CSC_16BIT BIT(6) /* 0:24bit, 1:16bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 0:Y[0]<-0(OFF), 1:Y[0]<-1(ON), 2:Y[0]<-G[0], 3:Y[0]<-Bit[15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SOLO_P2M_ALPHA_MODE(n) ((n)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SOLO_P2M_CSC_ON BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SOLO_P2M_INTERRUPT_REQ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SOLO_P2M_WRITE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SOLO_P2M_TRANS_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SOLO_P2M_EXT_CFG(n) (0x0094 + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SOLO_P2M_EXT_INC(n) ((n)<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SOLO_P2M_COPY_SIZE(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SOLO_P2M_TAR_ADR(n) (0x0098 + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SOLO_P2M_EXT_ADR(n) (0x009C + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SOLO_P2M_BUFFER(i) (0x2000 + ((i)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SOLO_VI_CH_SWITCH_0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SOLO_VI_CH_SWITCH_1 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SOLO_VI_CH_SWITCH_2 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SOLO_VI_CH_ENA 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SOLO_VI_CH_FORMAT 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SOLO_VI_FD_SEL_MASK(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SOLO_VI_PROG_MASK(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SOLO_VI_FMT_CFG 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SOLO_VI_FMT_CHECK_VCOUNT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SOLO_VI_FMT_CHECK_HCOUNT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SOLO_VI_FMT_TEST_SIGNAL BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SOLO_VI_PAGE_SW 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SOLO_FI_INV_DISP_LIVE(n) ((n)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SOLO_FI_INV_DISP_OUT(n) ((n)<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SOLO_DISP_SYNC_FI(n) ((n)<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SOLO_PIP_PAGE_ADD(n) ((n)<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SOLO_NORMAL_PAGE_ADD(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SOLO_VI_ACT_I_P 0x011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SOLO_VI_ACT_I_S 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SOLO_VI_ACT_P 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SOLO_VI_FI_INVERT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SOLO_VI_H_START(n) ((n)<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SOLO_VI_V_START(n) ((n)<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SOLO_VI_V_STOP(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SOLO_VI_STATUS0 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SOLO_VI_STATUS0_PAGE(__n) ((__n) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SOLO_VI_STATUS1 0x012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* XXX: Might be better off in kernel level disp.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DISP_PAGE(stat) ((stat) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SOLO_VI_PB_CONFIG 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SOLO_VI_PB_USER_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SOLO_VI_PB_PAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SOLO_VI_PB_RANGE_HV 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SOLO_VI_PB_HSIZE(h) ((h)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SOLO_VI_PB_VSIZE(v) ((v)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SOLO_VI_PB_ACT_H 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SOLO_VI_PB_HSTART(n) ((n)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SOLO_VI_PB_HSTOP(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SOLO_VI_PB_ACT_V 0x013C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SOLO_VI_PB_VSTART(n) ((n)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SOLO_VI_PB_VSTOP(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SOLO_VI_MOSAIC(ch) (0x0140 + ((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SOLO_VI_MOSAIC_SX(x) ((x)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SOLO_VI_MOSAIC_EX(x) ((x)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SOLO_VI_MOSAIC_SY(x) ((x)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SOLO_VI_MOSAIC_EY(x) ((x)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SOLO_VI_WIN_CTRL0(ch) (0x0180 + ((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SOLO_VI_WIN_CTRL1(ch) (0x01C0 + ((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SOLO_VI_WIN_CHANNEL(n) ((n)<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SOLO_VI_WIN_PIP(n) ((n)<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SOLO_VI_WIN_SCALE(n) ((n)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SOLO_VI_WIN_SX(x) ((x)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SOLO_VI_WIN_EX(x) ((x)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SOLO_VI_WIN_SY(x) ((x)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SOLO_VI_WIN_EY(x) ((x)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SOLO_VI_WIN_ON(ch) (0x0200 + ((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SOLO_VI_WIN_SW 0x0240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SOLO_VI_WIN_LIVE_AUTO_MUTE 0x0244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SOLO_VI_MOT_ADR 0x0260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SOLO_VI_MOTION_EN(mask) ((mask)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SOLO_VI_MOT_CTRL 0x0264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SOLO_VI_MOTION_FRAME_COUNT(n) ((n)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SOLO_VI_MOTION_SAMPLE_LENGTH(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SOLO_VI_MOTION_INTR_START_STOP BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SOLO_VI_MOTION_FREEZE_DATA BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SOLO_VI_MOTION_SAMPLE_COUNT(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SOLO_VI_MOT_CLEAR 0x0268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SOLO_VI_MOT_STATUS 0x026C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SOLO_VI_MOTION_CNT(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SOLO_VI_MOTION_BORDER 0x0270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SOLO_VI_MOTION_BAR 0x0274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SOLO_VI_MOTION_Y_SET BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SOLO_VI_MOTION_Y_ADD BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SOLO_VI_MOTION_CB_SET BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SOLO_VI_MOTION_CB_ADD BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SOLO_VI_MOTION_CR_SET BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SOLO_VI_MOTION_CR_ADD BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SOLO_VI_MOTION_Y_VALUE(v) ((v)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SOLO_VI_MOTION_CB_VALUE(v) ((v)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SOLO_VI_MOTION_CR_VALUE(v) ((v)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SOLO_VO_FMT_ENC 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SOLO_VO_SCAN_MODE_PROGRESSIVE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SOLO_VO_FMT_TYPE_PAL BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SOLO_VO_FMT_TYPE_NTSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SOLO_VO_USER_SET BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SOLO_VO_FI_CHANGE BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SOLO_VO_USER_COLOR_SET_VSYNC BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SOLO_VO_USER_COLOR_SET_HSYNC BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SOLO_VO_USER_COLOR_SET_NAH BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SOLO_VO_USER_COLOR_SET_NAV BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SOLO_VO_NA_COLOR_Y(Y) ((Y)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SOLO_VO_NA_COLOR_CB(CB) (((CB)/16)<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SOLO_VO_NA_COLOR_CR(CR) (((CR)/16)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SOLO_VO_ACT_H 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SOLO_VO_H_BLANK(n) ((n)<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SOLO_VO_H_START(n) ((n)<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SOLO_VO_H_STOP(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SOLO_VO_ACT_V 0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SOLO_VO_V_BLANK(n) ((n)<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SOLO_VO_V_START(n) ((n)<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SOLO_VO_V_STOP(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SOLO_VO_RANGE_HV 0x030C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SOLO_VO_SYNC_INVERT BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SOLO_VO_HSYNC_INVERT BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SOLO_VO_VSYNC_INVERT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SOLO_VO_H_LEN(n) ((n)<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SOLO_VO_V_LEN(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SOLO_VO_DISP_CTRL 0x0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SOLO_VO_DISP_ON BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SOLO_VO_DISP_ERASE_COUNT(n) ((n&0xf)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SOLO_VO_DISP_DOUBLE_SCAN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SOLO_VO_DISP_SINGLE_PAGE BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SOLO_VO_DISP_BASE(n) (((n)>>16) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SOLO_VO_DISP_ERASE 0x0314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SOLO_VO_DISP_ERASE_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SOLO_VO_ZOOM_CTRL 0x0318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SOLO_VO_ZOOM_VER_ON BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SOLO_VO_ZOOM_HOR_ON BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SOLO_VO_ZOOM_V_COMP BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SOLO_VO_ZOOM_SX(h) (((h)/2)<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SOLO_VO_ZOOM_SY(v) (((v)/2)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SOLO_VO_FREEZE_CTRL 0x031C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SOLO_VO_FREEZE_ON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SOLO_VO_FREEZE_INTERPOLATION BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SOLO_VO_BKG_COLOR 0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SOLO_BG_Y(y) ((y)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SOLO_BG_U(u) ((u)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SOLO_BG_V(v) ((v)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SOLO_VO_DEINTERLACE 0x0324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SOLO_VO_DEINTERLACE_THRESHOLD(n) ((n)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SOLO_VO_DEINTERLACE_EDGE_VALUE(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SOLO_VO_BORDER_LINE_COLOR 0x0330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SOLO_VO_BORDER_FILL_COLOR 0x0334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SOLO_VO_BORDER_LINE_MASK 0x0338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SOLO_VO_BORDER_FILL_MASK 0x033c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SOLO_VO_BORDER_X(n) (0x0340+((n)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SOLO_VO_BORDER_Y(n) (0x0354+((n)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SOLO_VO_CELL_EXT_SET 0x0368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SOLO_VO_CELL_EXT_START 0x036c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SOLO_VO_CELL_EXT_STOP 0x0370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SOLO_VO_CELL_EXT_SET2 0x0374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SOLO_VO_CELL_EXT_START2 0x0378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SOLO_VO_CELL_EXT_STOP2 0x037c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SOLO_VO_RECTANGLE_CTRL(n) (0x0368+((n)*12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SOLO_VO_RECTANGLE_START(n) (0x036c+((n)*12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SOLO_VO_RECTANGLE_STOP(n) (0x0370+((n)*12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SOLO_VO_CURSOR_POS (0x0380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SOLO_VO_CURSOR_CLR (0x0384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SOLO_VO_CURSOR_CLR2 (0x0388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SOLO_VO_CURSOR_MASK(id) (0x0390+((id)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SOLO_VO_EXPANSION(id) (0x0250+((id)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SOLO_OSG_CONFIG 0x03E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SOLO_VO_OSG_ON BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SOLO_VO_OSG_COLOR_MUTE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SOLO_VO_OSG_ALPHA_RATE(n) ((n)<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SOLO_VO_OSG_ALPHA_BG_RATE(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SOLO_VO_OSG_BASE(offset) (((offset)>>16)&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SOLO_OSG_ERASE 0x03E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SOLO_OSG_ERASE_ON (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SOLO_OSG_ERASE_OFF (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SOLO_VO_OSG_BLINK 0x03E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SOLO_VO_OSG_BLINK_ON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SOLO_VO_OSG_BLINK_INTREVAL18 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SOLO_CAP_BASE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SOLO_CAP_MAX_PAGE(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SOLO_CAP_BASE_ADDR(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SOLO_CAP_BTW 0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SOLO_CAP_PROG_BANDWIDTH(n) ((n)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SOLO_CAP_MAX_BANDWIDTH(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SOLO_DIM_SCALE1 0x0408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SOLO_DIM_SCALE2 0x040C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SOLO_DIM_SCALE3 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SOLO_DIM_SCALE4 0x0414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SOLO_DIM_SCALE5 0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SOLO_DIM_V_MB_NUM_FRAME(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SOLO_DIM_V_MB_NUM_FIELD(n) ((n)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SOLO_DIM_H_MB_NUM(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SOLO_DIM_PROG 0x041C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SOLO_CAP_STATUS 0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SOLO_CAP_CH_SCALE(ch) (0x0440+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SOLO_CAP_CH_COMP_ENA_E(ch) (0x0480+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SOLO_CAP_CH_INTV(ch) (0x04C0+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SOLO_CAP_CH_INTV_E(ch) (0x0500+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SOLO_VE_CFG0 0x0610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SOLO_VE_TWO_PAGE_MODE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SOLO_VE_INTR_CTRL(n) ((n)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SOLO_VE_BLOCK_SIZE(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SOLO_VE_BLOCK_BASE(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SOLO_VE_CFG1 0x0614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SOLO_VE_BYTE_ALIGN(n) ((n)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SOLO_VE_INSERT_INDEX BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SOLO_VE_MOTION_MODE(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SOLO_VE_MOTION_BASE(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SOLO_VE_MPEG_SIZE_H(n) ((n)<<28) /* 6110 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SOLO_VE_JPEG_SIZE_H(n) ((n)<<20) /* 6110 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SOLO_VE_INSERT_INDEX_JPEG BIT(19) /* 6110 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SOLO_VE_WMRK_POLY 0x061C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SOLO_VE_VMRK_INIT_KEY 0x0620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SOLO_VE_WMRK_STRL 0x0624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SOLO_VE_ENCRYP_POLY 0x0628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SOLO_VE_ENCRYP_INIT 0x062C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SOLO_VE_ATTR 0x0630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SOLO_VE_LITTLE_ENDIAN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SOLO_COMP_ATTR_RN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SOLO_COMP_ATTR_FCODE(n) ((n)<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SOLO_COMP_TIME_INC(n) ((n)<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SOLO_COMP_TIME_WIDTH(n) ((n)<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SOLO_DCT_INTERVAL(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SOLO_VE_COMPT_MOT 0x0634 /* 6110 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SOLO_VE_STATE(n) (0x0640+((n)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SOLO_VE_JPEG_QP_TBL 0x0670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SOLO_VE_JPEG_QP_CH_L 0x0674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SOLO_VE_JPEG_QP_CH_H 0x0678
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SOLO_VE_JPEG_CFG 0x067C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SOLO_VE_JPEG_CTRL 0x0680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SOLO_VE_CODE_ENCRYPT 0x0684 /* 6110 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SOLO_VE_JPEG_CFG1 0x0688 /* 6110 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SOLO_VE_WMRK_ENABLE 0x068C /* 6110 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SOLO_VE_OSD_CH 0x0690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SOLO_VE_OSD_BASE 0x0694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SOLO_VE_OSD_CLR 0x0698
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SOLO_VE_OSD_OPT 0x069C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SOLO_VE_OSD_V_DOUBLE BIT(16) /* 6110 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SOLO_VE_OSD_H_SHADOW BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SOLO_VE_OSD_V_SHADOW BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SOLO_VE_OSD_H_OFFSET(n) ((n & 0x7f)<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SOLO_VE_OSD_V_OFFSET(n) (n & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SOLO_VE_CH_INTL(ch) (0x0700+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SOLO_VE_CH_MOT(ch) (0x0740+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define SOLO_VE_CH_QP(ch) (0x0780+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SOLO_VE_CH_QP_E(ch) (0x07C0+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SOLO_VE_CH_GOP(ch) (0x0800+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SOLO_VE_CH_GOP_E(ch) (0x0840+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SOLO_VE_CH_REF_BASE(ch) (0x0880+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SOLO_VE_CH_REF_BASE_E(ch) (0x08C0+((ch)*4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SOLO_VE_MPEG4_QUE(n) (0x0A00+((n)*8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SOLO_VE_JPEG_QUE(n) (0x0A04+((n)*8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SOLO_VD_CFG0 0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SOLO_VD_CFG_NO_WRITE_NO_WINDOW BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SOLO_VD_CFG_BUSY_WIAT_CODE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SOLO_VD_CFG_BUSY_WIAT_REF BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SOLO_VD_CFG_BUSY_WIAT_RES BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SOLO_VD_CFG_BUSY_WIAT_MS BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SOLO_VD_CFG_SINGLE_MODE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SOLO_VD_CFG_SCAL_MANUAL BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SOLO_VD_CFG_USER_PAGE_CTRL BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SOLO_VD_CFG_LITTLE_ENDIAN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SOLO_VD_CFG_START_FI BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SOLO_VD_CFG_ERR_LOCK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SOLO_VD_CFG_ERR_INT_ENA BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SOLO_VD_CFG_TIME_WIDTH(n) ((n)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SOLO_VD_CFG_DCT_INTERVAL(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SOLO_VD_CFG1 0x0904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SOLO_VD_DEINTERLACE 0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SOLO_VD_DEINTERLACE_THRESHOLD(n) ((n)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SOLO_VD_DEINTERLACE_EDGE_VALUE(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SOLO_VD_CODE_ADR 0x090C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SOLO_VD_CTRL 0x0910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SOLO_VD_OPER_ON BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SOLO_VD_MAX_ITEM(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SOLO_VD_STATUS0 0x0920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SOLO_VD_STATUS0_INTR_ACK BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SOLO_VD_STATUS0_INTR_EMPTY BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SOLO_VD_STATUS0_INTR_ERR BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SOLO_VD_STATUS1 0x0924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SOLO_VD_IDX0 0x0930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SOLO_VD_IDX_INTERLACE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SOLO_VD_IDX_CHANNEL(n) ((n)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SOLO_VD_IDX_SIZE(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SOLO_VD_IDX1 0x0934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SOLO_VD_IDX_SRC_SCALE(n) ((n)<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SOLO_VD_IDX_WINDOW(n) ((n)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define SOLO_VD_IDX_DEINTERLACE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SOLO_VD_IDX_H_BLOCK(n) ((n)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SOLO_VD_IDX_V_BLOCK(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SOLO_VD_IDX2 0x0938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SOLO_VD_IDX_REF_BASE_SIDE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define SOLO_VD_IDX_REF_BASE(n) (((n)>>16)&0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SOLO_VD_IDX3 0x093C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define SOLO_VD_IDX_DISP_SCALE(n) ((n)<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define SOLO_VD_IDX_INTERLACE_WR BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define SOLO_VD_IDX_INTERPOL BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define SOLO_VD_IDX_HOR2X BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define SOLO_VD_IDX_OFFSET_X(n) ((n)<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SOLO_VD_IDX_OFFSET_Y(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SOLO_VD_IDX4 0x0940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SOLO_VD_IDX_DEC_WR_PAGE(n) ((n)<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SOLO_VD_IDX_DISP_RD_PAGE(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SOLO_VD_WR_PAGE(n) (0x03F0 + ((n) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SOLO_GPIO_CONFIG_0 0x0B00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SOLO_GPIO_CONFIG_1 0x0B04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SOLO_GPIO_DATA_OUT 0x0B08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SOLO_GPIO_DATA_IN 0x0B0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SOLO_GPIO_INT_ACK_STA 0x0B10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define SOLO_GPIO_INT_ENA 0x0B14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SOLO_GPIO_INT_CFG_0 0x0B18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SOLO_GPIO_INT_CFG_1 0x0B1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SOLO_IIC_CFG 0x0B20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define SOLO_IIC_ENABLE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SOLO_IIC_PRESCALE(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SOLO_IIC_CTRL 0x0B24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SOLO_IIC_AUTO_CLEAR BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SOLO_IIC_STATE_RX_ACK BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define SOLO_IIC_STATE_BUSY BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define SOLO_IIC_STATE_SIG_ERR BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SOLO_IIC_STATE_TRNS BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SOLO_IIC_CH_SET(n) ((n)<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SOLO_IIC_ACK_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SOLO_IIC_START BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SOLO_IIC_STOP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SOLO_IIC_READ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SOLO_IIC_WRITE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SOLO_IIC_TXD 0x0B28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SOLO_IIC_RXD 0x0B2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * UART REGISTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SOLO_UART_CONTROL(n) (0x0BA0 + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SOLO_UART_CLK_DIV(n) ((n)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SOLO_MODEM_CTRL_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SOLO_PARITY_ERROR_DROP BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SOLO_IRQ_ERR_EN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SOLO_IRQ_RX_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SOLO_IRQ_TX_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SOLO_RX_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SOLO_TX_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SOLO_UART_HALF_DUPLEX BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SOLO_UART_LOOPBACK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SOLO_BAUDRATE_230400 ((0<<9)|(0<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SOLO_BAUDRATE_115200 ((0<<9)|(1<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SOLO_BAUDRATE_57600 ((0<<9)|(2<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SOLO_BAUDRATE_38400 ((0<<9)|(3<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SOLO_BAUDRATE_19200 ((0<<9)|(4<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SOLO_BAUDRATE_9600 ((0<<9)|(5<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SOLO_BAUDRATE_4800 ((0<<9)|(6<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define SOLO_BAUDRATE_2400 ((1<<9)|(6<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define SOLO_BAUDRATE_1200 ((2<<9)|(6<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define SOLO_BAUDRATE_300 ((3<<9)|(6<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SOLO_UART_DATA_BIT_8 (3<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define SOLO_UART_DATA_BIT_7 (2<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SOLO_UART_DATA_BIT_6 (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define SOLO_UART_DATA_BIT_5 (0<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define SOLO_UART_STOP_BIT_1 (0<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SOLO_UART_STOP_BIT_2 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define SOLO_UART_PARITY_NONE (0<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SOLO_UART_PARITY_EVEN (2<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SOLO_UART_PARITY_ODD (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define SOLO_UART_STATUS(n) (0x0BA4 + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SOLO_UART_CTS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SOLO_UART_RX_BUSY BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SOLO_UART_OVERRUN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SOLO_UART_FRAME_ERR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SOLO_UART_PARITY_ERR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SOLO_UART_TX_BUSY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define SOLO_UART_RX_BUFF_CNT(stat) (((stat)>>6) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define SOLO_UART_RX_BUFF_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define SOLO_UART_TX_BUFF_CNT(stat) (((stat)>>0) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define SOLO_UART_TX_BUFF_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define SOLO_UART_TX_DATA(n) (0x0BA8 + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define SOLO_UART_TX_DATA_PUSH BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define SOLO_UART_RX_DATA(n) (0x0BAC + ((n)*0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define SOLO_UART_RX_DATA_POP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SOLO_TIMER_CLOCK_NUM 0x0be0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define SOLO_TIMER_USEC 0x0be8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define SOLO_TIMER_SEC 0x0bec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define SOLO_TIMER_USEC_LSB 0x0d20 /* 6110 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SOLO_AUDIO_CONTROL 0x0D00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SOLO_AUDIO_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SOLO_AUDIO_MASTER_MODE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SOLO_AUDIO_I2S_MODE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define SOLO_AUDIO_I2S_LR_SWAP BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SOLO_AUDIO_I2S_8BIT BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define SOLO_AUDIO_I2S_MULTI(n) ((n)<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define SOLO_AUDIO_MIX_9TO0 BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define SOLO_AUDIO_DEC_9TO0_VOL(n) ((n)<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define SOLO_AUDIO_MIX_19TO10 BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SOLO_AUDIO_DEC_19TO10_VOL(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define SOLO_AUDIO_MODE(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define SOLO_AUDIO_SAMPLE 0x0D04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define SOLO_AUDIO_EE_MODE_ON BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define SOLO_AUDIO_EE_ENC_CH(ch) ((ch)<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define SOLO_AUDIO_BITRATE(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define SOLO_AUDIO_CLK_DIV(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SOLO_AUDIO_FDMA_INTR 0x0D08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define SOLO_AUDIO_FDMA_INTERVAL(n) ((n)<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SOLO_AUDIO_INTR_ORDER(n) ((n)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SOLO_AUDIO_FDMA_BASE(n) ((n)<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SOLO_AUDIO_EVOL_0 0x0D0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define SOLO_AUDIO_EVOL_1 0x0D10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define SOLO_AUDIO_EVOL(ch, value) ((value)<<((ch)%10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define SOLO_AUDIO_STA 0x0D14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Watchdog configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define SOLO_WATCHDOG 0x0be4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define SOLO_WATCHDOG_SET(status, sec) (status << 8 | (sec & 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #endif /* __SOLO6X10_REGISTERS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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