^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Original author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ben Collins <bcollins@ubuntu.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Additional work by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * John Brooks <john.brooks@bluecherry.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "solo6x10.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static int multi_p2m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) module_param(multi_p2m, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MODULE_PARM_DESC(multi_p2m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "Use multiple P2M DMA channels (default: no, 6010-only)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int desc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) module_param(desc_mode, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_PARM_DESC(desc_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "Allow use of descriptor mode DMA (default: no, 6010-only)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void *sys_addr, u32 ext_addr, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int repeat, u32 ext_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (WARN_ON_ONCE((unsigned long)sys_addr & 0x03))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (WARN_ON_ONCE(!size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) dma_addr = pci_map_single(solo_dev->pdev, sys_addr, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (pci_dma_mapping_error(solo_dev->pdev, dma_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ret = solo_p2m_dma_t(solo_dev, wr, dma_addr, ext_addr, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) repeat, ext_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pci_unmap_single(solo_dev->pdev, dma_addr, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) wr ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Mutex must be held for p2m_id before calling this!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int solo_p2m_dma_desc(struct solo_dev *solo_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct solo_p2m_desc *desc, dma_addr_t desc_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int desc_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct solo_p2m_dev *p2m_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int p2m_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Get next ID. According to Softlogic, 6110 has problems on !=0 P2M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (solo_dev->type != SOLO_DEV_6110 && multi_p2m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) p2m_id = atomic_inc_return(&solo_dev->p2m_count) % SOLO_NR_P2M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) p2m_dev = &solo_dev->p2m_dev[p2m_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (mutex_lock_interruptible(&p2m_dev->mutex))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reinit_completion(&p2m_dev->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) p2m_dev->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && desc_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* For 6010 with more than one desc, we can do a one-shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) p2m_dev->desc_count = p2m_dev->desc_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) config = solo_reg_read(solo_dev, SOLO_P2M_CONFIG(p2m_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) solo_reg_write(solo_dev, SOLO_P2M_DES_ADR(p2m_id), desc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) solo_reg_write(solo_dev, SOLO_P2M_DESC_ID(p2m_id), desc_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SOLO_P2M_DESC_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* For single descriptors and 6110, we need to run each desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) p2m_dev->desc_count = desc_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) p2m_dev->desc_idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) p2m_dev->descs = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(p2m_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) desc[1].dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(p2m_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) desc[1].ext_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(p2m_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) desc[1].cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) desc[1].ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) timeout = wait_for_completion_timeout(&p2m_dev->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) solo_dev->p2m_jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (WARN_ON_ONCE(p2m_dev->error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) else if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) solo_dev->p2m_timeouts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Don't write here for the no_desc_mode case, because config is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * We can't test no_desc_mode again, it might race. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mutex_unlock(&p2m_dev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dma_addr_t dma_addr, u32 ext_addr, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int repeat, u32 ext_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) WARN_ON_ONCE(dma_addr & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) WARN_ON_ONCE(!size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) desc->cfg = SOLO_P2M_COPY_SIZE(size >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) desc->ctrl = SOLO_P2M_BURST_SIZE(SOLO_P2M_BURST_256) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (wr ? SOLO_P2M_WRITE : 0) | SOLO_P2M_TRANS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (repeat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) desc->cfg |= SOLO_P2M_EXT_INC(ext_size >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) desc->ctrl |= SOLO_P2M_PCI_INC(size >> 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SOLO_P2M_REPEAT(repeat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) desc->dma_addr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) desc->ext_addr = ext_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dma_addr_t dma_addr, u32 ext_addr, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int repeat, u32 ext_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct solo_p2m_desc desc[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) solo_p2m_fill_desc(&desc[1], wr, dma_addr, ext_addr, size, repeat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ext_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* No need for desc_dma since we know it is a single-shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return solo_p2m_dma_desc(solo_dev, desc, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void solo_p2m_isr(struct solo_dev *solo_dev, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct solo_p2m_dev *p2m_dev = &solo_dev->p2m_dev[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct solo_p2m_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (p2m_dev->desc_count <= p2m_dev->desc_idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) complete(&p2m_dev->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Setup next descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) p2m_dev->desc_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) desc = &p2m_dev->descs[p2m_dev->desc_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(id), desc->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(id), desc->ext_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(id), desc->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), desc->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void solo_p2m_error_isr(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int err = solo_reg_read(solo_dev, SOLO_PCI_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct solo_p2m_dev *p2m_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!(err & (SOLO_PCI_ERR_P2M | SOLO_PCI_ERR_P2M_DESC)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i < SOLO_NR_P2M; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) p2m_dev = &solo_dev->p2m_dev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) p2m_dev->error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) complete(&p2m_dev->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void solo_p2m_exit(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for (i = 0; i < SOLO_NR_P2M; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) solo_irq_off(solo_dev, SOLO_IRQ_P2M(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int solo_p2m_test(struct solo_dev *solo_dev, int base, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 *wr_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 *rd_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int order = get_order(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) wr_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (wr_buf == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rd_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (rd_buf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) free_pages((unsigned long)wr_buf, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (i = 0; i < (size >> 3); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) *(wr_buf + i) = (i << 16) | (i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for (i = (size >> 3); i < (size >> 2); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *(wr_buf + i) = ~((i << 16) | (i + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) memset(rd_buf, 0x55, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (solo_p2m_dma(solo_dev, 1, wr_buf, base, size, 0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto test_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (solo_p2m_dma(solo_dev, 0, rd_buf, base, size, 0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) goto test_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for (i = 0; i < (size >> 2); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (*(wr_buf + i) != *(rd_buf + i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto test_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) test_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) free_pages((unsigned long)wr_buf, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) free_pages((unsigned long)rd_buf, order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int solo_p2m_init(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct solo_p2m_dev *p2m_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) for (i = 0; i < SOLO_NR_P2M; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) p2m_dev = &solo_dev->p2m_dev[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mutex_init(&p2m_dev->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) init_completion(&p2m_dev->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) solo_reg_write(solo_dev, SOLO_P2M_CONFIG(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SOLO_P2M_CSC_16BIT_565 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SOLO_P2M_DESC_INTR_OPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SOLO_P2M_DMA_INTERVAL(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) SOLO_P2M_PCI_MASTER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) solo_irq_on(solo_dev, SOLO_IRQ_P2M(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Find correct SDRAM size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (solo_dev->sdram_size = 0, i = 2; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) solo_reg_write(solo_dev, SOLO_DMA_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SOLO_DMA_CTRL_REFRESH_CYCLE(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SOLO_DMA_CTRL_SDRAM_SIZE(i) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) SOLO_DMA_CTRL_SDRAM_CLK_INVERT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) SOLO_DMA_CTRL_READ_CLK_SELECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) SOLO_DMA_CTRL_LATENCY(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SOLO_SYS_CFG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (solo_p2m_test(solo_dev, 0x07ff0000, 0x00010000) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) solo_p2m_test(solo_dev, 0x05ff0000, 0x00010000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (solo_p2m_test(solo_dev, 0x03ff0000, 0x00010000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (solo_p2m_test(solo_dev, 0x01ff0000, 0x00010000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) solo_dev->sdram_size = (32 << 20) << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!solo_dev->sdram_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_err(&solo_dev->pdev->dev, "Error detecting SDRAM size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (SOLO_SDRAM_END(solo_dev) > solo_dev->sdram_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(&solo_dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "SDRAM is not large enough (%u < %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) solo_dev->sdram_size, SOLO_SDRAM_END(solo_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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