Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Original author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Ben Collins <bcollins@ubuntu.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Additional work by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * John Brooks <john.brooks@bluecherry.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /* XXX: The SOLO6x10 i2c does not have separate interrupts for each i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * channel. The bus can only handle one i2c event at a time. The below handles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * this all wrong. We should be using the status registers to see if the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * is in use, and have a global lock to check the status register. Also,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * the bulk of the work should be handled out-of-interrupt. The ugly loops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * that occur during interrupt scare me. The ISR should merely signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * thread context, ACK the interrupt, and move on. -- BenC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/sched/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "solo6x10.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) u8 solo_i2c_readbyte(struct solo_dev *solo_dev, int id, u8 addr, u8 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	msgs[0].addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	msgs[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	msgs[0].buf = &off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	msgs[1].addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	msgs[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	msgs[1].buf = &data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	i2c_transfer(&solo_dev->i2c_adap[id], msgs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) void solo_i2c_writebyte(struct solo_dev *solo_dev, int id, u8 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			u8 off, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct i2c_msg msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	buf[0] = off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	buf[1] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	msgs.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	msgs.addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	msgs.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	msgs.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	i2c_transfer(&solo_dev->i2c_adap[id], &msgs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static void solo_i2c_flush(struct solo_dev *solo_dev, int wr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	ctrl = SOLO_IIC_CH_SET(solo_dev->i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (solo_dev->i2c_state == IIC_STATE_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		ctrl |= SOLO_IIC_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (wr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		ctrl |= SOLO_IIC_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		ctrl |= SOLO_IIC_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		if (!(solo_dev->i2c_msg->flags & I2C_M_NO_RD_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			ctrl |= SOLO_IIC_ACK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (solo_dev->i2c_msg_ptr == solo_dev->i2c_msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		ctrl |= SOLO_IIC_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	solo_reg_write(solo_dev, SOLO_IIC_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static void solo_i2c_start(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 addr = solo_dev->i2c_msg->addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (solo_dev->i2c_msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		addr |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	solo_dev->i2c_state = IIC_STATE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	solo_reg_write(solo_dev, SOLO_IIC_TXD, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	solo_i2c_flush(solo_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static void solo_i2c_stop(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	solo_irq_off(solo_dev, SOLO_IRQ_IIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	solo_reg_write(solo_dev, SOLO_IIC_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	solo_dev->i2c_state = IIC_STATE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	wake_up(&solo_dev->i2c_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int solo_i2c_handle_read(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) prepare_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (solo_dev->i2c_msg_ptr != solo_dev->i2c_msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		solo_i2c_flush(solo_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	solo_dev->i2c_msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	solo_dev->i2c_msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	solo_dev->i2c_msg_num--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (solo_dev->i2c_msg_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		solo_i2c_stop(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (!(solo_dev->i2c_msg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		solo_i2c_start(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		if (solo_dev->i2c_msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			goto prepare_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			solo_i2c_stop(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int solo_i2c_handle_write(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) retry_write:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (solo_dev->i2c_msg_ptr != solo_dev->i2c_msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		solo_reg_write(solo_dev, SOLO_IIC_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			       solo_dev->i2c_msg->buf[solo_dev->i2c_msg_ptr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		solo_dev->i2c_msg_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		solo_i2c_flush(solo_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	solo_dev->i2c_msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	solo_dev->i2c_msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	solo_dev->i2c_msg_num--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (solo_dev->i2c_msg_num == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		solo_i2c_stop(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (!(solo_dev->i2c_msg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		solo_i2c_start(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (solo_dev->i2c_msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			solo_i2c_stop(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			goto retry_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int solo_i2c_isr(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 status = solo_reg_read(solo_dev, SOLO_IIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (CHK_FLAGS(status, SOLO_IIC_STATE_TRNS | SOLO_IIC_STATE_SIG_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	    || solo_dev->i2c_id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		solo_i2c_stop(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	switch (solo_dev->i2c_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	case IIC_STATE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		if (solo_dev->i2c_msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			solo_dev->i2c_state = IIC_STATE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			ret = solo_i2c_handle_read(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		solo_dev->i2c_state = IIC_STATE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	case IIC_STATE_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		ret = solo_i2c_handle_write(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case IIC_STATE_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		solo_dev->i2c_msg->buf[solo_dev->i2c_msg_ptr] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			solo_reg_read(solo_dev, SOLO_IIC_RXD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		solo_dev->i2c_msg_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		ret = solo_i2c_handle_read(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		solo_i2c_stop(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int solo_i2c_master_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct solo_dev *solo_dev = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	DEFINE_WAIT(wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	for (i = 0; i < SOLO_I2C_ADAPTERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		if (&solo_dev->i2c_adap[i] == adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (i == SOLO_I2C_ADAPTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return num; /* XXX Right return value for failure? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mutex_lock(&solo_dev->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	solo_dev->i2c_id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	solo_dev->i2c_msg = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	solo_dev->i2c_msg_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	solo_dev->i2c_msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	solo_reg_write(solo_dev, SOLO_IIC_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	solo_irq_on(solo_dev, SOLO_IRQ_IIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	solo_i2c_start(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	timeout = HZ / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		prepare_to_wait(&solo_dev->i2c_wait, &wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		if (solo_dev->i2c_state == IIC_STATE_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		timeout = schedule_timeout(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		if (signal_pending(current))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	finish_wait(&solo_dev->i2c_wait, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = num - solo_dev->i2c_msg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	solo_dev->i2c_state = IIC_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	solo_dev->i2c_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	mutex_unlock(&solo_dev->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static u32 solo_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return I2C_FUNC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct i2c_algorithm solo_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.master_xfer	= solo_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.functionality	= solo_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int solo_i2c_init(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	solo_reg_write(solo_dev, SOLO_IIC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		       SOLO_IIC_PRESCALE(8) | SOLO_IIC_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	solo_dev->i2c_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	solo_dev->i2c_state = IIC_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	init_waitqueue_head(&solo_dev->i2c_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	mutex_init(&solo_dev->i2c_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	for (i = 0; i < SOLO_I2C_ADAPTERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		struct i2c_adapter *adap = &solo_dev->i2c_adap[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		snprintf(adap->name, I2C_NAME_SIZE, "%s I2C %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			 SOLO6X10_NAME, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		adap->algo = &solo_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		adap->algo_data = solo_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		adap->retries = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		adap->dev.parent = &solo_dev->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		ret = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			adap->algo_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		for (i = 0; i < SOLO_I2C_ADAPTERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			if (!solo_dev->i2c_adap[i].algo_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			i2c_del_adapter(&solo_dev->i2c_adap[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			solo_dev->i2c_adap[i].algo_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void solo_i2c_exit(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	for (i = 0; i < SOLO_I2C_ADAPTERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		if (!solo_dev->i2c_adap[i].algo_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		i2c_del_adapter(&solo_dev->i2c_adap[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		solo_dev->i2c_adap[i].algo_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }