^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Original author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ben Collins <bcollins@ubuntu.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Additional work by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * John Brooks <john.brooks@bluecherry.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "solo6x10.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static void solo_gpio_mode(struct solo_dev *solo_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned int port_mask, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* To set gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) for (port = 0; port < 16; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (!((1 << port) & port_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ret &= (~(3 << (port << 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ret |= ((mode & 3) << (port << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) solo_reg_write(solo_dev, SOLO_GPIO_CONFIG_0, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* To set extended gpio - sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) for (port = 0; port < 16; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (!((1UL << (port + 16)) & port_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ret &= ~(1UL << port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ret |= 1UL << port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Enable GPIO[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ret |= 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) solo_reg_write(solo_dev, SOLO_GPIO_CONFIG_1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void solo_gpio_set(struct solo_dev *solo_dev, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) solo_reg_write(solo_dev, SOLO_GPIO_DATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) solo_reg_read(solo_dev, SOLO_GPIO_DATA_OUT) | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void solo_gpio_clear(struct solo_dev *solo_dev, unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) solo_reg_write(solo_dev, SOLO_GPIO_DATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) solo_reg_read(solo_dev, SOLO_GPIO_DATA_OUT) & ~value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void solo_gpio_config(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Video reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) solo_gpio_mode(solo_dev, 0x30, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) solo_gpio_clear(solo_dev, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) solo_gpio_set(solo_dev, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Warning: Don't touch the next line unless you're sure of what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * you're doing: first four gpio [0-3] are used for video. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) solo_gpio_mode(solo_dev, 0x0f, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* We use bit 8-15 of SOLO_GPIO_CONFIG_0 for relay purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) solo_gpio_mode(solo_dev, 0xff00, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Initially set relay status to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) solo_gpio_clear(solo_dev, 0xff00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Set input pins direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) solo_gpio_mode(solo_dev, 0xffff0000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Pins 0-7 are not exported, because it seems from code above they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * used for internal purposes. So offset 0 corresponds to pin 8, therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * offsets 0-7 are relay GPIOs, 8-23 - input GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int solo_gpiochip_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int ret, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct solo_dev *solo_dev = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (offset < 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mode = 3 & (ret >> ((offset + 8) * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = solo_reg_read(solo_dev, SOLO_GPIO_CONFIG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mode = 1 & (ret >> (offset - 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else if (mode == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int solo_gpiochip_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int solo_gpiochip_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int solo_gpiochip_get(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct solo_dev *solo_dev = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = solo_reg_read(solo_dev, SOLO_GPIO_DATA_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 1 & (ret >> (offset + 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void solo_gpiochip_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct solo_dev *solo_dev = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) solo_gpio_set(solo_dev, 1 << (offset + 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) solo_gpio_clear(solo_dev, 1 << (offset + 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int solo_gpio_init(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) solo_gpio_config(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) solo_dev->gpio_dev.label = SOLO6X10_NAME"_gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) solo_dev->gpio_dev.parent = &solo_dev->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) solo_dev->gpio_dev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) solo_dev->gpio_dev.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) solo_dev->gpio_dev.ngpio = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) solo_dev->gpio_dev.can_sleep = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) solo_dev->gpio_dev.get_direction = solo_gpiochip_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) solo_dev->gpio_dev.direction_input = solo_gpiochip_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) solo_dev->gpio_dev.direction_output = solo_gpiochip_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) solo_dev->gpio_dev.get = solo_gpiochip_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) solo_dev->gpio_dev.set = solo_gpiochip_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = gpiochip_add_data(&solo_dev->gpio_dev, solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) solo_dev->gpio_dev.label = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void solo_gpio_exit(struct solo_dev *solo_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #ifdef CONFIG_GPIOLIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (solo_dev->gpio_dev.label) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) gpiochip_remove(&solo_dev->gpio_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) solo_dev->gpio_dev.label = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) solo_gpio_clear(solo_dev, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) solo_gpio_config(solo_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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