^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ngene.h: nGene PCIe bridge driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2007 Micronas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _NGENE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _NGENE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dvb/frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/dmxdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/dvbdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/dvb_demux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/dvb_ca_en50221.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/dvb_ringbuffer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/dvb_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "cxd2099.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DEVICE_NAME "ngene"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NGENE_VID 0x18c3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NGENE_PID 0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef VIDEO_CAP_VC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VIDEO_CAP_AVC 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VIDEO_CAP_H264 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VIDEO_CAP_VC1 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VIDEO_CAP_WMV9 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VIDEO_CAP_MPEG4 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DEMOD_TYPE_STV090X 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DEMOD_TYPE_DRXK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DEMOD_TYPE_STV0367 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DEMOD_TYPE_XO2 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DEMOD_TYPE_STV0910 (DEMOD_TYPE_XO2 + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DEMOD_TYPE_SONY_CT2 (DEMOD_TYPE_XO2 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DEMOD_TYPE_SONY_ISDBT (DEMOD_TYPE_XO2 + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DEMOD_TYPE_SONY_C2T2 (DEMOD_TYPE_XO2 + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DEMOD_TYPE_ST_ATSC (DEMOD_TYPE_XO2 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DEMOD_TYPE_SONY_C2T2I (DEMOD_TYPE_XO2 + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NGENE_XO2_TYPE_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NGENE_XO2_TYPE_DUOFLEX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NGENE_XO2_TYPE_CI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum STREAM {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) STREAM_VIDEOIN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) STREAM_AUDIOIN1, /* I2S or SPI Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) STREAM_AUDIOIN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) STREAM_AUDIOOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MAX_STREAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum SMODE_BITS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SMODE_AUDIO_SPDIF = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SMODE_AVSYNC = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SMODE_TRANSPORT_STREAM = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SMODE_AUDIO_CAPTURE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SMODE_VBI_CAPTURE = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SMODE_VIDEO_CAPTURE = 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum STREAM_FLAG_BITS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SFLAG_COLORBAR = 0x04, /* Select colorbar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PROGRAM_ROM 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PROGRAM_SRAM 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PERIPHERALS0 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PERIPHERALS1 0x9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SHARED_BUFFER 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define NGENE_COMMAND (SHARED_BUFFER+0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NGENE_STATUS (SHARED_BUFFER+0x0208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define NGENE_EVENT (SHARED_BUFFER+0x0210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define VARIABLES (SHARED_BUFFER+0x0210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EEPROM_AREA (SHARED_BUFFER+0x0A00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SG_VBI_1 (SHARED_BUFFER+0x0B00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SG_VBI_2 (SHARED_BUFFER+0x0C80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SG_V_OUT (SHARED_BUFFER+0x0D80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DATA_A_OUT (SHARED_BUFFER+0x0F80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DATA_V_OUT (SHARED_BUFFER+0x3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TIMESTAMPS 0xA000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SCRATCHPAD 0xA080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define FORCE_INT 0xA088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define FORCE_NMI 0xA090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INT_STATUS 0xA0A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DEV_VER 0x9004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct SG_ADDR {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u64 curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u16 curr_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u16 elements;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 pad[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct SHARED_MEMORY {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* C000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 HostToNgene[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* C100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 NgeneToHost[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* C200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u64 NgeneCommand;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u64 NgeneStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u64 NgeneEvent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* C210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 pad1[0xc260 - 0xc218];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* C260 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 IntCounts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 IntEnable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* C268 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 pad2[0xd000 - 0xc268];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct BUFFER_STREAM_RESULTS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 Clock; /* Stream time in 100ns units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u16 RemainingLines; /* Remaining lines in this field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0 for complete field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 FieldCount; /* Video field number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) Bit 0 = FieldID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u16 BlockCount; /* Audio block count (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 Reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 DTOUpdate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct HW_SCATTER_GATHER_ELEMENT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u64 Address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 Length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 Reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct BUFFER_HEADER {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u64 Next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct BUFFER_STREAM_RESULTS SR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 Number_of_entries_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 Reserved5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u64 Address_of_first_entry_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 Number_of_entries_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 Reserved7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u64 Address_of_first_entry_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct EVENT_BUFFER {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 TimeStamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 GPIOStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 UARTStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 RXCharacter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 EventStatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 Reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Firmware commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) enum OPCODES {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CMD_NOP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) CMD_FWLOAD_PREPARE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) CMD_FWLOAD_FINISH = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CMD_I2C_READ = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CMD_I2C_WRITE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) CMD_I2C_WRITE_NOSTOP = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) CMD_I2C_CONTINUE_WRITE = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) CMD_DEBUG_OUTPUT = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CMD_CONTROL = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CMD_CONFIGURE_BUFFER = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CMD_CONFIGURE_FREE_BUFFER = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CMD_SPI_READ = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CMD_SPI_WRITE = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CMD_MEM_READ = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CMD_MEM_WRITE = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CMD_SFR_READ = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CMD_SFR_WRITE = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CMD_IRAM_READ = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CMD_IRAM_WRITE = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CMD_SET_GPIO_PIN = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CMD_SET_GPIO_INT = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) CMD_CONFIGURE_UART = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) CMD_WRITE_UART = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MAX_CMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) enum RESPONSES {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) OK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ERROR = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct FW_HEADER {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 Opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 Length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct FW_I2C_WRITE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u8 Device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 Data[250];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct FW_I2C_CONTINUE_WRITE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 Data[250];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct FW_I2C_READ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u8 Device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 Data[252]; /* followed by two bytes of read data count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct FW_SPI_WRITE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 ModeSelect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 Data[250];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct FW_SPI_READ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u8 ModeSelect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u8 Data[252]; /* followed by two bytes of read data count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct FW_FWLOAD_PREPARE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct FW_FWLOAD_FINISH {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u16 Address; /* address of final block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u16 Length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Meaning of FW_STREAM_CONTROL::Mode bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Bit 7: Loopback PEXin to PEXout using TVOut channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Bit 6: AVLOOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Bit 5: Audio select; 0=I2S, 1=SPDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Bit 4: AVSYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Bit 3: Enable transport stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Bit 2: Enable audio capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Bit 1: Enable ITU-Video VBI capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Bit 0: Enable ITU-Video capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * Bit 7: continuous capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Bit 6: capture one field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Bit 5: capture one frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Bit 4: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Bit 3: starting field; 0=odd, 1=even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Bit 2: sample size; 0=8-bit, 1=10-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Bit 1: data format; 0=UYVY, 1=YUY2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Bit 0: resets buffer pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) enum FSC_MODE_BITS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SMODE_LOOPBACK = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) SMODE_AVLOOP = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) _SMODE_AUDIO_SPDIF = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) _SMODE_AVSYNC = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) _SMODE_TRANSPORT_STREAM = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) _SMODE_AUDIO_CAPTURE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) _SMODE_VBI_CAPTURE = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) _SMODE_VIDEO_CAPTURE = 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Meaning of FW_STREAM_CONTROL::Stream bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Bit 3: Audio sample count: 0 = relative, 1 = absolute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Bits 1-0: stream select, UVI1, UVI2, TVOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct FW_STREAM_CONTROL {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 Control; /* Value written to UVI1_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 Mode; /* Controls clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 SetupDataLen; /* Length of setup data, MSB=1 write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) backwards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) for TS and Audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u64 Buffer_Address; /* Address of first buffer header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u16 BytesPerVideoLine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u16 MaxLinesPerField;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u16 MinLinesPerField;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u16 Reserved_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u16 BytesPerVBILine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u16 MaxVBILinesPerField;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u16 MinVBILinesPerField;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u16 SetupDataAddr; /* ngene relative address of setup data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 SetupData[32]; /* setup data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) } __attribute__((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define AUDIO_BLOCK_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define TS_BLOCK_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct FW_MEM_READ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u16 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct FW_MEM_WRITE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u16 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct FW_SFR_IRAM_READ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct FW_SFR_IRAM_WRITE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u8 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct FW_SET_GPIO_PIN {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u8 select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct FW_SET_GPIO_INT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u8 select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct FW_SET_DEBUGMODE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 debug_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct FW_CONFIGURE_BUFFERS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) enum _BUFFER_CONFIGS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) BUFFER_CONFIG_4422 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) BUFFER_CONFIG_3333 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) BUFFER_CONFIG_8022 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct FW_CONFIGURE_FREE_BUFFERS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u8 UVI1_BufferLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u8 UVI2_BufferLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u8 TVO_BufferLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u8 AUD1_BufferLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u8 AUD2_BufferLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u8 TVA_BufferLength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } __packed config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct FW_CONFIGURE_UART {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u8 UartControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) enum _UART_CONFIG {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) _UART_BAUDRATE_19200 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) _UART_BAUDRATE_9600 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) _UART_BAUDRATE_4800 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) _UART_BAUDRATE_2400 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) _UART_RX_ENABLE = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) _UART_TX_ENABLE = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct FW_WRITE_UART {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u8 Data[252];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct ngene_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 in_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 out_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 raw[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u8 raw8[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct FW_HEADER hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct FW_I2C_WRITE I2CWrite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct FW_I2C_CONTINUE_WRITE I2CContinueWrite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct FW_I2C_READ I2CRead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct FW_STREAM_CONTROL StreamControl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct FW_FWLOAD_PREPARE FWLoadPrepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct FW_FWLOAD_FINISH FWLoadFinish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct FW_MEM_READ MemoryRead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct FW_MEM_WRITE MemoryWrite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct FW_SFR_IRAM_READ SfrIramRead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct FW_SFR_IRAM_WRITE SfrIramWrite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct FW_SPI_WRITE SPIWrite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct FW_SPI_READ SPIRead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct FW_SET_GPIO_PIN SetGpioPin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct FW_SET_GPIO_INT SetGpioInt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct FW_SET_DEBUGMODE SetDebugMode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct FW_CONFIGURE_BUFFERS ConfigureBuffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct FW_CONFIGURE_UART ConfigureUart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct FW_WRITE_UART WriteUart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } __attribute__ ((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define NGENE_INTERFACE_VERSION 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) Max: (1920x1080i60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define OVERFLOW_BUFFER_SIZE (8192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define RING_SIZE_VIDEO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define RING_SIZE_AUDIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define RING_SIZE_TS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define NUM_SCATTER_GATHER_ENTRIES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) RING_SIZE_VIDEO * 2) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) (RING_SIZE_TS * PAGE_SIZE * 4) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define EVENT_QUEUE_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Gathers the current state of a single channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct SBufferHeader {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct SBufferHeader *Next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) void *Buffer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct HW_SCATTER_GATHER_ELEMENT *scList1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) void *Buffer2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct HW_SCATTER_GATHER_ELEMENT *scList2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) enum HWSTATE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) HWSTATE_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) HWSTATE_STARTUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) HWSTATE_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) HWSTATE_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) enum KSSTATE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) KSSTATE_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) KSSTATE_ACQUIRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) KSSTATE_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) KSSTATE_RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct SRingBufferDescriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct SBufferHeader *Head; /* Points to first buffer in ring buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) structure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u64 PAHead; /* Physical address of first buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 MemSize; /* Memory size of allocated ring buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) (needed for freeing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 NumBuffers; /* Number of buffers in the ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 Buffer1Length; /* Allocated length of Buffer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 Buffer2Length; /* Allocated length of Buffer 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) void *SCListMem; /* Memory to hold scatter gather lists for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u64 PASCListMem; /* Physical address .. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 SCListMemSize; /* Size of this memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) enum STREAMMODEFLAGS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) StreamMode_NONE = 0, /* Stream not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) StreamMode_TSIN = 2, /* Transport stream input (all) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) (only stream 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) enum BufferExchangeFlags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) BEF_EVEN_FIELD = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) BEF_CONTINUATION = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) BEF_MORE_DATA = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) BEF_OVERFLOW = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) DF_SWAP32 = 0x00010000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct MICI_STREAMINFO {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) IBufferExchange *pExchange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u8 Stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u8 Flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u8 Mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u8 Reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u16 nLinesVideo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u16 nBytesPerLineVideo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u16 nLinesVBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u16 nBytesPerLineVBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 CaptureLength; /* Used for audio and transport stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* STRUCTS ******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* sound hardware definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define MIXER_ADDR_TVTUNER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define MIXER_ADDR_LAST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct ngene_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*struct sound chip*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct mychip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct ngene_channel *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) spinlock_t mixer_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int mixer_volume[MIXER_ADDR_LAST + 1][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int capture_source[MIXER_ADDR_LAST + 1][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #ifdef NGENE_V4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct ngene_overlay {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int tvnorm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct v4l2_rect w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) enum v4l2_field field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct v4l2_clip *clips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int nclips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int setup_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct ngene_tvnorm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int v4l2_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u16 swidth, sheight; /* scaled standard width, height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int tuner_norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int soundstd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct ngene_vopen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct ngene_channel *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) enum v4l2_priority prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct videobuf_queue vbuf_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct videobuf_queue vbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int picxcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) enum v4l2_buf_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) const struct ngene_format *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) const struct ngene_format *ovfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct ngene_overlay ov;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct ngene_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct device device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct i2c_adapter i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct i2c_client *i2c_client[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int i2c_client_fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct ngene *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bool has_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) bool has_demux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int demod_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int (*gate_ctrl)(struct dvb_frontend *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct dvb_frontend *fe2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct dmxdev dmxdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct dvb_demux demux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct dvb_net dvbnet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct dmx_frontend hw_frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct dmx_frontend mem_frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int users;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct video_device *v4l_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct dvb_device *ci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct tasklet_struct demux_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct SBufferHeader *nextBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) enum KSSTATE State;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) enum HWSTATE HWState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u8 Stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u8 Flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8 Mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) IBufferExchange *pBufferExchange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) IBufferExchange *pBufferExchange2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) spinlock_t state_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u16 nLines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u16 nBytesPerLine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u16 nVBILines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u16 nBytesPerVBILine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u16 itumode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 Capture1Length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 Capture2Length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct SRingBufferDescriptor RingBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct SRingBufferDescriptor TSRingBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct SRingBufferDescriptor TSIdleBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u32 DataFormatFlags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int AudioDTOUpdated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 AudioDTOValue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int (*set_tone)(struct dvb_frontend *, enum fe_sec_tone_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u8 lnbh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* stuff from analog driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct mychip *mychip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct snd_card *soundcard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u8 *evenbuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u8 dma_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int soundstreamon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int audiomute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int soundbuffisallocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int sndbuffflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) int tun_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int dec_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int tun_dec_rdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) int lastbufferflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct ngene_tvnorm *tvnorms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int tvnorm_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int tvnorm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #ifdef NGENE_V4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int videousers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct v4l2_prio_state prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct ngene_vopen init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct v4l2_framebuffer fbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct ngene_buffer *screen; /* overlay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct list_head capture; /* video capture queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) spinlock_t s_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct semaphore reslock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int tsin_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u8 tsin_buffer[188];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct ngene_ci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct device device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct i2c_adapter i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct ngene *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct dvb_ca_en50221 *en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct ngene;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) typedef void (rx_cb_t)(struct ngene *, u32, u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) typedef void (tx_cb_t)(struct ngene *, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct ngene {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned char __iomem *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*struct i2c_adapter i2c_adapter;*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u32 device_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u32 fw_interface_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 icounts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) bool msi_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) bool cmd_timeout_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u8 *CmdDoneByte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int BootFirmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) void *OverflowBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dma_addr_t PAOverflowBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) void *FWInterfaceBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dma_addr_t PAFWInterfaceBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u8 *ngenetohost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u8 *hosttongene;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) int EventQueueOverflowCount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) int EventQueueOverflowFlag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct tasklet_struct event_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct EVENT_BUFFER *EventBuffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int EventQueueWriteIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int EventQueueReadIndex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) wait_queue_head_t cmd_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) int cmd_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct mutex cmd_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct mutex stream_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct semaphore pll_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct mutex i2c_switch_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int i2c_current_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int i2c_current_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) spinlock_t cmd_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct dvb_adapter adapter[MAX_STREAM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct ngene_channel channel[MAX_STREAM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct ngene_info *card_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) tx_cb_t *TxEventNotify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) rx_cb_t *RxEventNotify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int tx_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) wait_queue_head_t tx_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) wait_queue_head_t rx_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define UART_RBUF_LEN 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u8 uart_rbuf[UART_RBUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int uart_rp, uart_wp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define TS_FILLER 0x6f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u8 *tsout_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define TSOUT_BUF_SIZE (512*188*8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct dvb_ringbuffer tsout_rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u8 *tsin_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define TSIN_BUF_SIZE (512*188*8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct dvb_ringbuffer tsin_rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u8 *ain_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define AIN_BUF_SIZE (128*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct dvb_ringbuffer ain_rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u8 *vin_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define VIN_BUF_SIZE (4*1920*1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct dvb_ringbuffer vin_rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) unsigned long exp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) int prev_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct ngene_ci ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct ngene_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define NGENE_APP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define NGENE_TERRATEC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define NGENE_SIDEWINDER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define NGENE_RACER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define NGENE_VIPER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define NGENE_PYTHON 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define NGENE_VBOX_V1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define NGENE_VBOX_V2 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int fw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) bool msi_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) int io_type[MAX_STREAM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define NGENE_IO_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define NGENE_IO_TV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define NGENE_IO_HDTV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define NGENE_IO_TSIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define NGENE_IO_TSOUT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define NGENE_IO_AIN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) void *fe_config[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) void *tuner_config[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int (*demod_attach[4])(struct ngene_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int (*tuner_attach[4])(struct ngene_channel *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u8 avf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u8 msp[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u8 demoda[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u8 lnb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int i2c_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u8 ntsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u8 tsf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u8 i2s[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int (*gate_ctrl)(struct dvb_frontend *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int (*switch_ctrl)(struct ngene_channel *, int, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #ifdef NGENE_V4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct ngene_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int fourcc; /* video4linux 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int btformat; /* BT848_COLOR_FMT_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int btswap; /* BT848_COLOR_CTL_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) int depth; /* bit/pixel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int hshift, vshift; /* for planar modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int palette;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define RESOURCE_OVERLAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define RESOURCE_VIDEO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define RESOURCE_VBI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct ngene_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* common v4l buffer stuff -- must be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct videobuf_buffer vb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* ngene specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) const struct ngene_format *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) int tvnorm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int btformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int btswap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Provided by ngene-core.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) void ngene_remove(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) void ngene_shutdown(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int ngene_command(struct ngene *dev, struct ngene_command *com);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) void set_transfer(struct ngene_channel *chan, int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) void FillTSBuffer(void *Buffer, int Length, u32 Flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* Provided by ngene-cards.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int ngene_port_has_cxd2099(struct i2c_adapter *i2c, u8 *type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* Provided by ngene-i2c.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int ngene_i2c_init(struct ngene *dev, int dev_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* Provided by ngene-dvb.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) extern struct dvb_device ngene_dvbdev_ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int (*start_feed)(struct dvb_demux_feed *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int (*stop_feed)(struct dvb_demux_feed *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) void *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct dvb_demux *dvbdemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct dmx_frontend *hw_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct dmx_frontend *mem_frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct dvb_adapter *dvb_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* LocalWords: Endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags