Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ngene-i2c.c: nGene PCIe bridge driver i2c functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2005-2007 Micronas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *                         Modifications for new nGene firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *                         support for EEPROM-copying,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *                         support for new dual DVB-S2 card prototype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* FIXME - some of these can probably be removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/poll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/byteorder/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include "ngene.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* Firmware command for i2c operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static int ngene_command_i2c_read(struct ngene *dev, u8 adr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			   u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct ngene_command com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	com.cmd.hdr.Opcode = CMD_I2C_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	com.cmd.hdr.Length = outlen + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	com.cmd.I2CRead.Device = adr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	memcpy(com.cmd.I2CRead.Data, out, outlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	com.cmd.I2CRead.Data[outlen] = inlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	com.cmd.I2CRead.Data[outlen + 1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	com.in_len = outlen + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	com.out_len = inlen + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (ngene_command(dev, &com) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if ((com.cmd.raw8[0] >> 1) != adr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		memcpy(in, com.cmd.raw8, inlen + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		memcpy(in, com.cmd.raw8 + 1, inlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static int ngene_command_i2c_write(struct ngene *dev, u8 adr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 				   u8 *out, u8 outlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct ngene_command com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	com.cmd.hdr.Opcode = CMD_I2C_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	com.cmd.hdr.Length = outlen + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	com.cmd.I2CRead.Device = adr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	memcpy(com.cmd.I2CRead.Data, out, outlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	com.in_len = outlen + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	com.out_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (ngene_command(dev, &com) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (com.cmd.raw8[0] == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static void ngene_i2c_set_bus(struct ngene *dev, int bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (!(dev->card_info->i2c_access & 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (dev->i2c_current_bus == bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	switch (bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		ngene_command_gpio_set(dev, 3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		ngene_command_gpio_set(dev, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		ngene_command_gpio_set(dev, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		ngene_command_gpio_set(dev, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	dev->i2c_current_bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				 struct i2c_msg msg[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct ngene_channel *chan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		(struct ngene_channel *)i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct ngene *dev = chan->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mutex_lock(&dev->i2c_switch_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ngene_i2c_set_bus(dev, chan->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		if (!ngene_command_i2c_read(dev, msg[0].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					    msg[0].buf, msg[0].len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 					    msg[1].buf, msg[1].len, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (num == 1 && !(msg[0].flags & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		if (!ngene_command_i2c_write(dev, msg[0].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 					     msg[0].buf, msg[0].len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (num == 1 && (msg[0].flags & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (!ngene_command_i2c_read(dev, msg[0].addr, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 					    msg[0].buf, msg[0].len, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	mutex_unlock(&dev->i2c_switch_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	mutex_unlock(&dev->i2c_switch_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct i2c_algorithm ngene_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.master_xfer = ngene_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.functionality = ngene_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ngene_i2c_init(struct ngene *dev, int dev_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	strscpy(adap->name, "nGene", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	adap->algo = &ngene_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	adap->algo_data = (void *)&(dev->channel[dev_nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	adap->dev.parent = &dev->pci_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)