^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Conexant CX23885 PCIe bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kdev_t.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <media/v4l2-fh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/tuner.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/tveeprom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/videobuf2-dma-sg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/videobuf2-dvb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/rc-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "cx23885-reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "media/drv-intf/cx2341x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CX23885_VERSION "0.0.4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UNSET (-1U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CX23885_MAXBOARDS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Max number of inputs by card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MAX_CX23885_INPUT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CX23885_BOARD_NOAUTO UNSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CX23885_BOARD_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CX23885_BOARD_HAUPPAUGE_HVR1800 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CX23885_BOARD_HAUPPAUGE_HVR1250 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CX23885_BOARD_HAUPPAUGE_HVR1500 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CX23885_BOARD_HAUPPAUGE_HVR1200 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CX23885_BOARD_HAUPPAUGE_HVR1700 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CX23885_BOARD_HAUPPAUGE_HVR1400 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CX23885_BOARD_TBS_6920 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CX23885_BOARD_TEVII_S470 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CX23885_BOARD_DVBWORLD_2005 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CX23885_BOARD_HAUPPAUGE_HVR1270 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CX23885_BOARD_HAUPPAUGE_HVR1275 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CX23885_BOARD_HAUPPAUGE_HVR1255 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CX23885_BOARD_HAUPPAUGE_HVR1210 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CX23885_BOARD_MYGICA_X8506 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CX23885_BOARD_HAUPPAUGE_HVR1850 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CX23885_BOARD_HAUPPAUGE_HVR1290 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CX23885_BOARD_MYGICA_X8558PRO 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CX23885_BOARD_MPX885 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CX23885_BOARD_MYGICA_X8507 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CX23885_BOARD_TEVII_S471 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CX23885_BOARD_PROF_8000 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CX23885_BOARD_HAUPPAUGE_HVR4400 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CX23885_BOARD_AVERMEDIA_HC81R 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CX23885_BOARD_TBS_6981 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CX23885_BOARD_TBS_6980 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CX23885_BOARD_HAUPPAUGE_IMPACTVCBE 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CX23885_BOARD_DVBSKY_T9580 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CX23885_BOARD_DVBSKY_T980C 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CX23885_BOARD_DVBSKY_S950C 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CX23885_BOARD_TT_CT2_4500_CI 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CX23885_BOARD_DVBSKY_S950 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CX23885_BOARD_DVBSKY_S952 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CX23885_BOARD_DVBSKY_T982 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CX23885_BOARD_HAUPPAUGE_HVR5525 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CX23885_BOARD_HAUPPAUGE_STARBURST 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CX23885_BOARD_VIEWCAST_260E 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CX23885_BOARD_VIEWCAST_460E 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CX23885_BOARD_HAUPPAUGE_QUADHD_DVB 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CX23885_BOARD_HAUPPAUGE_HVR1265_K4 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CX23885_BOARD_HAUPPAUGE_STARBURST2 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CX23885_BOARD_AVERMEDIA_CE310B 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GPIO_0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GPIO_1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GPIO_2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GPIO_3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GPIO_4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GPIO_5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GPIO_6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GPIO_7 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPIO_8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GPIO_9 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GPIO_10 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GPIO_11 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GPIO_12 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GPIO_13 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GPIO_14 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GPIO_15 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CX23885_NORMS (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct cx23885_fmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 fourcc; /* v4l2 format id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 cxformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct cx23885_tvnorm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) v4l2_std_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 cxiformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 cxoformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) enum cx23885_itype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CX23885_VMUX_COMPOSITE1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CX23885_VMUX_COMPOSITE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CX23885_VMUX_COMPOSITE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CX23885_VMUX_COMPOSITE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CX23885_VMUX_SVIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CX23885_VMUX_COMPONENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CX23885_VMUX_TELEVISION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CX23885_VMUX_CABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CX23885_VMUX_DVB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CX23885_VMUX_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CX23885_RADIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enum cx23885_src_sel_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CX23885_SRC_SEL_EXT_656_VIDEO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct cx23885_riscmem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __le32 *cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) __le32 *jmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* buffer for one video frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct cx23885_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* common v4l buffer stuff -- must be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct vb2_v4l2_buffer vb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* cx23885 specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int bpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct cx23885_riscmem risc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct cx23885_fmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct cx23885_input {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) enum cx23885_itype type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int vmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int amux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 gpio0, gpio1, gpio2, gpio3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CX23885_MPEG_UNDEFINED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) CX23885_MPEG_DVB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CX23885_ANALOG_VIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CX23885_MPEG_ENCODER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } port_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct cx23885_board {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) port_t porta, portb, portc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int num_fds_portb, num_fds_portc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int tuner_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int radio_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned char tuner_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned char radio_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int tuner_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Vendors can and do run the PCIe bridge at different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * clock rates, driven physically by crystals on the PCBs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * The core has to accommodate this. This allows the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * to add new boards with new frequencys. The value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * expressed in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * The core framework will default this value based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * current designs, but it can vary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct cx23885_input input[MAX_CX23885_INPUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ci_type; /* for NetUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Force bottom field first during DMA (888 workaround) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 force_bff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct cx23885_subid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u16 subvendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct cx23885_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct cx23885_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* i2c i/o */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct i2c_adapter i2c_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct i2c_client i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 i2c_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* 885 registers used for raw address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 i2c_period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 reg_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 reg_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 reg_rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 reg_wdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct cx23885_dmaqueue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct list_head active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct cx23885_tsport {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct cx23885_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int sram_chno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct vb2_dvb_frontends frontends;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* dma queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct cx23885_dmaqueue mpegq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 ts_packet_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 ts_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 reg_gpcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 reg_gpcnt_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 reg_dma_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 reg_lngth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 reg_hw_sop_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 reg_gen_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 reg_bd_pkt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 reg_sop_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 reg_fifo_ovfl_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 reg_vld_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 reg_ts_clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 reg_ts_int_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 reg_ts_int_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 reg_src_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Default register vals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int pci_irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 dma_ctl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 ts_int_msk_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 gen_ctrl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 ts_clk_en_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 src_sel_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 vld_misc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 hw_sop_ctrl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Allow a single tsport to have multiple frontends */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 num_frontends;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void (*gate_ctrl)(struct cx23885_tsport *port, int open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void *port_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Workaround for a temp dvb_frontend that the tuner can attached to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct dvb_frontend analog_fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct i2c_client *i2c_client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct i2c_client *i2c_client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct i2c_client *i2c_client_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct i2c_client *i2c_client_ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int (*set_frontend)(struct dvb_frontend *fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int (*fe_set_voltage)(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum fe_sec_voltage voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct cx23885_kernel_ir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct cx23885_dev *cx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) char *phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct rc_dev *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct cx23885_audio_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int bpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct cx23885_riscmem risc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct scatterlist *sglist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int sglen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned long nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct cx23885_audio_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct cx23885_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) atomic_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int num_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct cx23885_audio_buffer *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct cx23885_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) atomic_t refcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct v4l2_device v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* pci stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned char pci_rev, pci_lat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int pci_bus, pci_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 __iomem *lmmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 __iomem *bmmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int pci_irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spinlock_t pci_irqmask_lock; /* protects mask reg too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int hwrevision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* This valud is board specific and is used to configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * AV core so we see nice clean and stable video and audio. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct cx23885_i2c i2c_bus[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct mutex gpio_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* board details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned int board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct cx23885_tsport ts1, ts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* sram configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct sram_channel *sram_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) CX23885_BRIDGE_UNDEFINED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CX23885_BRIDGE_885 = 885,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CX23885_BRIDGE_887 = 887,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) CX23885_BRIDGE_888 = 888,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) } bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Analog video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int audinput; /* Selectable audio input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 tvaudio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) v4l2_std_id tvnorm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int tuner_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned char tuner_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int tuner_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int radio_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned char radio_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct v4l2_subdev *sd_cx25840;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct work_struct cx25840_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Infrared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct v4l2_subdev *sd_ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct work_struct ir_rx_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned long ir_rx_notifications;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct work_struct ir_tx_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned long ir_tx_notifications;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct cx23885_kernel_ir *kernel_ir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) atomic_t ir_input_stopping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* V4l */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct video_device *video_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct video_device *vbi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* video capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct cx23885_fmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int width, height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct cx23885_dmaqueue vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct vb2_queue vb2_vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct cx23885_dmaqueue vbiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct vb2_queue vb2_vbiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* MPEG Encoder ONLY settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 cx23417_mailbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct cx2341x_handler cxhdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct video_device *v4l_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct vb2_queue vb2_mpegq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct cx23885_tvnorm encodernorm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Analog raw audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct cx23885_audio_dev *audio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Does the system require periodic DMA resets? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int need_dma_reset:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define call_all(dev, o, f, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define CX23885_HW_888_IR (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define CX23885_HW_AV_CORE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define call_hw(dev, grpid, o, f, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SRAM_CH01 0 /* Video A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SRAM_CH02 1 /* VBI A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SRAM_CH03 2 /* Video B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SRAM_CH04 3 /* Transport via B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SRAM_CH05 4 /* VBI B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SRAM_CH06 5 /* Video C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SRAM_CH07 6 /* Transport via C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SRAM_CH08 7 /* Audio Internal A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SRAM_CH09 8 /* Audio Internal B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SRAM_CH10 9 /* Audio External */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SRAM_CH11 10 /* COMB_3D_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SRAM_CH12 11 /* Comb 3D N1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SRAM_CH13 12 /* Comb 3D N2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SRAM_CH14 13 /* MOE Vid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SRAM_CH15 14 /* MOE RSLT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct sram_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 cmds_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 ctrl_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 cdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 fifo_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 ptr1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 ptr2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 cnt1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 cnt2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 jumponly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define cx_andor(reg, mask, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ((value) & (mask)), dev->lmmio+((reg)>>2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* cx23885-core.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct sram_channel *ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned int bpl, u32 risc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct sram_channel *ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) extern int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct scatterlist *sglist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int top_offset, unsigned int bottom_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int bpl, unsigned int padding, unsigned int lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) extern int cx23885_risc_vbibuffer(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct cx23885_riscmem *risc, struct scatterlist *sglist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int top_offset, unsigned int bottom_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned int bpl, unsigned int padding, unsigned int lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int cx23885_start_dma(struct cx23885_tsport *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct cx23885_dmaqueue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct cx23885_buffer *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) void cx23885_cancel_buffers(struct cx23885_tsport *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int asoutput);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* cx23885-cards.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) extern struct cx23885_board cx23885_boards[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) extern const unsigned int cx23885_bcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) extern struct cx23885_subid cx23885_subids[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) extern const unsigned int cx23885_idcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) extern int cx23885_tuner_callback(void *priv, int component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int command, int arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) extern void cx23885_card_list(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) extern int cx23885_ir_init(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) extern void cx23885_ir_fini(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) extern void cx23885_gpio_setup(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) extern void cx23885_card_setup(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) extern int cx23885_dvb_register(struct cx23885_tsport *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) extern int cx23885_buf_prepare(struct cx23885_buffer *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct cx23885_tsport *port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) extern void cx23885_buf_queue(struct cx23885_tsport *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct cx23885_buffer *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) extern void cx23885_free_buffer(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct cx23885_buffer *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* cx23885-video.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) extern int cx23885_video_register(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) extern void cx23885_video_unregister(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) extern void cx23885_video_wakeup(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct cx23885_dmaqueue *q, u32 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int cx23885_set_input(struct file *file, void *priv, unsigned int i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int cx23885_get_input(struct file *file, void *priv, unsigned int *i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int cx23885_set_frequency(struct file *file, void *priv, const struct v4l2_frequency *f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* cx23885-vbi.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) extern int cx23885_vbi_fmt(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct v4l2_format *f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) extern void cx23885_vbi_timeout(unsigned long data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) extern const struct vb2_ops cx23885_vbi_qops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* cx23885-i2c.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) extern int cx23885_i2c_register(struct cx23885_i2c *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* cx23885-417.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) extern int cx23885_417_register(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) extern void cx23885_417_unregister(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) extern void cx23885_mc417_init(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) extern int mc417_register_read(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u16 address, u32 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) extern int mc417_register_write(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u16 address, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* cx23885-alsa.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) extern struct cx23885_audio_dev *cx23885_audio_register(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) extern void cx23885_audio_unregister(struct cx23885_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) extern int cx23885_risc_databuffer(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct cx23885_riscmem *risc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct scatterlist *sglist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned int bpl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned int lines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned int lpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* tv norms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static inline unsigned int norm_maxh(v4l2_std_id norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return (norm & V4L2_STD_525_60) ? 480 : 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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