^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Conexant CX23885 PCIe bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "cx23885.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "cx23885-video.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kmod.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "cx23885-ioctl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "tuner-xc2028.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/drv-intf/cx25840.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MODULE_DESCRIPTION("v4l2 driver module for cx23885 based TV cards");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static unsigned int video_nr[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned int vbi_nr[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) module_param_array(video_nr, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) module_param_array(vbi_nr, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(video_nr, "video device numbers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MODULE_PARM_DESC(vbi_nr, "vbi device numbers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static unsigned int video_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) module_param(video_debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_PARM_DESC(video_debug, "enable debug messages [video]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static unsigned int irq_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) module_param(irq_debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static unsigned int vid_limit = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) module_param(vid_limit, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_PARM_DESC(vid_limit, "capture memory limit in megabytes");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define dprintk(level, fmt, arg...)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) do { if (video_debug >= level)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) printk(KERN_DEBUG pr_fmt("%s: video:" fmt), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* static data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FORMAT_FLAGS_PACKED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct cx23885_fmt formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .fourcc = V4L2_PIX_FMT_YUYV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .flags = FORMAT_FLAGS_PACKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct cx23885_fmt *format_by_fourcc(unsigned int fourcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) for (i = 0; i < ARRAY_SIZE(formats); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (formats[i].fourcc == fourcc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return formats+i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void cx23885_video_wakeup(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct cx23885_dmaqueue *q, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct cx23885_buffer *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (list_empty(&q->active))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) buf = list_entry(q->active.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct cx23885_buffer, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) buf->vb.sequence = q->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) buf->vb.vb2_buf.timestamp = ktime_get_ns();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) buf->vb.vb2_buf.index, count, q->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) list_del(&buf->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct v4l2_subdev_format format = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .which = V4L2_SUBDEV_FORMAT_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .format.code = MEDIA_BUS_FMT_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dprintk(1, "%s(norm = 0x%08x) name: [%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (unsigned int)norm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) v4l2_norm_to_name(norm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (dev->tvnorm == norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (dev->tvnorm != norm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (vb2_is_busy(&dev->vb2_vidq) || vb2_is_busy(&dev->vb2_vbiq) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) vb2_is_busy(&dev->vb2_mpegq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev->tvnorm = norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev->width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev->height = norm_maxh(norm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev->field = V4L2_FIELD_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) call_all(dev, video, s_std, norm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) format.format.width = dev->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) format.format.height = dev->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) format.format.field = dev->field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) call_all(dev, pad, set_fmt, NULL, &format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct video_device *cx23885_vdev_init(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct video_device *template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) char *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct video_device *vfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) vfd = video_device_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (NULL == vfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *vfd = *template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) vfd->v4l2_dev = &dev->v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) vfd->release = video_device_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) vfd->lock = &dev->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) snprintf(vfd->name, sizeof(vfd->name), "%s (%s)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cx23885_boards[dev->board].name, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) video_set_drvdata(vfd, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return vfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int cx23885_flatiron_write(struct cx23885_dev *dev, u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* 8 bit registers, 8 bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 buf[] = { reg, data };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct i2c_msg msg = { .addr = 0x98 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .flags = 0, .buf = buf, .len = 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return i2c_transfer(&dev->i2c_bus[2].i2c_adap, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 cx23885_flatiron_read(struct cx23885_dev *dev, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* 8 bit registers, 8 bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 b0[] = { reg };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 b1[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .addr = 0x98 >> 1, .flags = 0, .buf = b0, .len = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .addr = 0x98 >> 1, .flags = I2C_M_RD, .buf = b1, .len = 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = i2c_transfer(&dev->i2c_bus[2].i2c_adap, &msg[0], 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pr_err("%s() error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return b1[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void cx23885_flatiron_dump(struct cx23885_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dprintk(1, "Flatiron dump\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) for (i = 0; i < 0x24; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dprintk(1, "FI[%02x] = %02x\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cx23885_flatiron_read(dev, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int cx23885_flatiron_mux(struct cx23885_dev *dev, int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dprintk(1, "%s(input = %d)\n", __func__, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (input == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val = cx23885_flatiron_read(dev, CH_PWR_CTRL1) & ~FLD_CH_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else if (input == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val = cx23885_flatiron_read(dev, CH_PWR_CTRL1) | FLD_CH_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val |= 0x20; /* Enable clock to delta-sigma and dec filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cx23885_flatiron_write(dev, CH_PWR_CTRL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) cx23885_flatiron_write(dev, CH_PWR_CTRL2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (video_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cx23885_flatiron_dump(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int cx23885_video_mux(struct cx23885_dev *dev, unsigned int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dprintk(1, "%s() video_mux: %d [vmux=%d, gpio=0x%x,0x%x,0x%x,0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) input, INPUT(input)->vmux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) INPUT(input)->gpio0, INPUT(input)->gpio1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) INPUT(input)->gpio2, INPUT(input)->gpio3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (dev->board == CX23885_BOARD_MYGICA_X8506 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev->board == CX23885_BOARD_MAGICPRO_PROHDTVE2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev->board == CX23885_BOARD_MYGICA_X8507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Select Analog TV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (INPUT(input)->type == CX23885_VMUX_TELEVISION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cx23885_gpio_clear(dev, GPIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Tell the internal A/V decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) v4l2_subdev_call(dev->sd_cx25840, video, s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) INPUT(input)->vmux, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if ((dev->board == CX23885_BOARD_HAUPPAUGE_HVR1800) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) (dev->board == CX23885_BOARD_MPX885) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1250) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (dev->board == CX23885_BOARD_HAUPPAUGE_IMPACTVCBE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255_22111) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1265_K4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_DVB) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1850) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) (dev->board == CX23885_BOARD_HAUPPAUGE_HVR5525) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) (dev->board == CX23885_BOARD_MYGICA_X8507) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (dev->board == CX23885_BOARD_AVERMEDIA_HC81R) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (dev->board == CX23885_BOARD_VIEWCAST_260E) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (dev->board == CX23885_BOARD_VIEWCAST_460E) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) (dev->board == CX23885_BOARD_AVERMEDIA_CE310B)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Configure audio routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) v4l2_subdev_call(dev->sd_cx25840, audio, s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) INPUT(input)->amux, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (INPUT(input)->amux == CX25840_AUDIO7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cx23885_flatiron_mux(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else if (INPUT(input)->amux == CX25840_AUDIO6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) cx23885_flatiron_mux(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int cx23885_audio_mux(struct cx23885_dev *dev, unsigned int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dprintk(1, "%s(input=%d)\n", __func__, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* The baseband video core of the cx23885 has two audio inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * LR1 and LR2. In almost every single case so far only HVR1xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * cards we've only ever supported LR1. Time to support LR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * which is available via the optional white breakout header on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * We'll use a could of existing enums in the card struct to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * devs to specify which baseband input they need, or just default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * to what we've always used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (INPUT(input)->amux == CX25840_AUDIO7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cx23885_flatiron_mux(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) else if (INPUT(input)->amux == CX25840_AUDIO6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cx23885_flatiron_mux(dev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Not specifically defined, assume the default. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) cx23885_flatiron_mux(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int cx23885_start_video_dma(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct cx23885_dmaqueue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct cx23885_buffer *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Stop the dma/fifo before we tamper with it's risc programs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cx_clear(VID_A_DMA_CTL, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* setup fifo + format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) buf->bpl, buf->risc.dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* reset counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) cx_write(VID_A_GPCNT_CTL, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) q->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* enable irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) cx23885_irq_add_enable(dev, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) cx_set(VID_A_INT_MSK, 0x000011);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* start dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) cx_set(DEV_CNTRL2, (1<<5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) cx_set(VID_A_DMA_CTL, 0x11); /* FIFO and RISC enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int queue_setup(struct vb2_queue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int *num_buffers, unsigned int *num_planes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int sizes[], struct device *alloc_devs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct cx23885_dev *dev = q->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *num_planes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) sizes[0] = (dev->fmt->depth * dev->width * dev->height) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int buffer_prepare(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct cx23885_buffer *buf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) container_of(vbuf, struct cx23885_buffer, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 line0_offset, line1_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int field_tff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) buf->bpl = (dev->width * dev->fmt->depth) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (vb2_plane_size(vb, 0) < dev->height * buf->bpl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) vb2_set_plane_payload(vb, 0, dev->height * buf->bpl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) switch (dev->field) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case V4L2_FIELD_TOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cx23885_risc_buffer(dev->pci, &buf->risc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sgt->sgl, 0, UNSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) buf->bpl, 0, dev->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case V4L2_FIELD_BOTTOM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) cx23885_risc_buffer(dev->pci, &buf->risc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sgt->sgl, UNSET, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) buf->bpl, 0, dev->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case V4L2_FIELD_INTERLACED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (dev->tvnorm & V4L2_STD_525_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* NTSC or */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) field_tff = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) field_tff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (cx23885_boards[dev->board].force_bff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* PAL / SECAM OR 888 in NTSC MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) field_tff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (field_tff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* cx25840 transmits NTSC bottom field first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dprintk(1, "%s() Creating TFF/NTSC risc\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) line0_offset = buf->bpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) line1_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* All other formats are top field first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dprintk(1, "%s() Creating BFF/PAL/SECAM risc\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) line0_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) line1_offset = buf->bpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) cx23885_risc_buffer(dev->pci, &buf->risc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sgt->sgl, line0_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) line1_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) buf->bpl, buf->bpl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev->height >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case V4L2_FIELD_SEQ_TB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cx23885_risc_buffer(dev->pci, &buf->risc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) sgt->sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0, buf->bpl * (dev->height >> 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) buf->bpl, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev->height >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case V4L2_FIELD_SEQ_BT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) cx23885_risc_buffer(dev->pci, &buf->risc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) sgt->sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) buf->bpl * (dev->height >> 1), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) buf->bpl, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev->height >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dprintk(2, "[%p/%d] buffer_init - %dx%d %dbpp 0x%08x - dma=0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) buf, buf->vb.vb2_buf.index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev->width, dev->height, dev->fmt->depth, dev->fmt->fourcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) (unsigned long)buf->risc.dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static void buffer_finish(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct cx23885_buffer *buf = container_of(vbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct cx23885_buffer, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) cx23885_free_buffer(vb->vb2_queue->drv_priv, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * The risc program for each buffer works as follows: it starts with a simple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * 'JUMP to addr + 12', which is effectively a NOP. Then the code to DMA the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * buffer follows and at the end we have a JUMP back to the start + 12 (skipping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * the initial JUMP).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * This is the risc program of the first buffer to be queued if the active list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * is empty and it just keeps DMAing this buffer without generating any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * If a new buffer is added then the initial JUMP in the code for that buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * will generate an interrupt which signals that the previous buffer has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * DMAed successfully and that it can be returned to userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * It also sets the final jump of the previous buffer to the start of the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * buffer, thus chaining the new buffer into the DMA chain. This is a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * atomic u32 write, so there is no race condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * The end-result of all this that you only get an interrupt when a buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * is ready, so the control flow is very easy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void buffer_queue(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct cx23885_buffer *buf = container_of(vbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct cx23885_buffer, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct cx23885_buffer *prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct cx23885_dmaqueue *q = &dev->vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* add jump to start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) spin_lock_irqsave(&dev->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (list_empty(&q->active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) list_add_tail(&buf->queue, &q->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dprintk(2, "[%p/%d] buffer_queue - first active\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) buf, buf->vb.vb2_buf.index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) prev = list_entry(q->active.prev, struct cx23885_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) list_add_tail(&buf->queue, &q->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dprintk(2, "[%p/%d] buffer_queue - append to active\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) buf, buf->vb.vb2_buf.index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) spin_unlock_irqrestore(&dev->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct cx23885_dev *dev = q->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct cx23885_dmaqueue *dmaq = &dev->vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct cx23885_buffer *buf = list_entry(dmaq->active.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct cx23885_buffer, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) cx23885_start_video_dma(dev, dmaq, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void cx23885_stop_streaming(struct vb2_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct cx23885_dev *dev = q->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct cx23885_dmaqueue *dmaq = &dev->vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) cx_clear(VID_A_DMA_CTL, 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) spin_lock_irqsave(&dev->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) while (!list_empty(&dmaq->active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct cx23885_buffer *buf = list_entry(dmaq->active.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct cx23885_buffer, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) list_del(&buf->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) spin_unlock_irqrestore(&dev->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct vb2_ops cx23885_video_qops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .queue_setup = queue_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .buf_prepare = buffer_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .buf_finish = buffer_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .buf_queue = buffer_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .wait_prepare = vb2_ops_wait_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .wait_finish = vb2_ops_wait_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .start_streaming = cx23885_start_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .stop_streaming = cx23885_stop_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* VIDEO IOCTLS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) f->fmt.pix.width = dev->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) f->fmt.pix.height = dev->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) f->fmt.pix.field = dev->field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) f->fmt.pix.pixelformat = dev->fmt->fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) f->fmt.pix.bytesperline =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) (f->fmt.pix.width * dev->fmt->depth) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) f->fmt.pix.sizeimage =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) f->fmt.pix.height * f->fmt.pix.bytesperline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct cx23885_fmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) enum v4l2_field field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int maxw, maxh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) fmt = format_by_fourcc(f->fmt.pix.pixelformat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (NULL == fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) field = f->fmt.pix.field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) maxw = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) maxh = norm_maxh(dev->tvnorm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (V4L2_FIELD_ANY == field) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) field = (f->fmt.pix.height > maxh/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ? V4L2_FIELD_INTERLACED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) : V4L2_FIELD_BOTTOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) switch (field) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case V4L2_FIELD_TOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case V4L2_FIELD_BOTTOM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) maxh = maxh / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case V4L2_FIELD_INTERLACED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case V4L2_FIELD_SEQ_TB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case V4L2_FIELD_SEQ_BT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) field = V4L2_FIELD_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) f->fmt.pix.field = field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) v4l_bound_align_image(&f->fmt.pix.width, 48, maxw, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) &f->fmt.pix.height, 32, maxh, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) f->fmt.pix.bytesperline =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) (f->fmt.pix.width * fmt->depth) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) f->fmt.pix.sizeimage =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) f->fmt.pix.height * f->fmt.pix.bytesperline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct v4l2_subdev_format format = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .which = V4L2_SUBDEV_FORMAT_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dprintk(2, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) err = vidioc_try_fmt_vid_cap(file, priv, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (0 != err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (vb2_is_busy(&dev->vb2_vidq) || vb2_is_busy(&dev->vb2_vbiq) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) vb2_is_busy(&dev->vb2_mpegq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev->width = f->fmt.pix.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev->height = f->fmt.pix.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev->field = f->fmt.pix.field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dprintk(2, "%s() width=%d height=%d field=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev->width, dev->height, dev->field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) v4l2_fill_mbus_format(&format.format, &f->fmt.pix, MEDIA_BUS_FMT_FIXED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) call_all(dev, pad, set_fmt, NULL, &format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) v4l2_fill_pix_format(&f->fmt.pix, &format.format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* set_fmt overwrites f->fmt.pix.field, restore it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) f->fmt.pix.field = dev->field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int vidioc_querycap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct v4l2_capability *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) strscpy(cap->driver, "cx23885", sizeof(cap->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) strscpy(cap->card, cx23885_boards[dev->board].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) sizeof(cap->card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) cap->capabilities = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) V4L2_CAP_AUDIO | V4L2_CAP_VBI_CAPTURE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) V4L2_CAP_VIDEO_CAPTURE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) V4L2_CAP_DEVICE_CAPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) switch (dev->board) { /* i2c device tuners */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case CX23885_BOARD_HAUPPAUGE_HVR5525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cap->capabilities |= V4L2_CAP_TUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (dev->tuner_type != TUNER_ABSENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) cap->capabilities |= V4L2_CAP_TUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct v4l2_fmtdesc *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (unlikely(f->index >= ARRAY_SIZE(formats)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) f->pixelformat = formats[f->index].fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int vidioc_g_pixelaspect(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int type, struct v4l2_fract *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) bool is_50hz = dev->tvnorm & V4L2_STD_625_50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) f->numerator = is_50hz ? 54 : 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) f->denominator = is_50hz ? 59 : 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static int vidioc_g_selection(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct v4l2_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) switch (sel->target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case V4L2_SEL_TGT_CROP_BOUNDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case V4L2_SEL_TGT_CROP_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) sel->r.width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) sel->r.height = norm_maxh(dev->tvnorm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int vidioc_g_std(struct file *file, void *priv, v4l2_std_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) *id = dev->tvnorm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id tvnorms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return cx23885_set_tvnorm(dev, tvnorms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const char *iname[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [CX23885_VMUX_COMPOSITE1] = "Composite1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [CX23885_VMUX_COMPOSITE2] = "Composite2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [CX23885_VMUX_COMPOSITE3] = "Composite3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) [CX23885_VMUX_COMPOSITE4] = "Composite4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) [CX23885_VMUX_SVIDEO] = "S-Video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) [CX23885_VMUX_COMPONENT] = "Component",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) [CX23885_VMUX_TELEVISION] = "Television",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) [CX23885_VMUX_CABLE] = "Cable TV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) [CX23885_VMUX_DVB] = "DVB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) [CX23885_VMUX_DEBUG] = "for debug only",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) unsigned int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) n = i->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (n >= MAX_CX23885_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (0 == INPUT(n)->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) i->index = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) i->type = V4L2_INPUT_TYPE_CAMERA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) strscpy(i->name, iname[INPUT(n)->type], sizeof(i->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) i->std = CX23885_NORMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if ((CX23885_VMUX_TELEVISION == INPUT(n)->type) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) (CX23885_VMUX_CABLE == INPUT(n)->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) i->type = V4L2_INPUT_TYPE_TUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) i->audioset = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Two selectable audio inputs for non-tv inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) i->audioset = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (dev->input == n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* enum'd input matches our configured input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * Ask the video decoder to process the call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * and give it an oppertunity to update the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * status field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) call_all(dev, video, g_input_status, &i->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static int vidioc_enum_input(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct v4l2_input *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return cx23885_enum_input(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) int cx23885_get_input(struct file *file, void *priv, unsigned int *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) *i = dev->input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dprintk(1, "%s() returns %d\n", __func__, *i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return cx23885_get_input(file, priv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int cx23885_set_input(struct file *file, void *priv, unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dprintk(1, "%s(%d)\n", __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (i >= MAX_CX23885_INPUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dprintk(1, "%s() -EINVAL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (INPUT(i)->type == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) cx23885_video_mux(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* By default establish the default audio input for the card also */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Caller is free to use VIDIOC_S_AUDIO to override afterwards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) cx23885_audio_mux(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return cx23885_set_input(file, priv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int vidioc_log_status(struct file *file, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) call_all(dev, core, log_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int cx23885_query_audinput(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct v4l2_audio *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const char *iname[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) [0] = "Baseband L/R 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) [1] = "Baseband L/R 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) [2] = "TV",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) unsigned int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) n = i->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (n >= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) memset(i, 0, sizeof(*i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) i->index = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) strscpy(i->name, iname[n], sizeof(i->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) i->capability = V4L2_AUDCAP_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int vidioc_enum_audinput(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct v4l2_audio *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return cx23885_query_audinput(file, priv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int vidioc_g_audinput(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct v4l2_audio *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if ((CX23885_VMUX_TELEVISION == INPUT(dev->input)->type) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) (CX23885_VMUX_CABLE == INPUT(dev->input)->type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) i->index = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) i->index = dev->audinput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dprintk(1, "%s(input=%d)\n", __func__, i->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return cx23885_query_audinput(file, priv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int vidioc_s_audinput(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) const struct v4l2_audio *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if ((CX23885_VMUX_TELEVISION == INPUT(dev->input)->type) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) (CX23885_VMUX_CABLE == INPUT(dev->input)->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return i->index != 2 ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (i->index > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dprintk(1, "%s(%d)\n", __func__, i->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev->audinput = i->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* Skip the audio defaults from the cards struct, caller wants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * directly touch the audio mux hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) cx23885_flatiron_mux(dev, dev->audinput + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int vidioc_g_tuner(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct v4l2_tuner *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) switch (dev->board) { /* i2c device tuners */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case CX23885_BOARD_HAUPPAUGE_HVR5525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (dev->tuner_type == TUNER_ABSENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (0 != t->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) strscpy(t->name, "Television", sizeof(t->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) call_all(dev, tuner, g_tuner, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int vidioc_s_tuner(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) const struct v4l2_tuner *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) switch (dev->board) { /* i2c device tuners */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) case CX23885_BOARD_HAUPPAUGE_HVR5525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (dev->tuner_type == TUNER_ABSENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (0 != t->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Update the A/V core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) call_all(dev, tuner, s_tuner, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int vidioc_g_frequency(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) switch (dev->board) { /* i2c device tuners */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) case CX23885_BOARD_HAUPPAUGE_HVR5525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (dev->tuner_type == TUNER_ABSENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) f->type = V4L2_TUNER_ANALOG_TV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) f->frequency = dev->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) call_all(dev, tuner, g_frequency, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int cx23885_set_freq(struct cx23885_dev *dev, const struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct v4l2_ctrl *mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int old_mute_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) switch (dev->board) { /* i2c device tuners */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) case CX23885_BOARD_HAUPPAUGE_HVR5525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (dev->tuner_type == TUNER_ABSENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (unlikely(f->tuner != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev->freq = f->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* I need to mute audio here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) mute = v4l2_ctrl_find(&dev->ctrl_handler, V4L2_CID_AUDIO_MUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (mute) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) old_mute_val = v4l2_ctrl_g_ctrl(mute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!old_mute_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) v4l2_ctrl_s_ctrl(mute, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) call_all(dev, tuner, s_frequency, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* When changing channels it is required to reset TVAUDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* I need to unmute audio here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (old_mute_val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) v4l2_ctrl_s_ctrl(mute, old_mute_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static int cx23885_set_freq_via_ops(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) const struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct v4l2_ctrl *mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int old_mute_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct vb2_dvb_frontend *vfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct analog_parameters params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .mode = V4L2_TUNER_ANALOG_TV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .audmode = V4L2_TUNER_MODE_STEREO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .std = dev->tvnorm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .frequency = f->frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dev->freq = f->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* I need to mute audio here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) mute = v4l2_ctrl_find(&dev->ctrl_handler, V4L2_CID_AUDIO_MUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (mute) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) old_mute_val = v4l2_ctrl_g_ctrl(mute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (!old_mute_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) v4l2_ctrl_s_ctrl(mute, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* If HVR1850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dprintk(1, "%s() frequency=%d tuner=%d std=0x%llx\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) params.frequency, f->tuner, params.std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) vfe = vb2_dvb_get_frontend(&dev->ts2.frontends, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (!vfe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) fe = vfe->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if ((dev->board == CX23885_BOARD_HAUPPAUGE_HVR1850) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1255_22111) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1265_K4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) (dev->board == CX23885_BOARD_HAUPPAUGE_HVR5525) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_DVB) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) fe = &dev->ts1.analog_fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (fe && fe->ops.tuner_ops.set_analog_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) call_all(dev, video, s_std, dev->tvnorm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) fe->ops.tuner_ops.set_analog_params(fe, ¶ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) pr_err("%s() No analog tuner, aborting\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* When changing channels it is required to reset TVAUDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* I need to unmute audio here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (old_mute_val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) v4l2_ctrl_s_ctrl(mute, old_mute_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) int cx23885_set_frequency(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) const struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) switch (dev->board) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case CX23885_BOARD_HAUPPAUGE_HVR1255:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case CX23885_BOARD_HAUPPAUGE_HVR1850:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case CX23885_BOARD_HAUPPAUGE_HVR5525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ret = cx23885_set_freq_via_ops(dev, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ret = cx23885_set_freq(dev, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int vidioc_s_frequency(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) const struct v4l2_frequency *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return cx23885_set_frequency(file, priv, f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int cx23885_video_irq(struct cx23885_dev *dev, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) u32 mask, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) mask = cx_read(VID_A_INT_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (0 == (status & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) cx_write(VID_A_INT_STAT, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* risc op code error, fifo overflow or line sync detection error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if ((status & VID_BC_MSK_OPC_ERR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) (status & VID_BC_MSK_SYNC) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) (status & VID_BC_MSK_OF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (status & VID_BC_MSK_OPC_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) VID_BC_MSK_OPC_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) pr_warn("%s: video risc op code error\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) cx23885_sram_channel_dump(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) &dev->sram_channels[SRAM_CH01]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (status & VID_BC_MSK_SYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dprintk(7, " (VID_BC_MSK_SYNC 0x%08x) video lines miss-match\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) VID_BC_MSK_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (status & VID_BC_MSK_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dprintk(7, " (VID_BC_MSK_OF 0x%08x) fifo overflow\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) VID_BC_MSK_OF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (status & VID_BC_MSK_RISCI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) spin_lock(&dev->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) count = cx_read(VID_A_GPCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) cx23885_video_wakeup(dev, &dev->vidq, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) spin_unlock(&dev->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) handled++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* Allow the VBI framework to process it's payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) handled += cx23885_vbi_irq(dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* ----------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* exported stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static const struct v4l2_file_operations video_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .open = v4l2_fh_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .release = vb2_fop_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .read = vb2_fop_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .poll = vb2_fop_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .unlocked_ioctl = video_ioctl2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .mmap = vb2_fop_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static const struct v4l2_ioctl_ops video_ioctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .vidioc_querycap = vidioc_querycap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .vidioc_g_fmt_vbi_cap = cx23885_vbi_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .vidioc_try_fmt_vbi_cap = cx23885_vbi_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .vidioc_s_fmt_vbi_cap = cx23885_vbi_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .vidioc_reqbufs = vb2_ioctl_reqbufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .vidioc_querybuf = vb2_ioctl_querybuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .vidioc_qbuf = vb2_ioctl_qbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .vidioc_dqbuf = vb2_ioctl_dqbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .vidioc_streamon = vb2_ioctl_streamon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .vidioc_streamoff = vb2_ioctl_streamoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .vidioc_g_pixelaspect = vidioc_g_pixelaspect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .vidioc_g_selection = vidioc_g_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .vidioc_s_std = vidioc_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .vidioc_g_std = vidioc_g_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .vidioc_enum_input = vidioc_enum_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .vidioc_g_input = vidioc_g_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .vidioc_s_input = vidioc_s_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .vidioc_log_status = vidioc_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .vidioc_g_tuner = vidioc_g_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .vidioc_s_tuner = vidioc_s_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .vidioc_g_frequency = vidioc_g_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .vidioc_s_frequency = vidioc_s_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .vidioc_g_chip_info = cx23885_g_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .vidioc_g_register = cx23885_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .vidioc_s_register = cx23885_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .vidioc_enumaudio = vidioc_enum_audinput,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .vidioc_g_audio = vidioc_g_audinput,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .vidioc_s_audio = vidioc_s_audinput,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static struct video_device cx23885_vbi_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static struct video_device cx23885_video_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .name = "cx23885-video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .fops = &video_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .ioctl_ops = &video_ioctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .tvnorms = CX23885_NORMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) void cx23885_video_unregister(struct cx23885_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) cx23885_irq_remove(dev, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (dev->vbi_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (video_is_registered(dev->vbi_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) video_unregister_device(dev->vbi_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) video_device_release(dev->vbi_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev->vbi_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (dev->video_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (video_is_registered(dev->video_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) video_unregister_device(dev->video_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) video_device_release(dev->video_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) dev->video_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (dev->audio_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) cx23885_audio_unregister(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int cx23885_video_register(struct cx23885_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct vb2_queue *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* Initialize VBI template */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) cx23885_vbi_template = cx23885_video_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) strscpy(cx23885_vbi_template.name, "cx23885-vbi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) sizeof(cx23885_vbi_template.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dev->tvnorm = V4L2_STD_NTSC_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dev->fmt = format_by_fourcc(V4L2_PIX_FMT_YUYV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) dev->field = V4L2_FIELD_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dev->width = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dev->height = norm_maxh(dev->tvnorm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* init video dma queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) INIT_LIST_HEAD(&dev->vidq.active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* init vbi dma queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) INIT_LIST_HEAD(&dev->vbiq.active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) cx23885_irq_add_enable(dev, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if ((TUNER_ABSENT != dev->tuner_type) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ((dev->tuner_bus == 0) || (dev->tuner_bus == 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct v4l2_subdev *sd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (dev->tuner_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) sd = v4l2_i2c_new_subdev(&dev->v4l2_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) &dev->i2c_bus[dev->tuner_bus].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) "tuner", dev->tuner_addr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) sd = v4l2_i2c_new_subdev(&dev->v4l2_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) &dev->i2c_bus[dev->tuner_bus].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) "tuner", 0, v4l2_i2c_tuner_addrs(ADDRS_TV));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (sd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct tuner_setup tun_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) memset(&tun_setup, 0, sizeof(tun_setup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) tun_setup.mode_mask = T_ANALOG_TV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) tun_setup.type = dev->tuner_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) tun_setup.addr = v4l2_i2c_subdev_addr(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) tun_setup.tuner_callback = cx23885_tuner_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) v4l2_subdev_call(sd, tuner, s_type_addr, &tun_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if ((dev->board == CX23885_BOARD_LEADTEK_WINFAST_PXTV1200) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) (dev->board == CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct xc2028_ctrl ctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .fname = XC2028_DEFAULT_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .max_len = 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct v4l2_priv_tun_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .tuner = dev->tuner_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .priv = &ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) v4l2_subdev_call(sd, tuner, s_config, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (dev->board == CX23885_BOARD_AVERMEDIA_HC81R) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct xc2028_ctrl ctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .fname = "xc3028L-v36.fw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .max_len = 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct v4l2_priv_tun_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .tuner = dev->tuner_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .priv = &ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) v4l2_subdev_call(sd, tuner, s_config, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* initial device configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) mutex_lock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) cx23885_set_tvnorm(dev, dev->tvnorm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) cx23885_video_mux(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) cx23885_audio_mux(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) mutex_unlock(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) q = &dev->vb2_vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) q->gfp_flags = GFP_DMA32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) q->min_buffers_needed = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) q->drv_priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) q->buf_struct_size = sizeof(struct cx23885_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) q->ops = &cx23885_video_qops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) q->mem_ops = &vb2_dma_sg_memops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) q->lock = &dev->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) q->dev = &dev->pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) err = vb2_queue_init(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) goto fail_unreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) q = &dev->vb2_vbiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) q->type = V4L2_BUF_TYPE_VBI_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) q->gfp_flags = GFP_DMA32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) q->min_buffers_needed = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) q->drv_priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) q->buf_struct_size = sizeof(struct cx23885_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) q->ops = &cx23885_vbi_qops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) q->mem_ops = &vb2_dma_sg_memops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) q->lock = &dev->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) q->dev = &dev->pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) err = vb2_queue_init(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) goto fail_unreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* register Video device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) dev->video_dev = cx23885_vdev_init(dev, dev->pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) &cx23885_video_template, "video");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dev->video_dev->queue = &dev->vb2_vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) dev->video_dev->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) V4L2_CAP_AUDIO | V4L2_CAP_VIDEO_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) switch (dev->board) { /* i2c device tuners */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) case CX23885_BOARD_HAUPPAUGE_HVR5525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) dev->video_dev->device_caps |= V4L2_CAP_TUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (dev->tuner_type != TUNER_ABSENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dev->video_dev->device_caps |= V4L2_CAP_TUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) err = video_register_device(dev->video_dev, VFL_TYPE_VIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) video_nr[dev->nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) pr_info("%s: can't register video device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) goto fail_unreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) pr_info("%s: registered device %s [v4l2]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) dev->name, video_device_node_name(dev->video_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* register VBI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) dev->vbi_dev = cx23885_vdev_init(dev, dev->pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) &cx23885_vbi_template, "vbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) dev->vbi_dev->queue = &dev->vb2_vbiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dev->vbi_dev->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) V4L2_CAP_AUDIO | V4L2_CAP_VBI_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) switch (dev->board) { /* i2c device tuners */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) case CX23885_BOARD_HAUPPAUGE_HVR5525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) dev->vbi_dev->device_caps |= V4L2_CAP_TUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (dev->tuner_type != TUNER_ABSENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) dev->vbi_dev->device_caps |= V4L2_CAP_TUNER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) err = video_register_device(dev->vbi_dev, VFL_TYPE_VBI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) vbi_nr[dev->nr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) pr_info("%s: can't register vbi device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) goto fail_unreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) pr_info("%s: registered device %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dev->name, video_device_node_name(dev->vbi_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /* Register ALSA audio device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dev->audio_dev = cx23885_audio_register(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) fail_unreg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) cx23885_video_unregister(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
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