^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Conexant CX23885 PCIe bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "cx23885.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static unsigned int vbibufs = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) module_param(vbibufs, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MODULE_PARM_DESC(vbibufs, "number of vbi buffers, range 2-32");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static unsigned int vbi_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) module_param(vbi_debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MODULE_PARM_DESC(vbi_debug, "enable debug messages [vbi]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define dprintk(level, fmt, arg...)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) do { if (vbi_debug >= level)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) printk(KERN_DEBUG pr_fmt("%s: vbi:" fmt), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VBI_LINE_LENGTH 1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VBI_NTSC_LINE_COUNT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VBI_PAL_LINE_COUNT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int cx23885_vbi_fmt(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct v4l2_format *f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct cx23885_dev *dev = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) f->fmt.vbi.sampling_rate = 27000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) f->fmt.vbi.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) f->fmt.vbi.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (dev->tvnorm & V4L2_STD_525_60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* ntsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) f->fmt.vbi.start[0] = V4L2_VBI_ITU_525_F1_START + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) f->fmt.vbi.start[1] = V4L2_VBI_ITU_525_F2_START + 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) f->fmt.vbi.count[0] = VBI_NTSC_LINE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) f->fmt.vbi.count[1] = VBI_NTSC_LINE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } else if (dev->tvnorm & V4L2_STD_625_50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* pal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) f->fmt.vbi.start[0] = V4L2_VBI_ITU_625_F1_START + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) f->fmt.vbi.start[1] = V4L2_VBI_ITU_625_F2_START + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) f->fmt.vbi.count[0] = VBI_PAL_LINE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) f->fmt.vbi.count[1] = VBI_PAL_LINE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* We're given the Video Interrupt status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * The cx23885_video_irq() func has already validated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * the potential error bits, we just need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * deal with vbi payload and return indication if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * we actually processed any payload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (status & VID_BC_MSK_VBI_RISCI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dprintk(1, "%s() VID_BC_MSK_VBI_RISCI1\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) spin_lock(&dev->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) count = cx_read(VBI_A_GPCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) cx23885_video_wakeup(dev, &dev->vbiq, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) spin_unlock(&dev->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) handled++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int cx23885_start_vbi_dma(struct cx23885_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct cx23885_dmaqueue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct cx23885_buffer *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dprintk(1, "%s()\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* setup fifo + format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) VBI_LINE_LENGTH, buf->risc.dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* reset counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cx_write(VID_A_VBI_CTRL, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cx_write(VBI_A_GPCNT_CTL, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) q->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* enable irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) cx23885_irq_add_enable(dev, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cx_set(VID_A_INT_MSK, 0x000022);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* start dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) cx_set(DEV_CNTRL2, (1<<5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cx_set(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int queue_setup(struct vb2_queue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int *num_buffers, unsigned int *num_planes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int sizes[], struct device *alloc_devs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct cx23885_dev *dev = q->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned lines = VBI_PAL_LINE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (dev->tvnorm & V4L2_STD_525_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) lines = VBI_NTSC_LINE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *num_planes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) sizes[0] = lines * VBI_LINE_LENGTH * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int buffer_prepare(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct cx23885_buffer *buf = container_of(vbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct cx23885_buffer, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned lines = VBI_PAL_LINE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (dev->tvnorm & V4L2_STD_525_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) lines = VBI_NTSC_LINE_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (vb2_plane_size(vb, 0) < lines * VBI_LINE_LENGTH * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) vb2_set_plane_payload(vb, 0, lines * VBI_LINE_LENGTH * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cx23885_risc_vbibuffer(dev->pci, &buf->risc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) sgt->sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0, VBI_LINE_LENGTH * lines,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) VBI_LINE_LENGTH, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) lines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void buffer_finish(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct cx23885_buffer *buf = container_of(vbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct cx23885_buffer, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cx23885_free_buffer(vb->vb2_queue->drv_priv, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * The risc program for each buffer works as follows: it starts with a simple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * 'JUMP to addr + 12', which is effectively a NOP. Then the code to DMA the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * buffer follows and at the end we have a JUMP back to the start + 12 (skipping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * the initial JUMP).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * This is the risc program of the first buffer to be queued if the active list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * is empty and it just keeps DMAing this buffer without generating any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * If a new buffer is added then the initial JUMP in the code for that buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * will generate an interrupt which signals that the previous buffer has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * DMAed successfully and that it can be returned to userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * It also sets the final jump of the previous buffer to the start of the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * buffer, thus chaining the new buffer into the DMA chain. This is a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * atomic u32 write, so there is no race condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * The end-result of all this that you only get an interrupt when a buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * is ready, so the control flow is very easy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void buffer_queue(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct cx23885_dev *dev = vb->vb2_queue->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct cx23885_buffer *buf = container_of(vbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct cx23885_buffer, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct cx23885_buffer *prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct cx23885_dmaqueue *q = &dev->vbiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (list_empty(&q->active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) spin_lock_irqsave(&dev->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) list_add_tail(&buf->queue, &q->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_unlock_irqrestore(&dev->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dprintk(2, "[%p/%d] vbi_queue - first active\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) buf, buf->vb.vb2_buf.index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) prev = list_entry(q->active.prev, struct cx23885_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spin_lock_irqsave(&dev->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) list_add_tail(&buf->queue, &q->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spin_unlock_irqrestore(&dev->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dprintk(2, "[%p/%d] buffer_queue - append to active\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) buf, buf->vb.vb2_buf.index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct cx23885_dev *dev = q->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct cx23885_dmaqueue *dmaq = &dev->vbiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct cx23885_buffer *buf = list_entry(dmaq->active.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct cx23885_buffer, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) cx23885_start_vbi_dma(dev, dmaq, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void cx23885_stop_streaming(struct vb2_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct cx23885_dev *dev = q->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct cx23885_dmaqueue *dmaq = &dev->vbiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) cx_clear(VID_A_DMA_CTL, 0x22); /* FIFO and RISC enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) spin_lock_irqsave(&dev->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) while (!list_empty(&dmaq->active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct cx23885_buffer *buf = list_entry(dmaq->active.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct cx23885_buffer, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) list_del(&buf->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) spin_unlock_irqrestore(&dev->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) const struct vb2_ops cx23885_vbi_qops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .queue_setup = queue_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .buf_prepare = buffer_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .buf_finish = buffer_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .buf_queue = buffer_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .wait_prepare = vb2_ops_wait_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .wait_finish = vb2_ops_wait_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .start_streaming = cx23885_start_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .stop_streaming = cx23885_stop_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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