Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for the Conexant CX23885 PCIe bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _CX23885_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define _CX23885_REG_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) Address Map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 0x00000000 -> 0x00009000   TX SRAM  (Fifos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 0x00010000 -> 0x00013c00   RX SRAM  CMDS + CDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) EACH CMDS struct is 0x80 bytes long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) DMAx_PTR1 = 0x03040 address of first cluster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) DMAx_PTR2 = 0x10600 address of the CDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) DMAx_CNT1 = cluster size in (bytes >> 4) -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) DMAx_CNT2 = total cdt size for all entries >> 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) Cluster Descriptor entry = 4 DWORDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  DWORD 0 -> ptr to cluster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  DWORD 1 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  DWORD 2 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  DWORD 3 Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) Channel manager Data Structure entry = 20 DWORD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)   0  IntialProgramCounterLow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)   1  IntialProgramCounterHigh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)   2  ClusterDescriptorTableBase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)   3  ClusterDescriptorTableSize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)   4  InstructionQueueBase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)   5  InstructionQueueSize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) ...  Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  19  Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Risc Instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RISC_CNT_INC		 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RISC_CNT_RESET		 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RISC_IRQ1		 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RISC_IRQ2		 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RISC_EOL		 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RISC_SOL		 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define RISC_WRITE		 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define RISC_SKIP		 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RISC_JUMP		 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RISC_SYNC		 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RISC_RESYNC		 0x80008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RISC_READ		 0x90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RISC_WRITERM		 0xB0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RISC_WRITECM		 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define RISC_WRITECR		 0xD0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define RISC_WRITEC		 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define RISC_READC		 0xA0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* Audio and Video Core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define HOST_REG1		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define HOST_REG2		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define HOST_REG3		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* Chip Configuration Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CHIP_CTRL		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define AFE_CTRL		0x00000104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define VID_PLL_INT_POST	0x00000108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define VID_PLL_FRAC		0x0000010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define AUX_PLL_INT_POST	0x00000110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define AUX_PLL_FRAC		0x00000114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SYS_PLL_INT_POST	0x00000118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SYS_PLL_FRAC		0x0000011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PIN_CTRL		0x00000120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define AUD_IO_CTRL		0x00000124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define AUD_LOCK1		0x00000128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define AUD_LOCK2		0x0000012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define POWER_CTRL		0x00000130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define AFE_DIAG_CTRL1		0x00000134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define AFE_DIAG_CTRL3		0x0000013C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PLL_DIAG_CTRL		0x00000140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define AFE_CLK_OUT_CTRL	0x00000144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define DLL1_DIAG_CTRL		0x0000015C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* GPIO[23:19] Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define GPIO2_OUT_EN_REG	0x00000160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* GPIO[23:19] Data Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define GPIO2			0x00000164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IFADC_CTRL		0x00000180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* Infrared Remote Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define IR_CNTRL_REG	0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define IR_TXCLK_REG	0x00000204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define IR_RXCLK_REG	0x00000208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IR_CDUTY_REG	0x0000020C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define IR_STAT_REG	0x00000210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define IR_IRQEN_REG	0x00000214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define IR_FILTR_REG	0x00000218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IR_FIFO_REG	0x0000023C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Video Decoder Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MODE_CTRL		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OUT_CTRL1		0x00000404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OUT_CTRL2		0x00000408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GEN_STAT		0x0000040C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define INT_STAT_MASK		0x00000410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LUMA_CTRL		0x00000414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HSCALE_CTRL		0x00000418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VSCALE_CTRL		0x0000041C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CHROMA_CTRL		0x00000420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VBI_LINE_CTRL1		0x00000424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VBI_LINE_CTRL2		0x00000428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VBI_LINE_CTRL3		0x0000042C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VBI_LINE_CTRL4		0x00000430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VBI_LINE_CTRL5		0x00000434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VBI_FC_CFG		0x00000438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VBI_MISC_CFG1		0x0000043C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VBI_MISC_CFG2		0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VBI_PAY1		0x00000444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VBI_PAY2		0x00000448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VBI_CUST1_CFG1		0x0000044C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VBI_CUST1_CFG2		0x00000450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VBI_CUST1_CFG3		0x00000454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VBI_CUST2_CFG1		0x00000458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VBI_CUST2_CFG2		0x0000045C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VBI_CUST2_CFG3		0x00000460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VBI_CUST3_CFG1		0x00000464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VBI_CUST3_CFG2		0x00000468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VBI_CUST3_CFG3		0x0000046C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HORIZ_TIM_CTRL		0x00000470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VERT_TIM_CTRL		0x00000474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SRC_COMB_CFG		0x00000478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CHROMA_VBIOFF_CFG	0x0000047C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define FIELD_COUNT		0x00000480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MISC_TIM_CTRL		0x00000484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DFE_CTRL1		0x00000488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DFE_CTRL2		0x0000048C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DFE_CTRL3		0x00000490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PLL_CTRL		0x00000494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HTL_CTRL		0x00000498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define COMB_CTRL		0x0000049C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CRUSH_CTRL		0x000004A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SOFT_RST_CTRL		0x000004A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CX885_VERSION		0x000004B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VBI_PASS_CTRL		0x000004BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Audio Decoder Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* 8051 Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DL_CTL		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define STD_DET_STATUS	0x00000804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define STD_DET_CTL	0x00000808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DW8051_INT	0x0000080C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GENERAL_CTL	0x00000810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AAGC_CTL	0x00000814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DEMATRIX_CTL	0x000008CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PATH1_CTL1	0x000008D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PATH1_VOL_CTL	0x000008D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PATH1_EQ_CTL	0x000008D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PATH1_SC_CTL	0x000008DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PATH2_CTL1	0x000008E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PATH2_VOL_CTL	0x000008E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PATH2_EQ_CTL	0x000008E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PATH2_SC_CTL	0x000008EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Sample Rate Converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SRC_CTL		0x000008F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SRC_LF_COEF	0x000008F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SRC1_CTL	0x000008F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SRC2_CTL	0x000008FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SRC3_CTL	0x00000900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SRC4_CTL	0x00000904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SRC5_CTL	0x00000908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SRC6_CTL	0x0000090C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BAND_OUT_SEL	0x00000910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define I2S_N_CTL	0x00000914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define I2S_OUT_CTL	0x00000918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AUTOCONFIG_REG	0x000009C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Audio ADC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DSM_CTRL1	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DSM_CTRL2	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CHP_EN_CTRL	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CHP_CLK_CTRL1	0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CHP_CLK_CTRL2	0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BG_REF_CTRL	0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SD2_SW_CTRL1	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SD2_SW_CTRL2	0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SD2_BIAS_CTRL	0x0000000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AMP_BIAS_CTRL	0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CH_PWR_CTRL1	0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define FLD_CH_SEL      (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CH_PWR_CTRL2	0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DSM_STATUS1	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DSM_STATUS2	0x00000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DIG_CTL1	0x00000012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DIG_CTL2	0x00000013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define I2S_TX_CFG	0x0000001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DEV_CNTRL2	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define PCI_MSK_IR        (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PCI_MSK_AV_CORE   (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PCI_MSK_GPIO1     (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define PCI_MSK_GPIO0     (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PCI_MSK_APB_DMA   (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define PCI_MSK_AL_WR     (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PCI_MSK_AL_RD     (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PCI_MSK_RISC_WR   (1 <<  9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PCI_MSK_RISC_RD   (1 <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PCI_MSK_AUD_EXT   (1 <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PCI_MSK_AUD_INT   (1 <<  3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PCI_MSK_VID_C     (1 <<  2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PCI_MSK_VID_B     (1 <<  1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PCI_MSK_VID_A      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PCI_INT_MSK	0x00040010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PCI_INT_STAT	0x00040014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PCI_INT_MSTAT	0x00040018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define VID_A_INT_MSK	0x00040020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define VID_A_INT_STAT	0x00040024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define VID_A_INT_MSTAT	0x00040028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define VID_A_INT_SSTAT	0x0004002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define VID_B_INT_MSK	0x00040030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define VID_B_MSK_BAD_PKT     (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define VID_B_MSK_VBI_OPC_ERR (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define VID_B_MSK_OPC_ERR     (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define VID_B_MSK_VBI_SYNC    (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define VID_B_MSK_SYNC        (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define VID_B_MSK_VBI_OF      (1 <<  9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define VID_B_MSK_OF          (1 <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define VID_B_MSK_VBI_RISCI2  (1 <<  5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define VID_B_MSK_RISCI2      (1 <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define VID_B_MSK_VBI_RISCI1  (1 <<  1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define VID_B_MSK_RISCI1       1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define VID_B_INT_STAT	0x00040034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define VID_B_INT_MSTAT	0x00040038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define VID_B_INT_SSTAT	0x0004003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define VID_B_MSK_BAD_PKT (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define VID_B_MSK_OPC_ERR (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define VID_B_MSK_SYNC    (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define VID_B_MSK_OF      (1 <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define VID_B_MSK_RISCI2  (1 <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define VID_B_MSK_RISCI1   1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define VID_C_MSK_BAD_PKT (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define VID_C_MSK_OPC_ERR (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define VID_C_MSK_SYNC    (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define VID_C_MSK_OF      (1 <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define VID_C_MSK_RISCI2  (1 <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define VID_C_MSK_RISCI1   1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* A superset for testing purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define VID_BC_MSK_BAD_PKT (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define VID_BC_MSK_OPC_ERR (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define VID_BC_MSK_SYNC    (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define VID_BC_MSK_OF      (1 <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define VID_BC_MSK_VBI_RISCI2 (1 <<  5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define VID_BC_MSK_RISCI2  (1 <<  4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define VID_BC_MSK_VBI_RISCI1 (1 <<  1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define VID_BC_MSK_RISCI1   1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define VID_C_INT_MSK	0x00040040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define VID_C_INT_STAT	0x00040044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define VID_C_INT_MSTAT	0x00040048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define VID_C_INT_SSTAT	0x0004004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define AUDIO_INT_INT_MSK	0x00040050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define AUDIO_INT_INT_STAT	0x00040054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define AUDIO_INT_INT_MSTAT	0x00040058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define AUDIO_INT_INT_SSTAT	0x0004005C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define AUDIO_EXT_INT_MSK	0x00040060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define AUDIO_EXT_INT_STAT	0x00040064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define AUDIO_EXT_INT_MSTAT	0x00040068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define AUDIO_EXT_INT_SSTAT	0x0004006C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Bits [7:0] set in both TC_REQ and TC_REQ_SET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  * indicate a stall in the RISC engine for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  * particular rider traffic class. This causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  * the 885 and 888 bridges (unknown about 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  * to become inoperable. Setting bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  * TC_REQ_SET resets the corresponding bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * in TC_REQ (and TC_REQ_SET) allowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  * operation to continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TC_REQ		0x00040090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TC_REQ_SET	0x00040094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define RDR_CFG0	0x00050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define RDR_CFG1	0x00050004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define RDR_CFG2	0x00050008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define RDR_RDRCTL1	0x0005030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define RDR_TLCTL0	0x00050318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* APB DMAC Current Buffer Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DMA1_PTR1	0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DMA2_PTR1	0x00100004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DMA3_PTR1	0x00100008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DMA4_PTR1	0x0010000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DMA5_PTR1	0x00100010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DMA6_PTR1	0x00100014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DMA7_PTR1	0x00100018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DMA8_PTR1	0x0010001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* APB DMAC Current Table Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DMA1_PTR2	0x00100040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DMA2_PTR2	0x00100044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DMA3_PTR2	0x00100048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DMA4_PTR2	0x0010004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DMA5_PTR2	0x00100050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DMA6_PTR2	0x00100054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DMA7_PTR2	0x00100058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define DMA8_PTR2	0x0010005C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* APB DMAC Buffer Limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DMA1_CNT1	0x00100080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DMA2_CNT1	0x00100084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DMA3_CNT1	0x00100088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DMA4_CNT1	0x0010008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DMA5_CNT1	0x00100090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DMA6_CNT1	0x00100094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DMA7_CNT1	0x00100098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DMA8_CNT1	0x0010009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* APB DMAC Table Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DMA1_CNT2	0x001000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DMA2_CNT2	0x001000C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DMA3_CNT2	0x001000C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DMA4_CNT2	0x001000CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DMA5_CNT2	0x001000D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DMA6_CNT2	0x001000D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DMA7_CNT2	0x001000D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DMA8_CNT2	0x001000DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Timer Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define TM_CNT_LDW	0x00110000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TM_CNT_UW	0x00110004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define TM_LMT_LDW	0x00110008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TM_LMT_UW	0x0011000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define GP0_IO		0x00110010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define GPIO_ISM	0x00110014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SOFT_RESET	0x0011001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* GPIO (417 Microsoftcontroller) RW Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MC417_RWD	0x00110020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* GPIO (417 Microsoftcontroller) Output Enable, Low Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MC417_OEN	0x00110024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MC417_CTL	0x00110028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define ALT_PIN_OUT_SEL 0x0011002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CLK_DELAY	0x00110048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define PAD_CTRL	0x0011004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Video A Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define VID_A_GPCNT		0x00130020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define VBI_A_GPCNT		0x00130024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define VID_A_GPCNT_CTL		0x00130030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define VBI_A_GPCNT_CTL		0x00130034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define VID_A_DMA_CTL		0x00130040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define VID_A_VIP_CTRL		0x00130080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define VID_A_PIXEL_FRMT	0x00130084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define VID_A_VBI_CTRL		0x00130088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Video B Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define VID_B_DMA		0x00130100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define VBI_B_DMA		0x00130108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define VID_B_GPCNT		0x00130120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define VBI_B_GPCNT		0x00130124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define VID_B_GPCNT_CTL		0x00130134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define VBI_B_GPCNT_CTL		0x00130138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define VID_B_DMA_CTL		0x00130140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define VID_B_SRC_SEL		0x00130144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define VID_B_LNGTH		0x00130150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define VID_B_HW_SOP_CTL	0x00130154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define VID_B_GEN_CTL		0x00130158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define VID_B_BD_PKT_STATUS	0x0013015C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define VID_B_SOP_STATUS	0x00130160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define VID_B_FIFO_OVFL_STAT	0x00130164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define VID_B_VLD_MISC		0x00130168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define VID_B_TS_CLK_EN		0x0013016C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define VID_B_VIP_CTRL		0x00130180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define VID_B_PIXEL_FRMT	0x00130184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Video C Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define VID_C_DMA		0x00130200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define VBI_C_DMA		0x00130208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define VID_C_GPCNT		0x00130220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define VID_C_GPCNT_CTL		0x00130230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define VBI_C_GPCNT_CTL		0x00130234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define VID_C_DMA_CTL		0x00130240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define VID_C_LNGTH		0x00130250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define VID_C_HW_SOP_CTL	0x00130254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define VID_C_GEN_CTL		0x00130258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define VID_C_BD_PKT_STATUS	0x0013025C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define VID_C_SOP_STATUS	0x00130260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define VID_C_FIFO_OVFL_STAT	0x00130264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define VID_C_VLD_MISC		0x00130268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define VID_C_TS_CLK_EN		0x0013026C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Internal Audio Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define AUD_INT_A_GPCNT		0x00140020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define AUD_INT_B_GPCNT		0x00140024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define AUD_INT_A_GPCNT_CTL	0x00140030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define AUD_INT_B_GPCNT_CTL	0x00140034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define AUD_INT_DMA_CTL		0x00140040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define AUD_INT_A_LNGTH		0x00140050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define AUD_INT_B_LNGTH		0x00140054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define AUD_INT_A_MODE		0x00140058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define AUD_INT_B_MODE		0x0014005C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* External Audio Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define AUD_EXT_DMA		0x00140100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define AUD_EXT_GPCNT		0x00140120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define AUD_EXT_GPCNT_CTL	0x00140130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define AUD_EXT_DMA_CTL		0x00140140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define AUD_EXT_LNGTH		0x00140150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define AUD_EXT_A_MODE		0x00140158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* I2C Bus 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define I2C1_ADDR	0x00180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define I2C1_WDATA	0x00180004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define I2C1_CTRL	0x00180008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define I2C1_RDATA	0x0018000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define I2C1_STAT	0x00180010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* I2C Bus 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define I2C2_ADDR	0x00190000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define I2C2_WDATA	0x00190004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define I2C2_CTRL	0x00190008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define I2C2_RDATA	0x0019000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define I2C2_STAT	0x00190010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* I2C Bus 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define I2C3_ADDR	0x001A0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define I2C3_WDATA	0x001A0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define I2C3_CTRL	0x001A0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define I2C3_RDATA	0x001A000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define I2C3_STAT	0x001A0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define UART_CTL	0x001B0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define UART_BRD	0x001B0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define UART_ISR	0x001B000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define UART_CNT	0x001B0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #endif /* _CX23885_REG_H_ */