^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Conexant CX23885 PCIe bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "cx23885.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/dvb_ca_en50221.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "s5h1409.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "s5h1411.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "mt2131.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "tda8290.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "tda18271.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "lgdt330x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "xc4000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "xc5000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "max2165.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "tda10048.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "tuner-xc2028.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "tuner-simple.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "dib7000p.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "dib0070.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "dibx000_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "zl10353.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "stv0900.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "stv0900_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "stv6110.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "lnbh24.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "cx24116.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "cx24117.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "cimax2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "lgs8gxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "netup-eeprom.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "netup-init.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "lgdt3305.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "atbm8830.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "ts2020.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "ds3000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "cx23885-f300.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "altera-ci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "stv0367.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "drxk.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include "mt2063.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "stv090x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include "stb6100.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "stb6100_cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include "tda10071.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include "a8293.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include "mb86a20s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include "si2165.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include "si2168.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include "si2157.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include "sp2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include "m88ds3103.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include "m88rs6000t.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include "lgdt3306a.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static unsigned int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define dprintk(level, fmt, arg...)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) do { if (debug >= level)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) printk(KERN_DEBUG pr_fmt("%s dvb: " fmt), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __func__, ##arg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static unsigned int alt_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) module_param(alt_tuner, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int queue_setup(struct vb2_queue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int *num_buffers, unsigned int *num_planes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int sizes[], struct device *alloc_devs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct cx23885_tsport *port = q->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) port->ts_packet_size = 188 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) port->ts_packet_count = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *num_planes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) sizes[0] = port->ts_packet_size * port->ts_packet_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *num_buffers = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int buffer_prepare(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct cx23885_buffer *buf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) container_of(vbuf, struct cx23885_buffer, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return cx23885_buf_prepare(buf, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void buffer_finish(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct cx23885_dev *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct cx23885_buffer *buf = container_of(vbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct cx23885_buffer, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cx23885_free_buffer(dev, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void buffer_queue(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct cx23885_buffer *buf = container_of(vbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct cx23885_buffer, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) cx23885_buf_queue(port, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct vb2_dvb_frontends *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct vb2_dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) f = &port->frontends;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (f->gate <= 1) /* undefined or fe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) fe = vb2_dvb_get_frontend(f, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) fe = vb2_dvb_get_frontend(f, f->gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct cx23885_tsport *port = q->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct cx23885_dmaqueue *dmaq = &port->mpegq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct cx23885_buffer *buf = list_entry(dmaq->active.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct cx23885_buffer, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cx23885_start_dma(port, dmaq, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void cx23885_stop_streaming(struct vb2_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct cx23885_tsport *port = q->drv_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cx23885_cancel_buffers(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct vb2_ops dvb_qops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .queue_setup = queue_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .buf_prepare = buffer_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .buf_finish = buffer_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .buf_queue = buffer_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .wait_prepare = vb2_ops_wait_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .wait_finish = vb2_ops_wait_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .start_streaming = cx23885_start_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .stop_streaming = cx23885_stop_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct s5h1409_config hauppauge_generic_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .demod_address = 0x32 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .output_mode = S5H1409_SERIAL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .gpio = S5H1409_GPIO_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .qam_if = 44000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .inversion = S5H1409_INVERSION_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .status_mode = S5H1409_DEMODLOCKING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct tda10048_config hauppauge_hvr1200_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .demod_address = 0x10 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .output_mode = TDA10048_SERIAL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .fwbulkwritelen = TDA10048_BULKWRITE_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .inversion = TDA10048_INVERSION_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .dtv6_if_freq_khz = TDA10048_IF_3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .dtv7_if_freq_khz = TDA10048_IF_3800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .dtv8_if_freq_khz = TDA10048_IF_4300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .clk_freq_khz = TDA10048_CLK_16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct tda10048_config hauppauge_hvr1210_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .demod_address = 0x10 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .output_mode = TDA10048_SERIAL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .fwbulkwritelen = TDA10048_BULKWRITE_200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .inversion = TDA10048_INVERSION_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .dtv6_if_freq_khz = TDA10048_IF_3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .dtv7_if_freq_khz = TDA10048_IF_3500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .dtv8_if_freq_khz = TDA10048_IF_4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .clk_freq_khz = TDA10048_CLK_16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct s5h1409_config hauppauge_ezqam_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .demod_address = 0x32 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .output_mode = S5H1409_SERIAL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .gpio = S5H1409_GPIO_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .qam_if = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .inversion = S5H1409_INVERSION_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .status_mode = S5H1409_DEMODLOCKING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct s5h1409_config hauppauge_hvr1800lp_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .demod_address = 0x32 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .output_mode = S5H1409_SERIAL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .gpio = S5H1409_GPIO_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .qam_if = 44000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .inversion = S5H1409_INVERSION_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .status_mode = S5H1409_DEMODLOCKING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct s5h1409_config hauppauge_hvr1500_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .demod_address = 0x32 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .output_mode = S5H1409_SERIAL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .gpio = S5H1409_GPIO_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .inversion = S5H1409_INVERSION_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .status_mode = S5H1409_DEMODLOCKING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct mt2131_config hauppauge_generic_tunerconfig = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct lgdt330x_config fusionhdtv_5_express = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .demod_chip = LGDT3303,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .serial_mpeg = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct s5h1409_config hauppauge_hvr1500q_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .demod_address = 0x32 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .output_mode = S5H1409_SERIAL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .gpio = S5H1409_GPIO_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .qam_if = 44000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .inversion = S5H1409_INVERSION_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .status_mode = S5H1409_DEMODLOCKING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct s5h1409_config dvico_s5h1409_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .demod_address = 0x32 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .output_mode = S5H1409_SERIAL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .gpio = S5H1409_GPIO_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .qam_if = 44000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .inversion = S5H1409_INVERSION_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .status_mode = S5H1409_DEMODLOCKING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .mpeg_timing = S5H1409_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct s5h1411_config dvico_s5h1411_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .output_mode = S5H1411_SERIAL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .gpio = S5H1411_GPIO_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .qam_if = S5H1411_IF_44000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .vsb_if = S5H1411_IF_44000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .inversion = S5H1411_INVERSION_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .status_mode = S5H1411_DEMODLOCKING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .mpeg_timing = S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct s5h1411_config hcw_s5h1411_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .output_mode = S5H1411_SERIAL_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .gpio = S5H1411_GPIO_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .vsb_if = S5H1411_IF_44000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .qam_if = S5H1411_IF_4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .inversion = S5H1411_INVERSION_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .status_mode = S5H1411_DEMODLOCKING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .mpeg_timing = S5H1411_MPEGTIMING_CONTINUOUS_NONINVERTING_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .i2c_address = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .if_khz = 5380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct xc5000_config dvico_xc5000_tunerconfig = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .i2c_address = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .if_khz = 5380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct tda829x_config tda829x_no_probe = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .probe_tuner = TDA829X_DONT_PROBE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct tda18271_std_map hauppauge_tda18271_std_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .if_lvl = 6, .rfagc_top = 0x37 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .if_lvl = 6, .rfagc_top = 0x37 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .if_lvl = 1, .rfagc_top = 0x37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .if_lvl = 1, .rfagc_top = 0x37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .if_lvl = 1, .rfagc_top = 0x37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct tda18271_config hauppauge_tda18271_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .std_map = &hauppauge_tda18271_std_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .gate = TDA18271_GATE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .output_opt = TDA18271_OUTPUT_LT_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct tda18271_config hauppauge_hvr1200_tuner_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .std_map = &hauppauge_hvr1200_tda18271_std_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .gate = TDA18271_GATE_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .output_opt = TDA18271_OUTPUT_LT_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct tda18271_config hauppauge_hvr1210_tuner_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .gate = TDA18271_GATE_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .output_opt = TDA18271_OUTPUT_LT_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct tda18271_config hauppauge_hvr4400_tuner_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .gate = TDA18271_GATE_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .output_opt = TDA18271_OUTPUT_LT_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct tda18271_std_map hauppauge_hvr127x_std_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .if_lvl = 1, .rfagc_top = 0x58 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .if_lvl = 1, .rfagc_top = 0x58 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct tda18271_config hauppauge_hvr127x_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .std_map = &hauppauge_hvr127x_std_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .output_opt = TDA18271_OUTPUT_LT_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct lgdt3305_config hauppauge_lgdt3305_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .i2c_addr = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .mpeg_mode = LGDT3305_MPEG_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .deny_i2c_rptr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .spectral_inversion = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .qam_if_khz = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .vsb_if_khz = 3250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct dibx000_agc_config xc3028_agc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) BAND_VHF | BAND_UHF, /* band_caps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * P_agc_nb_est=2, P_agc_write=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 712, /* inv_gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 21, /* time_stabiliz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0, /* alpha_level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 118, /* thlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0, /* wbd_inv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 2867, /* wbd_ref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0, /* wbd_sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 2, /* wbd_alpha */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0, /* agc1_max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0, /* agc1_min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 39718, /* agc2_max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 9930, /* agc2_min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0, /* agc1_pt1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0, /* agc1_pt2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 0, /* agc1_pt3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0, /* agc1_slope1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0, /* agc1_slope2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0, /* agc2_pt1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 128, /* agc2_pt2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 29, /* agc2_slope1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 29, /* agc2_slope2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 17, /* alpha_mant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 27, /* alpha_exp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 23, /* beta_mant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 51, /* beta_exp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 1, /* perform_agc_softsplit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* PLL Configuration for COFDM BW_MHz = 8.000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * With external clock = 30.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct dibx000_bandwidth_config xc3028_bw_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 60000, /* internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 30000, /* sampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 1, /* pll_cfg: prediv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 8, /* pll_cfg: ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 3, /* pll_cfg: range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 1, /* pll_cfg: reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0, /* pll_cfg: bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0, /* misc: refdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0, /* misc: bypclk_div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 1, /* misc: IO_CLK_en_core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 1, /* misc: ADClkSrc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0, /* misc: modulo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 20452225, /* timf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 30000000 /* xtal_hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .output_mpeg2_in_188_bytes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .hostbus_diversity = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .tuner_is_baseband = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .update_lna = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .agc_config_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .agc = &xc3028_agc_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .bw = &xc3028_bw_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .pwm_freq_div = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .agc_control = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .spur_protect = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .output_mode = OUTMODE_MPEG2_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static struct zl10353_config dvico_fusionhdtv_xc3028 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .demod_address = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .if2 = 45600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .no_tuner = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .disable_i2c_gate_ctrl = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static struct stv0900_reg stv0900_ts_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { R0900_TSGENERAL, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { R0900_P1_TSSPEED, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { R0900_P2_TSSPEED, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { R0900_P1_TSCFGM, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { R0900_P2_TSCFGM, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { R0900_P1_TSCFGH, 0xe0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { R0900_P2_TSCFGH, 0xe0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { R0900_P1_TSCFGL, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { R0900_P2_TSCFGL, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { 0xffff, 0xff }, /* terminate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct stv0900_config netup_stv0900_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .demod_address = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .demod_mode = 1, /* dual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .xtal = 8000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .diseqc_mode = 2,/* 2/3 PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .ts_config_regs = stv0900_ts_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .tun1_maddress = 0,/* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .tun2_maddress = 3,/* 0x63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .tun1_adc = 1,/* 1 Vpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .tun2_adc = 1,/* 1 Vpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static struct stv6110_config netup_stv6110_tunerconfig_a = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .i2c_address = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .mclk = 16000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .clk_div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .gain = 8, /* +16 dB - maximum gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static struct stv6110_config netup_stv6110_tunerconfig_b = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .i2c_address = 0x63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .mclk = 16000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .clk_div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .gain = 8, /* +16 dB - maximum gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static struct cx24116_config tbs_cx24116_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .demod_address = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static struct cx24117_config tbs_cx24117_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .demod_address = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static struct ds3000_config tevii_ds3000_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .demod_address = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct ts2020_config tevii_ts2020_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .tuner_address = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .clk_out_div = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .frequency_div = 1146000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static struct cx24116_config dvbworld_cx24116_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .demod_address = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .prod = LGS8GXX_PROD_LGS8GL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .demod_address = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .serial_ts = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .ts_clk_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .ts_clk_gated = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .if_clk_freq = 30400, /* 30.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .if_freq = 5380, /* 5.38 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .if_neg_center = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .ext_adc = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .adc_signed = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .if_neg_edge = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static struct xc5000_config mygica_x8506_xc5000_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .i2c_address = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .if_khz = 5380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static struct mb86a20s_config mygica_x8507_mb86a20s_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .demod_address = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct xc5000_config mygica_x8507_xc5000_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .i2c_address = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .if_khz = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static struct stv090x_config prof_8000_stv090x_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .device = STV0903,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .demod_mode = STV090x_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .clk_mode = STV090x_CLK_EXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .xtal = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .address = 0x6A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .repeater_level = STV090x_RPTLEVEL_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .adc1_range = STV090x_ADC_2Vpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .diseqc_envelope_mode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .tuner_get_frequency = stb6100_get_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .tuner_set_frequency = stb6100_set_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .tuner_set_bandwidth = stb6100_set_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .tuner_get_bandwidth = stb6100_get_bandwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static struct stb6100_config prof_8000_stb6100_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .tuner_address = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .refclock = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static struct lgdt3306a_config hauppauge_quadHD_ATSC_a_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .i2c_addr = 0x59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .qam_if_khz = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .vsb_if_khz = 3250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .deny_i2c_rptr = 1, /* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .spectral_inversion = 0, /* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .mpeg_mode = LGDT3306A_MPEG_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .tpclk_edge = LGDT3306A_TPCLK_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .tpvalid_polarity = LGDT3306A_TP_VALID_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .xtalMHz = 25, /* 24 or 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static struct lgdt3306a_config hauppauge_quadHD_ATSC_b_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .i2c_addr = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .qam_if_khz = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .vsb_if_khz = 3250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .deny_i2c_rptr = 1, /* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .spectral_inversion = 0, /* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .mpeg_mode = LGDT3306A_MPEG_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .tpclk_edge = LGDT3306A_TPCLK_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .tpvalid_polarity = LGDT3306A_TP_VALID_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .xtalMHz = 25, /* 24 or 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int p8000_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct cx23885_tsport *port = fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct cx23885_dev *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (voltage == SEC_VOLTAGE_18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) cx_write(MC417_RWD, 0x00001e00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) else if (voltage == SEC_VOLTAGE_13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) cx_write(MC417_RWD, 0x00001a00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) cx_write(MC417_RWD, 0x00001800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int dvbsky_t9580_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct cx23885_tsport *port = fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct cx23885_dev *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case SEC_VOLTAGE_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) cx23885_gpio_set(dev, GPIO_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) cx23885_gpio_clear(dev, GPIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case SEC_VOLTAGE_18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) cx23885_gpio_set(dev, GPIO_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) cx23885_gpio_set(dev, GPIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case SEC_VOLTAGE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) cx23885_gpio_clear(dev, GPIO_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) cx23885_gpio_clear(dev, GPIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* call the frontend set_voltage function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) port->fe_set_voltage(fe, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int dvbsky_s952_portc_set_voltage(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) enum fe_sec_voltage voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct cx23885_tsport *port = fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct cx23885_dev *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) cx23885_gpio_enable(dev, GPIO_12 | GPIO_13, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) switch (voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case SEC_VOLTAGE_13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cx23885_gpio_set(dev, GPIO_13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) cx23885_gpio_clear(dev, GPIO_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case SEC_VOLTAGE_18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) cx23885_gpio_set(dev, GPIO_13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) cx23885_gpio_set(dev, GPIO_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) case SEC_VOLTAGE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) cx23885_gpio_clear(dev, GPIO_13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) cx23885_gpio_clear(dev, GPIO_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* call the frontend set_voltage function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return port->fe_set_voltage(fe, voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int cx23885_sp2_ci_ctrl(void *priv, u8 read, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u8 data, int *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* MC417 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define SP2_DATA 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define SP2_WR 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define SP2_RD 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define SP2_ACK 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define SP2_ADHI 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define SP2_ADLO 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define SP2_CS1 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define SP2_CS0 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define SP2_EN_ALL 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define SP2_CTRL_OFF (SP2_CS1 | SP2_CS0 | SP2_WR | SP2_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct cx23885_tsport *port = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct cx23885_dev *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) mutex_lock(&dev->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* write addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) cx_write(MC417_OEN, SP2_EN_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) cx_write(MC417_RWD, SP2_CTRL_OFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) SP2_ADLO | (0xff & addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) cx_clear(MC417_RWD, SP2_ADLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) cx_write(MC417_RWD, SP2_CTRL_OFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) SP2_ADHI | (0xff & (addr >> 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) cx_clear(MC417_RWD, SP2_ADHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* data in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) cx_write(MC417_OEN, SP2_EN_ALL | SP2_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* data out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) cx_write(MC417_RWD, SP2_CTRL_OFF | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* chip select 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) cx_clear(MC417_RWD, SP2_CS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) cx_clear(MC417_RWD, (read) ? SP2_RD : SP2_WR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* wait for a maximum of 1 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) timeout = jiffies + msecs_to_jiffies(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) while (!time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) tmp = cx_read(MC417_RWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if ((tmp & SP2_ACK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) usleep_range(50, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) cx_set(MC417_RWD, SP2_CTRL_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) *mem = tmp & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) mutex_unlock(&dev->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (!read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (*mem < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct dtv_frontend_properties *p = &fe->dtv_property_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct cx23885_tsport *port = fe->dvb->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct cx23885_dev *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) switch (dev->board) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case CX23885_BOARD_HAUPPAUGE_HVR1275:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) switch (p->modulation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case VSB_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) cx23885_gpio_clear(dev, GPIO_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case QAM_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) case QAM_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) cx23885_gpio_set(dev, GPIO_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) case CX23885_BOARD_MYGICA_X8506:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) case CX23885_BOARD_MYGICA_X8507:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case CX23885_BOARD_MAGICPRO_PROHDTVE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Select Digital TV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) cx23885_gpio_set(dev, GPIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Call the real set_frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (port->set_frontend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return port->set_frontend(fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct dvb_frontend *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) port->set_frontend = fe->ops.set_frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) fe->ops.set_frontend = cx23885_dvb_set_frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .prod = LGS8GXX_PROD_LGS8G75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .demod_address = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .serial_ts = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .ts_clk_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .ts_clk_gated = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .if_clk_freq = 30400, /* 30.4 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .if_freq = 6500, /* 6.50 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .if_neg_center = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .ext_adc = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .adc_signed = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .adc_vpp = 2, /* 1.6 Vpp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .if_neg_edge = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .i2c_address = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .if_khz = 6500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .prod = ATBM8830_PROD_8830,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .demod_address = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .serial_ts = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .ts_sampling_edge = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .ts_clk_gated = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .osc_clk_freq = 30400, /* in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .if_freq = 0, /* zero IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .zif_swap_iq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .agc_min = 0x2E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .agc_max = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .agc_hold_loop = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .i2c_address = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .osc_clk = 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .prod = ATBM8830_PROD_8830,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .demod_address = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .serial_ts = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .ts_sampling_edge = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .ts_clk_gated = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .osc_clk_freq = 30400, /* in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .if_freq = 0, /* zero IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .zif_swap_iq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .agc_min = 0x2E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .agc_max = 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .agc_hold_loop = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .i2c_address = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .osc_clk = 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static struct stv0367_config netup_stv0367_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .demod_address = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .xtal = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .if_khz = 4500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .if_iq_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .ts_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .clk_pol = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .demod_address = 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .xtal = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .if_khz = 4500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .if_iq_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .ts_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .clk_pol = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static struct xc5000_config netup_xc5000_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .i2c_address = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .if_khz = 4500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .i2c_address = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .if_khz = 4500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static struct drxk_config terratec_drxk_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .adr = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .no_i2c_bridge = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .adr = 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .no_i2c_bridge = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static struct mt2063_config terratec_mt2063_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .tuner_address = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .tuner_address = 0x67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const struct tda10071_platform_data hauppauge_tda10071_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .clk = 40444000, /* 40.444 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .i2c_wr_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .ts_mode = TDA10071_TS_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .pll_multiplier = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .tuner_i2c_addr = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static const struct m88ds3103_config dvbsky_t9580_m88ds3103_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .i2c_addr = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .clock = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .i2c_wr_max = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .clock_out = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .ts_mode = M88DS3103_TS_PARALLEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .ts_clk = 16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .ts_clk_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .lnb_en_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .lnb_hv_pol = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .agc = 0x99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const struct m88ds3103_config dvbsky_s950c_m88ds3103_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .i2c_addr = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .clock = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .i2c_wr_max = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .clock_out = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .ts_mode = M88DS3103_TS_CI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .ts_clk = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .ts_clk_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .lnb_en_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .lnb_hv_pol = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .agc = 0x99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const struct m88ds3103_config hauppauge_hvr5525_m88ds3103_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .i2c_addr = 0x69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .clock = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .i2c_wr_max = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .ts_mode = M88DS3103_TS_PARALLEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .ts_clk = 16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .ts_clk_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .agc = 0x99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static struct lgdt3306a_config hauppauge_hvr1265k4_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .i2c_addr = 0x59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .qam_if_khz = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .vsb_if_khz = 3250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .deny_i2c_rptr = 1, /* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .spectral_inversion = 0, /* Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .mpeg_mode = LGDT3306A_MPEG_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .tpclk_edge = LGDT3306A_TPCLK_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .tpvalid_polarity = LGDT3306A_TP_VALID_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .xtalMHz = 25, /* 24 or 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct cx23885_dev *dev = (struct cx23885_dev *)device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) unsigned long timeout = jiffies + msecs_to_jiffies(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) uint32_t mem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) mem = cx_read(MC417_RWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) cx_set(MC417_OEN, ALT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) mem &= ~ALT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) mem |= (data & ALT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) mem |= ALT_AD_RG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) mem &= ~ALT_AD_RG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) mem &= ~ALT_CS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) mem = (mem & ~ALT_RD) | ALT_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) mem = (mem & ~ALT_WR) | ALT_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) cx_write(MC417_RWD, mem); /* start RW cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mem = cx_read(MC417_RWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if ((mem & ALT_RDY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return mem & ALT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct dib7000p_ops *dib7000p_ops = fe->sec_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return dib7000p_ops->set_gpio(fe, 8, 0, !onoff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int dib7070_tuner_sleep(struct dvb_frontend *fe, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static struct dib0070_config dib7070p_dib0070_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .reset = dib7070_tuner_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .sleep = dib7070_tuner_sleep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .clock_khz = 12000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .freq_offset_khz_vhf = 550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* .flip_chip = 1, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* DIB7070 generic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static struct dibx000_agc_config dib7070_agc_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .inv_gain = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .time_stabiliz = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .alpha_level = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .thlock = 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .wbd_inv = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .wbd_ref = 3530,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .wbd_sel = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .wbd_alpha = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .agc1_max = 65535,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .agc1_min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .agc2_max = 65535,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .agc2_min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .agc1_pt1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .agc1_pt2 = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .agc1_pt3 = 183,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .agc1_slope1 = 206,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .agc1_slope2 = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .agc2_pt1 = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .agc2_pt2 = 152,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .agc2_slope1 = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .agc2_slope2 = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .alpha_mant = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .alpha_exp = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .beta_mant = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .beta_exp = 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .perform_agc_softsplit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .internal = 60000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .sampling = 15000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .pll_prediv = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .pll_ratio = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .pll_range = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .pll_reset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .pll_bypass = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .enable_refdiv = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .bypclk_div = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .IO_CLK_en_core = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .ADClkSrc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .modulo = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* refsel, sel, freq_15k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .ifreq = (0 << 25) | 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .timf = 20452225,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .xtal_hz = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static struct dib7000p_config dib7070p_dib7000p_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* .output_mode = OUTMODE_MPEG2_FIFO, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .output_mode = OUTMODE_MPEG2_SERIAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .output_mpeg2_in_188_bytes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .agc_config_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .agc = &dib7070_agc_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .bw = &dib7070_bw_config_12_mhz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .tuner_is_baseband = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .spur_protect = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .gpio_dir = 0xfcef, /* DIB7000P_GPIO_DEFAULT_DIRECTIONS, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .gpio_val = 0x0110, /* DIB7000P_GPIO_DEFAULT_VALUES, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .hostbus_diversity = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static int dvb_register_ci_mac(struct cx23885_tsport *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct cx23885_dev *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct i2c_client *client_ci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct vb2_dvb_frontend *fe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (!fe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) switch (dev->board) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static struct netup_card_info cinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) memcpy(port->frontends.adapter.proposed_mac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) cinfo.port[port->nr - 1].mac, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) pr_info("NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) port->nr, port->frontends.adapter.proposed_mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) netup_ci_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct altera_ci_config netup_ci_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .dev = dev,/* magic number to identify*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .adapter = &port->frontends.adapter,/* for CI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .demux = &fe0->dvb.demux,/* for hw pid filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .fpga_rw = netup_altera_fpga_rw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) altera_ci_init(&netup_ci_cfg, port->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) case CX23885_BOARD_TEVII_S470: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) u8 eeprom[256]; /* 24C02 i2c eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (port->nr != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* Read entire EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) pr_info("TeVii S470 MAC= %pM\n", eeprom + 0xa0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case CX23885_BOARD_DVBSKY_T9580:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) case CX23885_BOARD_DVBSKY_S950:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) case CX23885_BOARD_DVBSKY_S952:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) case CX23885_BOARD_DVBSKY_T982: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) u8 eeprom[256]; /* 24C02 i2c eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (port->nr > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Read entire EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) sizeof(eeprom));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) pr_info("%s port %d MAC address: %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) cx23885_boards[dev->board].name, port->nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) eeprom + 0xc0 + (port->nr-1) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xc0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) (port->nr-1) * 8, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) case CX23885_BOARD_DVBSKY_S950C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) case CX23885_BOARD_DVBSKY_T980C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) case CX23885_BOARD_TT_CT2_4500_CI: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u8 eeprom[256]; /* 24C02 i2c eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct sp2_config sp2_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct i2c_board_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct cx23885_i2c *i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* attach CI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) memset(&sp2_config, 0, sizeof(sp2_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) sp2_config.dvb_adap = &port->frontends.adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) sp2_config.priv = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) sp2_config.ci_control = cx23885_sp2_ci_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) strscpy(info.type, "sp2", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) info.addr = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) info.platform_data = &sp2_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) client_ci = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (!i2c_client_has_driver(client_ci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (!try_module_get(client_ci->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) i2c_unregister_device(client_ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) port->i2c_client_ci = client_ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (port->nr != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* Read entire EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) sizeof(eeprom));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) pr_info("%s MAC address: %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) cx23885_boards[dev->board].name, eeprom + 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xc0, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static int dvb_register(struct cx23885_tsport *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct dib7000p_ops dib7000p_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct cx23885_dev *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct vb2_dvb_frontend *fe0, *fe1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct si2168_config si2168_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct si2165_platform_data si2165_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct si2157_config si2157_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct ts2020_config ts2020_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct m88ds3103_platform_data m88ds3103_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct m88rs6000t_config m88rs6000t_config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct a8293_platform_data a8293_pdata = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct i2c_board_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct i2c_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct i2c_client *client_demod = NULL, *client_tuner = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct i2c_client *client_sec = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int (*p_set_voltage)(struct dvb_frontend *fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) enum fe_sec_voltage voltage) = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) int mfe_shared = 0; /* bus not shared by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Get the first frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (!fe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* init struct vb2_dvb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) fe0->dvb.name = dev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* multi-frontend gate control is undefined or defaults to fe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) port->frontends.gate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* Sets the gate control callback to be used by i2c command calls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) port->gate_ctrl = cx23885_dvb_gate_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* init frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) switch (dev->board) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) case CX23885_BOARD_HAUPPAUGE_HVR1250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) fe0->dvb.frontend = dvb_attach(s5h1409_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) &hauppauge_generic_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) dvb_attach(mt2131_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) &hauppauge_generic_tunerconfig, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) case CX23885_BOARD_HAUPPAUGE_HVR1270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) case CX23885_BOARD_HAUPPAUGE_HVR1275:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) &hauppauge_lgdt3305_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) dvb_attach(tda18271_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) 0x60, &dev->i2c_bus[1].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) &hauppauge_hvr127x_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) cx23885_set_frontend_hook(port, fe0->dvb.frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) case CX23885_BOARD_HAUPPAUGE_HVR1255:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) fe0->dvb.frontend = dvb_attach(s5h1411_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) &hcw_s5h1411_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dvb_attach(tda18271_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) 0x60, &dev->i2c_bus[1].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) &hauppauge_tda18271_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) tda18271_attach(&dev->ts1.analog_fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) 0x60, &dev->i2c_bus[1].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) &hauppauge_tda18271_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) case CX23885_BOARD_HAUPPAUGE_HVR1800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) switch (alt_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) fe0->dvb.frontend =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dvb_attach(s5h1409_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) &hauppauge_ezqam_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dvb_attach(tda829x_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) &dev->i2c_bus[1].i2c_adap, 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) &tda829x_no_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) dvb_attach(tda18271_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) 0x60, &dev->i2c_bus[1].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) &hauppauge_tda18271_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) fe0->dvb.frontend =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dvb_attach(s5h1409_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) &hauppauge_generic_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) dvb_attach(mt2131_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) &hauppauge_generic_tunerconfig, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) fe0->dvb.frontend = dvb_attach(s5h1409_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) &hauppauge_hvr1800lp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dvb_attach(mt2131_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) &hauppauge_generic_tunerconfig, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) &fusionhdtv_5_express,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) &i2c_bus->i2c_adap, 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) TUNER_LG_TDVS_H06XF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) i2c_bus = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) fe0->dvb.frontend = dvb_attach(s5h1409_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) &hauppauge_hvr1500q_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) &dev->i2c_bus[0].i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dvb_attach(xc5000_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &hauppauge_hvr1500q_tunerconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) case CX23885_BOARD_HAUPPAUGE_HVR1500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) i2c_bus = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) fe0->dvb.frontend = dvb_attach(s5h1409_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) &hauppauge_hvr1500_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) &dev->i2c_bus[0].i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (fe0->dvb.frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct xc2028_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .i2c_adap = &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .i2c_addr = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static struct xc2028_ctrl ctl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .fname = XC2028_DEFAULT_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .max_len = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .demod = XC3028_FE_OREN538,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) fe = dvb_attach(xc2028_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) fe0->dvb.frontend, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) fe->ops.tuner_ops.set_config(fe, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) case CX23885_BOARD_HAUPPAUGE_HVR1200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) case CX23885_BOARD_HAUPPAUGE_HVR1700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) fe0->dvb.frontend = dvb_attach(tda10048_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) &hauppauge_hvr1200_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) dvb_attach(tda829x_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) &dev->i2c_bus[1].i2c_adap, 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) &tda829x_no_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) dvb_attach(tda18271_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) 0x60, &dev->i2c_bus[1].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) &hauppauge_hvr1200_tuner_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) case CX23885_BOARD_HAUPPAUGE_HVR1210:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) fe0->dvb.frontend = dvb_attach(tda10048_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) &hauppauge_hvr1210_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (fe0->dvb.frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dvb_attach(tda18271_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) 0x60, &dev->i2c_bus[1].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) &hauppauge_hvr1210_tuner_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) case CX23885_BOARD_HAUPPAUGE_HVR1400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (!dvb_attach(dib7000p_attach, &dib7000p_ops))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) 0x12, &hauppauge_hvr1400_dib7000_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (fe0->dvb.frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) struct xc2028_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .i2c_adap = &dev->i2c_bus[1].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .i2c_addr = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static struct xc2028_ctrl ctl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .fname = XC3028L_DEFAULT_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .max_len = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .demod = XC3028_FE_DIBCOM52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* This is true for all demods with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) v36 firmware? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .type = XC2028_D2633,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) fe = dvb_attach(xc2028_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) fe0->dvb.frontend, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) fe->ops.tuner_ops.set_config(fe, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) i2c_bus = &dev->i2c_bus[port->nr - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) fe0->dvb.frontend = dvb_attach(s5h1409_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) &dvico_s5h1409_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) fe0->dvb.frontend = dvb_attach(s5h1411_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) &dvico_s5h1411_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (fe0->dvb.frontend != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) dvb_attach(xc5000_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) &dvico_xc5000_tunerconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) i2c_bus = &dev->i2c_bus[port->nr - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) fe0->dvb.frontend = dvb_attach(zl10353_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) &dvico_fusionhdtv_xc3028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (fe0->dvb.frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct xc2028_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .i2c_adap = &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .i2c_addr = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static struct xc2028_ctrl ctl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .fname = XC2028_DEFAULT_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .max_len = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .demod = XC3028_FE_ZARLINK456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) fe->ops.tuner_ops.set_config(fe, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) i2c_bus = &dev->i2c_bus[port->nr - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* cxusb_ctrl_msg(adap->dev, CMD_DIGITAL, NULL, 0, NULL, 0); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* cxusb_bluebird_gpio_pulse(adap->dev, 0x02, 1); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (!dvb_attach(dib7000p_attach, &dib7000p_ops))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (dib7000p_ops.i2c_enumeration(&i2c_bus->i2c_adap, 1, 0x12, &dib7070p_dib7000p_config) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) pr_warn("Unable to enumerate dib7000p\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap, 0x80, &dib7070p_dib7000p_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (fe0->dvb.frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct i2c_adapter *tun_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) fe0->dvb.frontend->sec_priv = kmemdup(&dib7000p_ops, sizeof(dib7000p_ops), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (!fe0->dvb.frontend->sec_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) tun_i2c = dib7000p_ops.get_i2c_master(fe0->dvb.frontend, DIBX000_I2C_INTERFACE_TUNER, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (!dvb_attach(dib0070_attach, fe0->dvb.frontend, tun_i2c, &dib7070p_dib0070_config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) fe0->dvb.frontend = dvb_attach(zl10353_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) &dvico_fusionhdtv_xc3028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (fe0->dvb.frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct xc2028_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .i2c_adap = &dev->i2c_bus[1].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .i2c_addr = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static struct xc2028_ctrl ctl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .fname = XC2028_DEFAULT_FIRMWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .max_len = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .demod = XC3028_FE_ZARLINK456,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) fe->ops.tuner_ops.set_config(fe, &ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) fe0->dvb.frontend = dvb_attach(zl10353_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) &dvico_fusionhdtv_xc3028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (fe0->dvb.frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct dvb_frontend *fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct xc4000_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .i2c_address = 0x61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .default_pm = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .dvb_amplitude = 134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .set_smoothedcvbs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .if_khz = 4560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) &dev->i2c_bus[1].i2c_adap, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (!fe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) pr_err("%s/2: xc4000 attach failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) case CX23885_BOARD_TBS_6920:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) i2c_bus = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) fe0->dvb.frontend = dvb_attach(cx24116_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) &tbs_cx24116_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (fe0->dvb.frontend != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) case CX23885_BOARD_TBS_6980:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) case CX23885_BOARD_TBS_6981:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) i2c_bus = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* PORT B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) fe0->dvb.frontend = dvb_attach(cx24117_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) &tbs_cx24117_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* PORT C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) fe0->dvb.frontend = dvb_attach(cx24117_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) &tbs_cx24117_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) case CX23885_BOARD_TEVII_S470:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) i2c_bus = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) fe0->dvb.frontend = dvb_attach(ds3000_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) &tevii_ds3000_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (fe0->dvb.frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dvb_attach(ts2020_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) &tevii_ts2020_config, &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) case CX23885_BOARD_DVBWORLD_2005:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) i2c_bus = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) fe0->dvb.frontend = dvb_attach(cx24116_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) &dvbworld_cx24116_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* port B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) fe0->dvb.frontend = dvb_attach(stv0900_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) &netup_stv0900_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) &i2c_bus->i2c_adap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (fe0->dvb.frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (dvb_attach(stv6110_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) &netup_stv6110_tunerconfig_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) &i2c_bus->i2c_adap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (!dvb_attach(lnbh24_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) LNBH24_PCL | LNBH24_TTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) LNBH24_TEN, 0x09))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) pr_err("No LNBH24 found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* port C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) fe0->dvb.frontend = dvb_attach(stv0900_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) &netup_stv0900_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) &i2c_bus->i2c_adap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (fe0->dvb.frontend != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (dvb_attach(stv6110_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) &netup_stv6110_tunerconfig_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) &i2c_bus->i2c_adap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (!dvb_attach(lnbh24_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) LNBH24_PCL | LNBH24_TTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) LNBH24_TEN, 0x0a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) pr_err("No LNBH24 found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) case CX23885_BOARD_MYGICA_X8506:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) i2c_bus2 = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) &mygica_x8506_lgs8gl5_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) dvb_attach(xc5000_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) &i2c_bus2->i2c_adap, &mygica_x8506_xc5000_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) cx23885_set_frontend_hook(port, fe0->dvb.frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) case CX23885_BOARD_MYGICA_X8507:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) i2c_bus2 = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) fe0->dvb.frontend = dvb_attach(mb86a20s_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) &mygica_x8507_mb86a20s_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) dvb_attach(xc5000_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) &i2c_bus2->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) &mygica_x8507_xc5000_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) cx23885_set_frontend_hook(port, fe0->dvb.frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) case CX23885_BOARD_MAGICPRO_PROHDTVE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) i2c_bus2 = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) &magicpro_prohdtve2_lgs8g75_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) dvb_attach(xc5000_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) &i2c_bus2->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) &magicpro_prohdtve2_xc5000_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) cx23885_set_frontend_hook(port, fe0->dvb.frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) case CX23885_BOARD_HAUPPAUGE_HVR1850:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) fe0->dvb.frontend = dvb_attach(s5h1411_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) &hcw_s5h1411_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) dvb_attach(tda18271_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) 0x60, &dev->i2c_bus[0].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) &hauppauge_tda18271_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) tda18271_attach(&dev->ts1.analog_fe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) 0x60, &dev->i2c_bus[1].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) &hauppauge_tda18271_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) case CX23885_BOARD_HAUPPAUGE_HVR1290:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) fe0->dvb.frontend = dvb_attach(s5h1411_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) &hcw_s5h1411_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) dvb_attach(tda18271_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) 0x60, &dev->i2c_bus[0].i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) &hauppauge_tda18271_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) case CX23885_BOARD_MYGICA_X8558PRO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /* port B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) fe0->dvb.frontend = dvb_attach(atbm8830_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) &mygica_x8558pro_atbm8830_cfg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) dvb_attach(max2165_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) &mygic_x8558pro_max2165_cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* port C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) i2c_bus = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) fe0->dvb.frontend = dvb_attach(atbm8830_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) &mygica_x8558pro_atbm8830_cfg2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) dvb_attach(max2165_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) &mygic_x8558pro_max2165_cfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (port->nr > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) mfe_shared = 1;/* MFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) port->frontends.gate = 0;/* not clear for me yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* ports B, C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* MFE frontend 1 DVB-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) &netup_stv0367_config[port->nr - 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (NULL == dvb_attach(xc5000_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) &netup_xc5000_config[port->nr - 1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) /* load xc5000 firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* MFE frontend 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) fe1 = vb2_dvb_get_frontend(&port->frontends, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (fe1 == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /* DVB-C init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) &netup_stv0367_config[port->nr - 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (fe1->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) fe1->dvb.frontend->id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (NULL == dvb_attach(xc5000_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) fe1->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) &netup_xc5000_config[port->nr - 1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) i2c_bus2 = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) /* port b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) fe0->dvb.frontend = dvb_attach(drxk_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) &terratec_drxk_config[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (!dvb_attach(mt2063_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) &terratec_mt2063_config[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) &i2c_bus2->i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* port c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) fe0->dvb.frontend = dvb_attach(drxk_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) &terratec_drxk_config[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (!dvb_attach(mt2063_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) &terratec_mt2063_config[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) &i2c_bus2->i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) case CX23885_BOARD_TEVII_S471:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) i2c_bus = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) fe0->dvb.frontend = dvb_attach(ds3000_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) &tevii_ds3000_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) dvb_attach(ts2020_attach, fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) &tevii_ts2020_config, &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) case CX23885_BOARD_PROF_8000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) fe0->dvb.frontend = dvb_attach(stv090x_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) &prof_8000_stv090x_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) &i2c_bus->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) STV090x_DEMODULATOR_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (!dvb_attach(stb6100_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) &prof_8000_stb6100_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) &i2c_bus->i2c_adap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) case CX23885_BOARD_HAUPPAUGE_HVR4400: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) struct tda10071_platform_data tda10071_pdata = hauppauge_tda10071_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) struct a8293_platform_data a8293_pdata = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) i2c_bus2 = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /* port b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /* attach demod + tuner combo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) memset(&info, 0, sizeof(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) strscpy(info.type, "tda10071_cx24118", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) info.addr = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) info.platform_data = &tda10071_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) request_module("tda10071");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (!i2c_client_has_driver(client_demod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (!try_module_get(client_demod->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) fe0->dvb.frontend = tda10071_pdata.get_dvb_frontend(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) port->i2c_client_demod = client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* attach SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) a8293_pdata.dvb_frontend = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) memset(&info, 0, sizeof(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) strscpy(info.type, "a8293", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) info.addr = 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) info.platform_data = &a8293_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) request_module("a8293");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) client_sec = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (!i2c_client_has_driver(client_sec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (!try_module_get(client_sec->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) i2c_unregister_device(client_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) port->i2c_client_sec = client_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) /* port c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) memset(&si2165_pdata, 0, sizeof(si2165_pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) si2165_pdata.fe = &fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) si2165_pdata.chip_mode = SI2165_MODE_PLL_XTAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) si2165_pdata.ref_freq_hz = 16000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) strscpy(info.type, "si2165", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) info.addr = 0x64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) info.platform_data = &si2165_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (!i2c_client_has_driver(client_demod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (!try_module_get(client_demod->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) port->i2c_client_demod = client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (!dvb_attach(tda18271_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) fe0->dvb.frontend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) 0x60, &i2c_bus2->i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) &hauppauge_hvr4400_tuner_config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) case CX23885_BOARD_HAUPPAUGE_STARBURST: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) struct tda10071_platform_data tda10071_pdata = hauppauge_tda10071_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) struct a8293_platform_data a8293_pdata = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* attach demod + tuner combo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) memset(&info, 0, sizeof(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) strscpy(info.type, "tda10071_cx24118", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) info.addr = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) info.platform_data = &tda10071_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) request_module("tda10071");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (!i2c_client_has_driver(client_demod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) if (!try_module_get(client_demod->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) fe0->dvb.frontend = tda10071_pdata.get_dvb_frontend(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) port->i2c_client_demod = client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) /* attach SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) a8293_pdata.dvb_frontend = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) memset(&info, 0, sizeof(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) strscpy(info.type, "a8293", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) info.addr = 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) info.platform_data = &a8293_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) request_module("a8293");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) client_sec = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (!i2c_client_has_driver(client_sec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (!try_module_get(client_sec->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) i2c_unregister_device(client_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) port->i2c_client_sec = client_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) case CX23885_BOARD_DVBSKY_T9580:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) case CX23885_BOARD_DVBSKY_S950:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) i2c_bus2 = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /* port b - satellite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) fe0->dvb.frontend = dvb_attach(m88ds3103_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) &dvbsky_t9580_m88ds3103_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) &i2c_bus2->i2c_adap, &adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) memset(&ts2020_config, 0, sizeof(ts2020_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ts2020_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ts2020_config.get_agc_pwm = m88ds3103_get_agc_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) strscpy(info.type, "ts2020", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) info.addr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) info.platform_data = &ts2020_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) client_tuner = i2c_new_client_device(adapter, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (!i2c_client_has_driver(client_tuner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* delegate signal strength measurement to tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) fe0->dvb.frontend->ops.read_signal_strength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) * for setting the voltage we need to set GPIOs on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * the card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) port->fe_set_voltage =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) fe0->dvb.frontend->ops.set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) fe0->dvb.frontend->ops.set_voltage =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) dvbsky_t9580_set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) /* port c - terrestrial/cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) memset(&si2168_config, 0, sizeof(si2168_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) si2168_config.i2c_adapter = &adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) si2168_config.fe = &fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) si2168_config.ts_mode = SI2168_TS_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) strscpy(info.type, "si2168", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) info.addr = 0x64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) info.platform_data = &si2168_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (!i2c_client_has_driver(client_demod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) if (!try_module_get(client_demod->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) port->i2c_client_demod = client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) si2157_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) strscpy(info.type, "si2157", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) info.addr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) info.platform_data = &si2157_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) client_tuner = i2c_new_client_device(adapter, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if (!i2c_client_has_driver(client_tuner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) case CX23885_BOARD_DVBSKY_T980C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) case CX23885_BOARD_TT_CT2_4500_CI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) i2c_bus2 = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) memset(&si2168_config, 0, sizeof(si2168_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) si2168_config.i2c_adapter = &adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) si2168_config.fe = &fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) si2168_config.ts_mode = SI2168_TS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) strscpy(info.type, "si2168", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) info.addr = 0x64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) info.platform_data = &si2168_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) client_demod = i2c_new_client_device(&i2c_bus2->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (!i2c_client_has_driver(client_demod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) if (!try_module_get(client_demod->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) port->i2c_client_demod = client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) si2157_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) strscpy(info.type, "si2157", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) info.addr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) info.platform_data = &si2157_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) client_tuner = i2c_new_client_device(adapter, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (!i2c_client_has_driver(client_tuner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) case CX23885_BOARD_DVBSKY_S950C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) i2c_bus2 = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) fe0->dvb.frontend = dvb_attach(m88ds3103_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) &dvbsky_s950c_m88ds3103_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) &i2c_bus2->i2c_adap, &adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) memset(&ts2020_config, 0, sizeof(ts2020_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) ts2020_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ts2020_config.get_agc_pwm = m88ds3103_get_agc_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) strscpy(info.type, "ts2020", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) info.addr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) info.platform_data = &ts2020_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) client_tuner = i2c_new_client_device(adapter, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) if (!i2c_client_has_driver(client_tuner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* delegate signal strength measurement to tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) fe0->dvb.frontend->ops.read_signal_strength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) case CX23885_BOARD_DVBSKY_S952:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) memset(&m88ds3103_pdata, 0, sizeof(m88ds3103_pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) m88ds3103_pdata.clk = 27000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) m88ds3103_pdata.i2c_wr_max = 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) m88ds3103_pdata.agc = 0x99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) m88ds3103_pdata.clk_out = M88DS3103_CLOCK_OUT_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) m88ds3103_pdata.lnb_en_pol = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /* port b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) i2c_bus = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) m88ds3103_pdata.ts_mode = M88DS3103_TS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) m88ds3103_pdata.ts_clk = 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) m88ds3103_pdata.ts_clk_pol = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) p_set_voltage = dvbsky_t9580_set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) /* port c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) m88ds3103_pdata.ts_mode = M88DS3103_TS_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) m88ds3103_pdata.ts_clk = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) m88ds3103_pdata.ts_clk_pol = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) p_set_voltage = dvbsky_s952_portc_set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) memset(&info, 0, sizeof(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) strscpy(info.type, "m88ds3103", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) info.addr = 0x68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) info.platform_data = &m88ds3103_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if (!i2c_client_has_driver(client_demod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (!try_module_get(client_demod->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) port->i2c_client_demod = client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) adapter = m88ds3103_pdata.get_i2c_adapter(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) fe0->dvb.frontend = m88ds3103_pdata.get_dvb_frontend(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) memset(&ts2020_config, 0, sizeof(ts2020_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ts2020_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) ts2020_config.get_agc_pwm = m88ds3103_get_agc_pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) strscpy(info.type, "ts2020", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) info.addr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) info.platform_data = &ts2020_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) client_tuner = i2c_new_client_device(adapter, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) if (!i2c_client_has_driver(client_tuner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* delegate signal strength measurement to tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) fe0->dvb.frontend->ops.read_signal_strength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) * for setting the voltage we need to set GPIOs on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) * the card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) port->fe_set_voltage =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) fe0->dvb.frontend->ops.set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) fe0->dvb.frontend->ops.set_voltage = p_set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) case CX23885_BOARD_DVBSKY_T982:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) memset(&si2168_config, 0, sizeof(si2168_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /* port b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) i2c_bus = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) si2168_config.ts_mode = SI2168_TS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /* port c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) si2168_config.ts_mode = SI2168_TS_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) si2168_config.i2c_adapter = &adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) si2168_config.fe = &fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) strscpy(info.type, "si2168", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) info.addr = 0x64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) info.platform_data = &si2168_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (!i2c_client_has_driver(client_demod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) if (!try_module_get(client_demod->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) port->i2c_client_demod = client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) si2157_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) strscpy(info.type, "si2157", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) info.addr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) info.platform_data = &si2157_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) request_module(info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) client_tuner = i2c_new_client_device(adapter, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) if (!i2c_client_has_driver(client_tuner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) case CX23885_BOARD_HAUPPAUGE_STARBURST2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) case CX23885_BOARD_HAUPPAUGE_HVR5525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) i2c_bus2 = &dev->i2c_bus[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) /* port b - satellite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) fe0->dvb.frontend = dvb_attach(m88ds3103_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) &hauppauge_hvr5525_m88ds3103_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) &i2c_bus->i2c_adap, &adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) /* attach SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) a8293_pdata.dvb_frontend = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) memset(&info, 0, sizeof(info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) strscpy(info.type, "a8293", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) info.addr = 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) info.platform_data = &a8293_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) request_module("a8293");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) client_sec = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) if (!i2c_client_has_driver(client_sec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (!try_module_get(client_sec->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) i2c_unregister_device(client_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) port->i2c_client_sec = client_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) memset(&m88rs6000t_config, 0, sizeof(m88rs6000t_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) m88rs6000t_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) strscpy(info.type, "m88rs6000t", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) info.addr = 0x21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) info.platform_data = &m88rs6000t_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) request_module("%s", info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) client_tuner = i2c_new_client_device(adapter, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) if (!i2c_client_has_driver(client_tuner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) /* delegate signal strength measurement to tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) fe0->dvb.frontend->ops.read_signal_strength =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) /* port c - terrestrial/cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) memset(&si2168_config, 0, sizeof(si2168_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) si2168_config.i2c_adapter = &adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) si2168_config.fe = &fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) si2168_config.ts_mode = SI2168_TS_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) strscpy(info.type, "si2168", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) info.addr = 0x64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) info.platform_data = &si2168_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) request_module("%s", info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) client_demod = i2c_new_client_device(&i2c_bus->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) if (!i2c_client_has_driver(client_demod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (!try_module_get(client_demod->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) port->i2c_client_demod = client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) si2157_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) strscpy(info.type, "si2157", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) info.addr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) info.platform_data = &si2157_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) request_module("%s", info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) client_tuner = i2c_new_client_device(&i2c_bus2->i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (!i2c_client_has_driver(client_tuner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) dev->ts1.analog_fe.tuner_priv = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) memcpy(&dev->ts1.analog_fe.ops.tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) &fe0->dvb.frontend->ops.tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) case CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) pr_info("%s(): board=%d port=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) dev->board, port->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /* port b - Terrestrial/cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) memset(&si2168_config, 0, sizeof(si2168_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) si2168_config.i2c_adapter = &adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) si2168_config.fe = &fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) si2168_config.ts_mode = SI2168_TS_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) strscpy(info.type, "si2168", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) info.addr = 0x64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) info.platform_data = &si2168_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) request_module("%s", info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) client_demod = i2c_new_client_device(&dev->i2c_bus[0].i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) if (!i2c_client_has_driver(client_demod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) if (!try_module_get(client_demod->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) port->i2c_client_demod = client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) si2157_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) strscpy(info.type, "si2157", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) info.addr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) info.platform_data = &si2157_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) request_module("%s", info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) if (!i2c_client_has_driver(client_tuner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) /* we only attach tuner for analog on the 888 version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) if (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_DVB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) pr_info("%s(): QUADHD_DVB analog setup\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) dev->ts1.analog_fe.tuner_priv = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) memcpy(&dev->ts1.analog_fe.ops.tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) &fe0->dvb.frontend->ops.tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /* port c - terrestrial/cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) memset(&si2168_config, 0, sizeof(si2168_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) si2168_config.i2c_adapter = &adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) si2168_config.fe = &fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) si2168_config.ts_mode = SI2168_TS_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) strscpy(info.type, "si2168", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) info.addr = 0x66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) info.platform_data = &si2168_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) request_module("%s", info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) client_demod = i2c_new_client_device(&dev->i2c_bus[0].i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (!i2c_client_has_driver(client_demod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) if (!try_module_get(client_demod->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) port->i2c_client_demod = client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) si2157_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) strscpy(info.type, "si2157", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) info.addr = 0x62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) info.platform_data = &si2157_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) request_module("%s", info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if (!i2c_client_has_driver(client_tuner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) case CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) pr_info("%s(): board=%d port=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) dev->board, port->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* port b - Terrestrial/cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) fe0->dvb.frontend = dvb_attach(lgdt3306a_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) &hauppauge_quadHD_ATSC_a_config, &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) si2157_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) si2157_config.inversion = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) strscpy(info.type, "si2157", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) info.addr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) info.platform_data = &si2157_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) request_module("%s", info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) if (!i2c_client_has_driver(client_tuner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) /* we only attach tuner for analog on the 888 version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) if (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) pr_info("%s(): QUADHD_ATSC analog setup\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) dev->ts1.analog_fe.tuner_priv = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) memcpy(&dev->ts1.analog_fe.ops.tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) &fe0->dvb.frontend->ops.tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) /* port c - terrestrial/cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) fe0->dvb.frontend = dvb_attach(lgdt3306a_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) &hauppauge_quadHD_ATSC_b_config, &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) si2157_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) si2157_config.inversion = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) strscpy(info.type, "si2157", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) info.addr = 0x62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) info.platform_data = &si2157_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) request_module("%s", info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) if (!i2c_client_has_driver(client_tuner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) case CX23885_BOARD_HAUPPAUGE_HVR1265_K4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) switch (port->nr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) /* port c - Terrestrial/cable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) /* attach frontend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) i2c_bus = &dev->i2c_bus[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) fe0->dvb.frontend = dvb_attach(lgdt3306a_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) &hauppauge_hvr1265k4_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) &i2c_bus->i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) if (fe0->dvb.frontend == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* attach tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) memset(&si2157_config, 0, sizeof(si2157_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) si2157_config.fe = fe0->dvb.frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) si2157_config.if_port = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) si2157_config.inversion = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) strscpy(info.type, "si2157", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) info.addr = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) info.platform_data = &si2157_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) request_module("%s", info.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) client_tuner = i2c_new_client_device(&dev->i2c_bus[1].i2c_adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (!i2c_client_has_driver(client_tuner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) if (!try_module_get(client_tuner->dev.driver->owner)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) client_tuner = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) port->i2c_client_tuner = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) dev->ts1.analog_fe.tuner_priv = client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) memcpy(&dev->ts1.analog_fe.ops.tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) &fe0->dvb.frontend->ops.tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) sizeof(struct dvb_tuner_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) pr_info("%s: The frontend of your DVB/ATSC card isn't supported yet\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) pr_err("%s: frontend initialization failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) /* define general-purpose callback pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) fe0->dvb.frontend->callback = cx23885_tuner_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) if (fe1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) fe1->dvb.frontend->callback = cx23885_tuner_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) /* Ensure all frontends negotiate bus access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) if (fe1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) /* Put the tuner in standby to keep it quiet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) call_all(dev, tuner, standby);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) if (fe0->dvb.frontend->ops.analog_ops.standby)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) /* register everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) ret = vb2_dvb_register_bus(&port->frontends, THIS_MODULE, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) &dev->pci->dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) adapter_nr, mfe_shared);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) ret = dvb_register_ci_mac(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) goto frontend_detach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) frontend_detach:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /* remove I2C client for SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) client_sec = port->i2c_client_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) if (client_sec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) module_put(client_sec->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) i2c_unregister_device(client_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) port->i2c_client_sec = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) /* remove I2C client for tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) client_tuner = port->i2c_client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (client_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) module_put(client_tuner->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) i2c_unregister_device(client_tuner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) port->i2c_client_tuner = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) /* remove I2C client for demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) client_demod = port->i2c_client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) if (client_demod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) module_put(client_demod->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) i2c_unregister_device(client_demod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) port->i2c_client_demod = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) port->gate_ctrl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) vb2_dvb_dealloc_frontends(&port->frontends);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) int cx23885_dvb_register(struct cx23885_tsport *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) struct vb2_dvb_frontend *fe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) struct cx23885_dev *dev = port->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) /* Here we need to allocate the correct number of frontends,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) * as reflected in the cards struct. The reality is that currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) * no cx23885 boards support this - yet. But, if we don't modify this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) * code then the second frontend would never be allocated (later)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) * and fail with error before the attach in dvb_register().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) * Without these changes we risk an OOPS later. The changes here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) * are for safety, and should provide a good foundation for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) * future addition of any multi-frontend cx23885 based boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) pr_info("%s() allocating %d frontend(s)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) port->num_frontends);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) for (i = 1; i <= port->num_frontends; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) struct vb2_queue *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) if (vb2_dvb_alloc_frontend(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) &port->frontends, i) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) pr_err("%s() failed to alloc\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) fe0 = vb2_dvb_get_frontend(&port->frontends, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) if (!fe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) dprintk(1, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) dev->board,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) dev->pci_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) dev->pci_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) /* dvb stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) /* We have to init the queue for each frontend on a port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) pr_info("%s: cx23885 based dvb card\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) q = &fe0->dvb.dvbq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) q->gfp_flags = GFP_DMA32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) q->min_buffers_needed = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) q->drv_priv = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) q->buf_struct_size = sizeof(struct cx23885_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) q->ops = &dvb_qops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) q->mem_ops = &vb2_dma_sg_memops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) q->lock = &dev->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) q->dev = &dev->pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) err = vb2_queue_init(q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) err = dvb_register(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) if (err != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) pr_err("%s() dvb_register failed err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) int cx23885_dvb_unregister(struct cx23885_tsport *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) struct vb2_dvb_frontend *fe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) if (fe0 && fe0->dvb.frontend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) vb2_dvb_unregister_bus(&port->frontends);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) /* remove I2C client for CI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) client = port->i2c_client_ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) if (client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) module_put(client->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) i2c_unregister_device(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) /* remove I2C client for SEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) client = port->i2c_client_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) if (client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) module_put(client->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) i2c_unregister_device(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) /* remove I2C client for tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) client = port->i2c_client_tuner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) if (client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) module_put(client->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) i2c_unregister_device(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) /* remove I2C client for demodulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) client = port->i2c_client_demod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) module_put(client->dev.driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) i2c_unregister_device(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) switch (port->dev->board) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) netup_ci_exit(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) altera_ci_release(port->dev, port->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) port->gate_ctrl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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