^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * altera-ci.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * CI driver in conjunction with NetUp Dual DVB-T/C RF CI card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010,2011 NetUP Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * currently cx23885 GPIO's used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GPIO-0 ~INT in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * GPIO-1 TMS out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * GPIO-2 ~reset chips out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * GPIO-3 to GPIO-10 data/addr for CA in/out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GPIO-11 ~CS out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * GPIO-12 AD_RG out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * GPIO-13 ~WR out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * GPIO-14 ~RD out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * GPIO-15 ~RDY in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * GPIO-16 TCK out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * GPIO-17 TDO in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * GPIO-18 TDI out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Bit definitions for MC417_RWD and MC417_OEN registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * bits 31-16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * +-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * | Reserved |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * +-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * +-------+-------+-------+-------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * | TDI | TDO | TCK | RDY# | #RD | #WR | AD_RG | #CS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * +-------+-------+-------+-------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * +-------+-------+-------+-------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * | DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * +-------+-------+-------+-------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <media/dvb_demux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <media/dvb_frontend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "altera-ci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <media/dvb_ca_en50221.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* FPGA regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NETUP_CI_INT_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NETUP_CI_BUSCTRL2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NETUP_CI_ADDR0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NETUP_CI_ADDR1 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NETUP_CI_DATA 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NETUP_CI_BUSCTRL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NETUP_CI_PID_ADDR0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NETUP_CI_PID_ADDR1 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NETUP_CI_PID_DATA 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NETUP_CI_TSA_DIV 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define NETUP_CI_TSB_DIV 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NETUP_CI_REVISION 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* const for ci op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define NETUP_CI_FLG_CTL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define NETUP_CI_FLG_RD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define NETUP_CI_FLG_AD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static unsigned int ci_dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) module_param(ci_dbg, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_PARM_DESC(ci_dbg, "Enable CI debugging");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static unsigned int pid_dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) module_param(pid_dbg, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MODULE_PARM_DESC(pid_dbg, "Enable PID filtering debugging");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MODULE_DESCRIPTION("altera FPGA CI module");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MODULE_AUTHOR("Igor M. Liplianin <liplianin@netup.ru>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ci_dbg_print(fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ci_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) printk(KERN_DEBUG pr_fmt("%s: " fmt), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __func__, ##args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define pid_dbg_print(fmt, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (pid_dbg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) printk(KERN_DEBUG pr_fmt("%s: " fmt), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __func__, ##args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct altera_ci_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct netup_hw_pid_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct fpga_internal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct mutex fpga_mutex;/* two CI's on the same fpga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct netup_hw_pid_filter *pid_filt[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct altera_ci_state *state[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int (*fpga_rw) (void *dev, int flag, int data, int rw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int cis_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int filts_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int strt_wrk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* stores all private variables for communication with CI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct altera_ci_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct fpga_internal *internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct dvb_ca_en50221 ca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* stores all private variables for hardware pid filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct netup_hw_pid_filter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct fpga_internal *internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct dvb_demux *demux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* save old functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int (*start_feed)(struct dvb_demux_feed *feed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int (*stop_feed)(struct dvb_demux_feed *feed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* internal params node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct fpga_inode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* pointer for internal params, one for each pair of CI's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct fpga_internal *internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct fpga_inode *next_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* first internal params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct fpga_inode *fpga_first_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* find chip by dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct fpga_inode *find_inode(void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct fpga_inode *temp_chip = fpga_first_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (temp_chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return temp_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) Search for the last fpga CI chip or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) find it by dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) while ((temp_chip != NULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (temp_chip->internal->dev != dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) temp_chip = temp_chip->next_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return temp_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* check demux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct fpga_internal *check_filter(struct fpga_internal *temp_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void *demux_dev, int filt_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (temp_int == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if ((temp_int->pid_filt[filt_nr]) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (temp_int->pid_filt[filt_nr]->demux == demux_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return temp_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* find chip by demux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct fpga_inode *find_dinode(void *demux_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct fpga_inode *temp_chip = fpga_first_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct fpga_internal *temp_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Search of the last fpga CI chip or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * find it by demux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) while (temp_chip != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (temp_chip->internal != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) temp_int = temp_chip->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (check_filter(temp_int, demux_dev, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (check_filter(temp_int, demux_dev, 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) temp_chip = temp_chip->next_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return temp_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* deallocating chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void remove_inode(struct fpga_internal *internal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct fpga_inode *prev_node = fpga_first_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct fpga_inode *del_node = find_inode(internal->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (del_node != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (del_node == fpga_first_inode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) fpga_first_inode = del_node->next_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) while (prev_node->next_inode != del_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) prev_node = prev_node->next_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (del_node->next_inode == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) prev_node->next_inode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) prev_node->next_inode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) prev_node->next_inode->next_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) kfree(del_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* allocating new chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct fpga_inode *append_internal(struct fpga_internal *internal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct fpga_inode *new_node = fpga_first_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (new_node == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) new_node = kmalloc(sizeof(struct fpga_inode), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) fpga_first_inode = new_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) while (new_node->next_inode != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) new_node = new_node->next_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) new_node->next_inode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) kmalloc(sizeof(struct fpga_inode), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (new_node->next_inode != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) new_node = new_node->next_inode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) new_node = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (new_node != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) new_node->internal = internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) new_node->next_inode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return new_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int netup_fpga_op_rw(struct fpga_internal *inter, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 val, u8 read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) inter->fpga_rw(inter->dev, NETUP_CI_FLG_AD, addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return inter->fpga_rw(inter->dev, 0, val, read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* flag - mem/io, read - read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int altera_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 flag, u8 read, int addr, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct altera_ci_state *state = en50221->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct fpga_internal *inter = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int mem = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (0 != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mutex_lock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) netup_fpga_op_rw(inter, NETUP_CI_ADDR0, ((addr << 1) & 0xfe), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) netup_fpga_op_rw(inter, NETUP_CI_ADDR1, ((addr >> 7) & 0x7f), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) store &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) store |= ((state->nr << 7) | (flag << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, store, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mem = netup_fpga_op_rw(inter, NETUP_CI_DATA, val, read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mutex_unlock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ci_dbg_print("%s: %s: addr=[0x%02x], %s=%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) (read) ? "read" : "write", addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) (flag == NETUP_CI_FLG_CTL) ? "ctl" : "mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) (read) ? mem : val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int altera_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int slot, int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return altera_ci_op_cam(en50221, slot, 0, NETUP_CI_FLG_RD, addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int altera_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int slot, int addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return altera_ci_op_cam(en50221, slot, 0, 0, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int altera_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int slot, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return altera_ci_op_cam(en50221, slot, NETUP_CI_FLG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) NETUP_CI_FLG_RD, addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int altera_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u8 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return altera_ci_op_cam(en50221, slot, NETUP_CI_FLG_CTL, 0, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int altera_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct altera_ci_state *state = en50221->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct fpga_internal *inter = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* reasonable timeout for CI reset is 10 seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long t_out = jiffies + msecs_to_jiffies(9999);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ci_dbg_print("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (0 != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mutex_lock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) (ret & 0xcf) | (1 << (5 - state->nr)), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mutex_unlock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mutex_lock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0, NETUP_CI_FLG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mutex_unlock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if ((ret & (1 << (5 - state->nr))) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (time_after(jiffies, t_out))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ci_dbg_print("%s: %d msecs\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) jiffies_to_msecs(jiffies + msecs_to_jiffies(9999) - t_out));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int altera_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int altera_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct altera_ci_state *state = en50221->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct fpga_internal *inter = state->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ci_dbg_print("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (0 != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mutex_lock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (ret & 0x0f) | (1 << (3 - state->nr)), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mutex_unlock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* work handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void netup_read_ci_status(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct fpga_internal *inter =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) container_of(work, struct fpga_internal, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ci_dbg_print("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mutex_lock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* ack' irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0, NETUP_CI_FLG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mutex_unlock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (inter->state[1] != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) inter->state[1]->status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ((ret & 1) == 0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DVB_CA_EN50221_POLL_CAM_PRESENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DVB_CA_EN50221_POLL_CAM_READY : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ci_dbg_print("%s: setting CI[1] status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) __func__, inter->state[1]->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (inter->state[0] != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) inter->state[0]->status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ((ret & 2) == 0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DVB_CA_EN50221_POLL_CAM_PRESENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DVB_CA_EN50221_POLL_CAM_READY : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ci_dbg_print("%s: setting CI[0] status = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __func__, inter->state[0]->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* CI irq handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int altera_ci_irq(void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct fpga_inode *temp_int = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct fpga_internal *inter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ci_dbg_print("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (dev != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) temp_int = find_inode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (temp_int != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) inter = temp_int->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) schedule_work(&inter->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) EXPORT_SYMBOL(altera_ci_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int altera_poll_ci_slot_status(struct dvb_ca_en50221 *en50221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int slot, int open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct altera_ci_state *state = en50221->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (0 != slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return state->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void altera_hw_filt_release(void *main_dev, int filt_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct fpga_inode *temp_int = find_inode(main_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct netup_hw_pid_filter *pid_filt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ci_dbg_print("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (temp_int != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pid_filt = temp_int->internal->pid_filt[filt_nr - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* stored old feed controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pid_filt->demux->start_feed = pid_filt->start_feed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pid_filt->demux->stop_feed = pid_filt->stop_feed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (((--(temp_int->internal->filts_used)) <= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ((temp_int->internal->cis_used) <= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ci_dbg_print("%s: Actually removing\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) remove_inode(temp_int->internal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) kfree(pid_filt->internal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) kfree(pid_filt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) void altera_ci_release(void *dev, int ci_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct fpga_inode *temp_int = find_inode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct altera_ci_state *state = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ci_dbg_print("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (temp_int != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) state = temp_int->internal->state[ci_nr - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) altera_hw_filt_release(dev, ci_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (((temp_int->internal->filts_used) <= 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ((--(temp_int->internal->cis_used)) <= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ci_dbg_print("%s: Actually removing\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) remove_inode(temp_int->internal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) kfree(state->internal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (state != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (state->ca.data != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dvb_ca_en50221_release(&state->ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) EXPORT_SYMBOL(altera_ci_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static void altera_pid_control(struct netup_hw_pid_filter *pid_filt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u16 pid, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct fpga_internal *inter = pid_filt->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 store = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* pid 0-0x1f always enabled, don't touch them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if ((pid == 0x2000) || (pid < 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mutex_lock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, (pid >> 3) & 0xff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ((pid >> 11) & 0x03) | (pid_filt->nr << 2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) store = netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 0, NETUP_CI_FLG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (onoff)/* 0 - on, 1 - off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) store |= (1 << (pid & 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) store &= ~(1 << (pid & 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, store, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mutex_unlock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pid_dbg_print("%s: (%d) set pid: %5d 0x%04x '%s'\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pid_filt->nr, pid, pid, onoff ? "off" : "on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static void altera_toggle_fullts_streaming(struct netup_hw_pid_filter *pid_filt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int filt_nr, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct fpga_internal *inter = pid_filt->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u8 store = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pid_dbg_print("%s: pid_filt->nr[%d] now %s\n", __func__, pid_filt->nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) onoff ? "off" : "on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (onoff)/* 0 - on, 1 - off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) store = 0xff;/* ignore pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) store = 0;/* enable pid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mutex_lock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) for (i = 0; i < 1024; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, i & 0xff, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ((i >> 8) & 0x03) | (pid_filt->nr << 2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* pid 0-0x1f always enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) netup_fpga_op_rw(inter, NETUP_CI_PID_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) (i > 3 ? store : 0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mutex_unlock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int altera_pid_feed_control(void *demux_dev, int filt_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct dvb_demux_feed *feed, int onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct fpga_inode *temp_int = find_dinode(demux_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct fpga_internal *inter = temp_int->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct netup_hw_pid_filter *pid_filt = inter->pid_filt[filt_nr - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) altera_pid_control(pid_filt, feed->pid, onoff ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* call old feed proc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (onoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pid_filt->start_feed(feed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pid_filt->stop_feed(feed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (feed->pid == 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) altera_toggle_fullts_streaming(pid_filt, filt_nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) onoff ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int altera_ci_start_feed(struct dvb_demux_feed *feed, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) altera_pid_feed_control(feed->demux, num, feed, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int altera_ci_stop_feed(struct dvb_demux_feed *feed, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) altera_pid_feed_control(feed->demux, num, feed, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int altera_ci_start_feed_1(struct dvb_demux_feed *feed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return altera_ci_start_feed(feed, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int altera_ci_stop_feed_1(struct dvb_demux_feed *feed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return altera_ci_stop_feed(feed, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int altera_ci_start_feed_2(struct dvb_demux_feed *feed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return altera_ci_start_feed(feed, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int altera_ci_stop_feed_2(struct dvb_demux_feed *feed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return altera_ci_stop_feed(feed, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int altera_hw_filt_init(struct altera_ci_config *config, int hw_filt_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct netup_hw_pid_filter *pid_filt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct fpga_inode *temp_int = find_inode(config->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct fpga_internal *inter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pid_filt = kzalloc(sizeof(struct netup_hw_pid_filter), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ci_dbg_print("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!pid_filt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (temp_int != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) inter = temp_int->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) (inter->filts_used)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ci_dbg_print("%s: Find Internal Structure!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!inter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) temp_int = append_internal(inter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!temp_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) inter->filts_used = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) inter->dev = config->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) inter->fpga_rw = config->fpga_rw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) mutex_init(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) inter->strt_wrk = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ci_dbg_print("%s: Create New Internal Structure!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ci_dbg_print("%s: setting hw pid filter = %p for ci = %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) pid_filt, hw_filt_nr - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) inter->pid_filt[hw_filt_nr - 1] = pid_filt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pid_filt->demux = config->demux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pid_filt->internal = inter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) pid_filt->nr = hw_filt_nr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* store old feed controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) pid_filt->start_feed = config->demux->start_feed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) pid_filt->stop_feed = config->demux->stop_feed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* replace with new feed controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (hw_filt_nr == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) pid_filt->demux->start_feed = altera_ci_start_feed_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pid_filt->demux->stop_feed = altera_ci_stop_feed_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) } else if (hw_filt_nr == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) pid_filt->demux->start_feed = altera_ci_start_feed_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) pid_filt->demux->stop_feed = altera_ci_stop_feed_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) altera_toggle_fullts_streaming(pid_filt, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ci_dbg_print("%s: Can't init hardware filter: Error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) kfree(pid_filt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) kfree(inter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int altera_ci_init(struct altera_ci_config *config, int ci_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct altera_ci_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct fpga_inode *temp_int = find_inode(config->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct fpga_internal *inter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u8 store = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) state = kzalloc(sizeof(struct altera_ci_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ci_dbg_print("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (!state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (temp_int != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) inter = temp_int->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) (inter->cis_used)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) inter->fpga_rw = config->fpga_rw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ci_dbg_print("%s: Find Internal Structure!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) inter = kzalloc(sizeof(struct fpga_internal), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (!inter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) temp_int = append_internal(inter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (!temp_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) inter->cis_used = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) inter->dev = config->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) inter->fpga_rw = config->fpga_rw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mutex_init(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) inter->strt_wrk = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ci_dbg_print("%s: Create New Internal Structure!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ci_dbg_print("%s: setting state = %p for ci = %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) state, ci_nr - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) state->internal = inter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) state->nr = ci_nr - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) state->ca.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) state->ca.read_attribute_mem = altera_ci_read_attribute_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) state->ca.write_attribute_mem = altera_ci_write_attribute_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) state->ca.read_cam_control = altera_ci_read_cam_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) state->ca.write_cam_control = altera_ci_write_cam_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) state->ca.slot_reset = altera_ci_slot_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) state->ca.slot_shutdown = altera_ci_slot_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) state->ca.slot_ts_enable = altera_ci_slot_ts_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) state->ca.poll_slot_status = altera_poll_ci_slot_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) state->ca.data = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = dvb_ca_en50221_init(config->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) &state->ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* flags */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* n_slots */ 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (0 != ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) inter->state[ci_nr - 1] = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) altera_hw_filt_init(config, ci_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (inter->strt_wrk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) INIT_WORK(&inter->work, netup_read_ci_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) inter->strt_wrk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ci_dbg_print("%s: CI initialized!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mutex_lock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Enable div */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) netup_fpga_op_rw(inter, NETUP_CI_TSA_DIV, 0x0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) netup_fpga_op_rw(inter, NETUP_CI_TSB_DIV, 0x0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* enable TS out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) store |= (3 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = netup_fpga_op_rw(inter, NETUP_CI_REVISION, 0, NETUP_CI_FLG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* enable irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0x44, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mutex_unlock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ci_dbg_print("%s: NetUP CI Revision = 0x%x\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) schedule_work(&inter->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) kfree(inter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) EXPORT_SYMBOL(altera_ci_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int altera_ci_tuner_reset(void *dev, int ci_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct fpga_inode *temp_int = find_inode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct fpga_internal *inter = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u8 store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ci_dbg_print("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (temp_int == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (temp_int->internal == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) inter = temp_int->internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) mutex_lock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) store &= ~(4 << (2 - ci_nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) store |= (4 << (2 - ci_nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) mutex_unlock(&inter->fpga_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) EXPORT_SYMBOL(altera_ci_tuner_reset);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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