^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cobalt driver initialization and card probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Derived from cx18-driver.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <media/i2c/adv7604.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <media/i2c/adv7842.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <media/i2c/adv7511.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "cobalt-driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "cobalt-irq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "cobalt-i2c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "cobalt-v4l2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "cobalt-flash.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "cobalt-alsa.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "cobalt-omnitek.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* add your revision and whatnot here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const struct pci_device_id cobalt_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_COBALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_DEVICE_TABLE(pci, cobalt_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static atomic_t cobalt_instance = ATOMIC_INIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int cobalt_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) module_param_named(debug, cobalt_debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MODULE_PARM_DESC(debug, "Debug level. Default: 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int cobalt_ignore_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param_named(ignore_err, cobalt_ignore_err, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(ignore_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "If set then ignore missing i2c adapters/receivers. Default: 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com> & Morten Hestnes");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_DESCRIPTION("cobalt driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static u8 edid[256] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0x50, 0x21, 0x32, 0x27, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0x22, 0x1a, 0x01, 0x03, 0x80, 0x30, 0x1b, 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0x0f, 0xee, 0x91, 0xa3, 0x54, 0x4c, 0x99, 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0x0f, 0x50, 0x54, 0x2f, 0xcf, 0x00, 0x31, 0x59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 0x45, 0x59, 0x61, 0x59, 0x81, 0x99, 0x01, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 0x46, 0x00, 0xe0, 0x0e, 0x11, 0x00, 0x00, 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x55, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x5e, 0x11, 0x00, 0x0a, 0x20, 0x20, 0x20, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0x6f, 0x62, 0x61, 0x6c, 0x74, 0x0a, 0x20, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0x02, 0x03, 0x1f, 0xf0, 0x4a, 0x90, 0x1f, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0x13, 0x22, 0x21, 0x20, 0x02, 0x11, 0x01, 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0x09, 0x07, 0x07, 0x68, 0x03, 0x0c, 0x00, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0x00, 0x00, 0x22, 0x0f, 0xe2, 0x00, 0xea, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void cobalt_set_interrupt(struct cobalt *cobalt, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned irqs = COBALT_SYSSTAT_VI0_INT1_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) COBALT_SYSSTAT_VI1_INT1_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) COBALT_SYSSTAT_VI2_INT1_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) COBALT_SYSSTAT_VI3_INT1_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) COBALT_SYSSTAT_VI0_INT2_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) COBALT_SYSSTAT_VI1_INT2_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) COBALT_SYSSTAT_VI2_INT2_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) COBALT_SYSSTAT_VI3_INT2_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) COBALT_SYSSTAT_VI0_LOST_DATA_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) COBALT_SYSSTAT_VI1_LOST_DATA_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) COBALT_SYSSTAT_VI2_LOST_DATA_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) COBALT_SYSSTAT_VI3_LOST_DATA_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (cobalt->have_hsma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) irqs |= COBALT_SYSSTAT_VIHSMA_INT1_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) COBALT_SYSSTAT_VIHSMA_INT2_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (cobalt->have_hsma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) irqs |= COBALT_SYSSTAT_VOHSMA_INT1_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Clear any existing interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) cobalt_write_bar1(cobalt, COBALT_SYS_STAT_EDGE, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* PIO Core interrupt mask register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Enable ADV7604 INT1 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK, irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Disable all ADV7604 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static unsigned cobalt_get_sd_nr(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct cobalt *cobalt = to_cobalt(sd->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) for (i = 0; i < COBALT_NUM_NODES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (sd == cobalt->streams[i].sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) cobalt_err("Invalid adv7604 subdev pointer!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void cobalt_notify(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int notification, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct cobalt *cobalt = to_cobalt(sd->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned sd_nr = cobalt_get_sd_nr(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct cobalt_stream *s = &cobalt->streams[sd_nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool hotplug = arg ? *((int *)arg) : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (s->is_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) switch (notification) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case ADV76XX_HOTPLUG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cobalt_s_bit_sysctrl(cobalt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) COBALT_SYS_CTRL_HPD_TO_CONNECTOR_BIT(sd_nr), hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cobalt_dbg(1, "Set hotplug for adv %d to %d\n", sd_nr, hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case V4L2_DEVICE_NOTIFY_EVENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cobalt_dbg(1, "Format changed for adv %d\n", sd_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) v4l2_event_queue(&s->vdev, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int get_payload_size(u16 code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) case 0: return 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case 1: return 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case 2: return 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case 3: return 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case 4: return 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case 5: return 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) default: return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const char *get_link_speed(u16 stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) switch (stat & PCI_EXP_LNKSTA_CLS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case 1: return "2.5 Gbit/s";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case 2: return "5 Gbit/s";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case 3: return "10 Gbit/s";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return "Unknown speed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void cobalt_pcie_status_show(struct cobalt *cobalt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct pci_dev *pci_dev = cobalt->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct pci_dev *pci_bus_dev = cobalt->pci_dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 capa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u16 stat, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!pci_is_pcie(pci_dev) || !pci_is_pcie(pci_bus_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pcie_capability_read_dword(pci_dev, PCI_EXP_DEVCAP, &capa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pcie_capability_read_word(pci_dev, PCI_EXP_DEVCTL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pcie_capability_read_word(pci_dev, PCI_EXP_DEVSTA, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cobalt_info("PCIe device capability 0x%08x: Max payload %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) capa, get_payload_size(capa & PCI_EXP_DEVCAP_PAYLOAD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cobalt_info("PCIe device control 0x%04x: Max payload %d. Max read request %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) get_payload_size((ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) get_payload_size((ctrl & PCI_EXP_DEVCTL_READRQ) >> 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cobalt_info("PCIe device status 0x%04x\n", stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &capa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cobalt_info("PCIe link capability 0x%08x: %s per lane and %u lanes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) capa, get_link_speed(capa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (capa & PCI_EXP_LNKCAP_MLW) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cobalt_info("PCIe link control 0x%04x\n", ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cobalt_info("PCIe link status 0x%04x: %s per lane and %u lanes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) stat, get_link_speed(stat),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (stat & PCI_EXP_LNKSTA_NLW) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pcie_capability_read_dword(pci_bus_dev, PCI_EXP_LNKCAP, &capa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cobalt_info("PCIe bus link capability 0x%08x: %s per lane and %u lanes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) capa, get_link_speed(capa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) (capa & PCI_EXP_LNKCAP_MLW) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pcie_capability_read_dword(pci_dev, PCI_EXP_SLTCAP, &capa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pcie_capability_read_word(pci_dev, PCI_EXP_SLTCTL, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pcie_capability_read_word(pci_dev, PCI_EXP_SLTSTA, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cobalt_info("PCIe slot capability 0x%08x\n", capa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cobalt_info("PCIe slot control 0x%04x\n", ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cobalt_info("PCIe slot status 0x%04x\n", stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static unsigned pcie_link_get_lanes(struct cobalt *cobalt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct pci_dev *pci_dev = cobalt->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!pci_is_pcie(pci_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return (link & PCI_EXP_LNKSTA_NLW) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static unsigned pcie_bus_link_get_lanes(struct cobalt *cobalt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct pci_dev *pci_dev = cobalt->pci_dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!pci_is_pcie(pci_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return (link & PCI_EXP_LNKCAP_MLW) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void msi_config_show(struct cobalt *cobalt, struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u16 ctrl, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 adrs_l, adrs_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pci_read_config_word(pci_dev, 0x52, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cobalt_info("MSI %s\n", ctrl & 1 ? "enable" : "disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) cobalt_info("MSI multiple message: Capable %u. Enable %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) (1 << ((ctrl >> 1) & 7)), (1 << ((ctrl >> 4) & 7)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ctrl & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cobalt_info("MSI: 64-bit address capable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pci_read_config_dword(pci_dev, 0x54, &adrs_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pci_read_config_dword(pci_dev, 0x58, &adrs_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pci_read_config_word(pci_dev, 0x5c, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ctrl & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cobalt_info("MSI: Address 0x%08x%08x. Data 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) adrs_h, adrs_l, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cobalt_info("MSI: Address 0x%08x. Data 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) adrs_l, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void cobalt_pci_iounmap(struct cobalt *cobalt, struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (cobalt->bar0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pci_iounmap(pci_dev, cobalt->bar0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) cobalt->bar0 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (cobalt->bar1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pci_iounmap(pci_dev, cobalt->bar1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cobalt->bar1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void cobalt_free_msi(struct cobalt *cobalt, struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) free_irq(pci_dev->irq, (void *)cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pci_free_irq_vectors(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int cobalt_setup_pci(struct cobalt *cobalt, struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cobalt_dbg(1, "enabling pci device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = pci_enable_device(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) cobalt_err("can't enable device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pci_set_master(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &cobalt->card_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pci_read_config_word(pci_dev, PCI_DEVICE_ID, &cobalt->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) switch (cobalt->device_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case PCI_DEVICE_ID_COBALT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) cobalt_info("PCI Express interface from Omnitek\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) cobalt_info("PCI Express interface provider is unknown!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (pcie_link_get_lanes(cobalt) != 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) cobalt_warn("PCI Express link width is %d lanes.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pcie_link_get_lanes(cobalt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (pcie_bus_link_get_lanes(cobalt) < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) cobalt_warn("The current slot only supports %d lanes, for best performance 8 are needed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pcie_bus_link_get_lanes(cobalt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (pcie_link_get_lanes(cobalt) != pcie_bus_link_get_lanes(cobalt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) cobalt_err("The card is most likely not seated correctly in the PCIe slot\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) cobalt_err("no suitable DMA available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = pci_request_regions(pci_dev, "cobalt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) cobalt_err("error requesting regions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cobalt_pcie_status_show(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) cobalt->bar0 = pci_iomap(pci_dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cobalt->bar1 = pci_iomap(pci_dev, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (cobalt->bar1 == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) cobalt->bar1 = pci_iomap(pci_dev, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cobalt_info("64-bit BAR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!cobalt->bar0 || !cobalt->bar1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) goto err_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Reset the video inputs before enabling any interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ctrl = cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) cobalt_write_bar1(cobalt, COBALT_SYS_CTRL_BASE, ctrl & ~0xf00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Disable interrupts to prevent any spurious interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) from being generated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cobalt_set_interrupt(cobalt, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (pci_alloc_irq_vectors(pci_dev, 1, 1, PCI_IRQ_MSI) < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) cobalt_err("Could not enable MSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) goto err_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) msi_config_show(cobalt, pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Register IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (request_irq(pci_dev->irq, cobalt_irq_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) cobalt->v4l2_dev.name, (void *)cobalt)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cobalt_err("Failed to register irq %d\n", pci_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto err_msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) omni_sg_dma_init(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) err_msi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pci_disable_msi(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) err_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cobalt_pci_iounmap(cobalt, pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pci_release_regions(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) err_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pci_disable_device(cobalt->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int cobalt_hdl_info_get(struct cobalt *cobalt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) for (i = 0; i < COBALT_HDL_INFO_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) cobalt->hdl_info[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ioread8(cobalt->bar1 + COBALT_HDL_INFO_BASE + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) cobalt->hdl_info[COBALT_HDL_INFO_SIZE - 1] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (strstr(cobalt->hdl_info, COBALT_HDL_SEARCH_STR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void cobalt_stream_struct_init(struct cobalt *cobalt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) for (i = 0; i < COBALT_NUM_STREAMS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct cobalt_stream *s = &cobalt->streams[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) s->cobalt = cobalt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) s->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) s->is_audio = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) s->is_output = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) s->is_dummy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* The Memory DMA channels will always get a lower channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * number than the FIFO DMA. Video input should map to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * stream 0-3. The other can use stream struct from 4 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * higher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (i <= COBALT_HSMA_IN_NODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) s->dma_channel = i + cobalt->first_fifo_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) s->video_channel = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) s->dma_fifo_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) COBALT_SYSSTAT_VI0_LOST_DATA_MSK << (4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) s->adv_irq_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) COBALT_SYSSTAT_VI0_INT1_MSK << (4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else if (i >= COBALT_AUDIO_IN_STREAM &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) i <= COBALT_AUDIO_IN_STREAM + 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned idx = i - COBALT_AUDIO_IN_STREAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) s->dma_channel = 6 + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) s->is_audio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) s->video_channel = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) s->dma_fifo_mask = COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) } else if (i == COBALT_HSMA_OUT_NODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) s->dma_channel = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) s->is_output = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) s->video_channel = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) s->dma_fifo_mask = COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) s->adv_irq_mask = COBALT_SYSSTAT_VOHSMA_INT1_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else if (i == COBALT_AUDIO_OUT_STREAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) s->dma_channel = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) s->is_audio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) s->is_output = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) s->video_channel = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) s->dma_fifo_mask = COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* FIXME: Memory DMA for debug purpose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) s->dma_channel = i - COBALT_NUM_NODES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cobalt_info("stream #%d -> dma channel #%d <- video channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) i, s->dma_channel, s->video_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int cobalt_subdevs_init(struct cobalt *cobalt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct adv76xx_platform_data adv7604_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .disable_pwrdnb = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .ain_sel = ADV7604_AIN7_8_9_NC_SYNC_3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .bus_order = ADV7604_BUS_ORDER_BRG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .blank_data = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .op_format_mode_sel = ADV7604_OP_FORMAT_MODE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .dr_str_data = ADV76XX_DR_STR_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .dr_str_clk = ADV76XX_DR_STR_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .dr_str_sync = ADV76XX_DR_STR_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .hdmi_free_run_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .inv_vs_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .inv_hs_pol = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static struct i2c_board_info adv7604_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .type = "adv7604",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .addr = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .platform_data = &adv7604_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct cobalt_stream *s = cobalt->streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) for (i = 0; i < COBALT_NUM_INPUTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct v4l2_subdev_format sd_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .pad = ADV7604_PAD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .which = V4L2_SUBDEV_FORMAT_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .format.code = MEDIA_BUS_FMT_YUYV8_1X16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct v4l2_subdev_edid cobalt_edid = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .pad = ADV76XX_PAD_HDMI_PORT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .start_block = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .blocks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .edid = edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) s[i].pad_source = ADV7604_PAD_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) s[i].i2c_adap = &cobalt->i2c_adap[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (s[i].i2c_adap->dev.parent == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) cobalt_s_bit_sysctrl(cobalt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(i), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) s[i].sd = v4l2_i2c_new_subdev_board(&cobalt->v4l2_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) s[i].i2c_adap, &adv7604_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!s[i].sd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (cobalt_ignore_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) err = v4l2_subdev_call(s[i].sd, video, s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ADV76XX_PAD_HDMI_PORT_A, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) err = v4l2_subdev_call(s[i].sd, pad, set_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) &cobalt_edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) err = v4l2_subdev_call(s[i].sd, pad, set_fmt, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &sd_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Reset channel video module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) cobalt_s_bit_sysctrl(cobalt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cobalt_s_bit_sysctrl(cobalt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(i), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) s[i].is_dummy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cobalt->streams[i + COBALT_AUDIO_IN_STREAM].is_dummy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int cobalt_subdevs_hsma_init(struct cobalt *cobalt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct adv7842_platform_data adv7842_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .disable_pwrdnb = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .ain_sel = ADV7842_AIN1_2_3_NC_SYNC_1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .bus_order = ADV7842_BUS_ORDER_RBG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .op_format_mode_sel = ADV7842_OP_FORMAT_MODE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .blank_data = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .dr_str_data = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .dr_str_clk = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .dr_str_sync = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .mode = ADV7842_MODE_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .hdmi_free_run_enable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .i2c_sdp_io = 0x4a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .i2c_sdp = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .i2c_cp = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .i2c_vdp = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .i2c_afe = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .i2c_hdmi = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .i2c_repeater = 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .i2c_edid = 0x36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .i2c_infoframe = 0x3e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .i2c_cec = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .i2c_avlink = 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static struct i2c_board_info adv7842_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .type = "adv7842",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .addr = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .platform_data = &adv7842_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static struct v4l2_subdev_format sd_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .pad = ADV7842_PAD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .which = V4L2_SUBDEV_FORMAT_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .format.code = MEDIA_BUS_FMT_YUYV8_1X16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static struct adv7511_platform_data adv7511_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .i2c_edid = 0x7e >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .i2c_cec = 0x7c >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .i2c_pktmem = 0x70 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .cec_clk = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static struct i2c_board_info adv7511_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .type = "adv7511-v4l2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .addr = 0x39, /* 0x39 or 0x3d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .platform_data = &adv7511_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct v4l2_subdev_edid cobalt_edid = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .pad = ADV7842_EDID_PORT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .start_block = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .blocks = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .edid = edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct cobalt_stream *s = &cobalt->streams[COBALT_HSMA_IN_NODE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) s->i2c_adap = &cobalt->i2c_adap[COBALT_NUM_ADAPTERS - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (s->i2c_adap->dev.parent == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(4), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) s->sd = v4l2_i2c_new_subdev_board(&cobalt->v4l2_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) s->i2c_adap, &adv7842_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (s->sd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int err = v4l2_subdev_call(s->sd, pad, set_edid, &cobalt_edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) err = v4l2_subdev_call(s->sd, pad, set_fmt, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) &sd_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) cobalt->have_hsma_rx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) s->pad_source = ADV7842_PAD_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) s->is_dummy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) cobalt->streams[4 + COBALT_AUDIO_IN_STREAM].is_dummy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Reset channel video module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) cobalt_s_bit_sysctrl(cobalt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) cobalt_s_bit_sysctrl(cobalt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(4), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_PWRDN0_TO_HSMA_TX_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) s++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) s->i2c_adap = &cobalt->i2c_adap[COBALT_NUM_ADAPTERS - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) s->sd = v4l2_i2c_new_subdev_board(&cobalt->v4l2_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) s->i2c_adap, &adv7511_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (s->sd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* A transmitter is hooked up, so we can set this bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) cobalt_s_bit_sysctrl(cobalt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) cobalt_s_bit_sysctrl(cobalt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) cobalt_s_bit_sysctrl(cobalt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) COBALT_SYS_CTRL_VIDEO_TX_RESETN_BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) cobalt->have_hsma_tx = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) v4l2_subdev_call(s->sd, core, s_power, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) v4l2_subdev_call(s->sd, video, s_stream, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) v4l2_subdev_call(s->sd, audio, s_stream, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) v4l2_ctrl_s_ctrl(v4l2_ctrl_find(s->sd->ctrl_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) V4L2_CID_DV_TX_MODE), V4L2_DV_TX_MODE_HDMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) s->is_dummy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) cobalt->streams[COBALT_AUDIO_OUT_STREAM].is_dummy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int cobalt_probe(struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct cobalt *cobalt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* FIXME - module parameter arrays constrain max instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) i = atomic_inc_return(&cobalt_instance) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) cobalt = kzalloc(sizeof(struct cobalt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (cobalt == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) cobalt->pci_dev = pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) cobalt->instance = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) mutex_init(&cobalt->pci_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) retval = v4l2_device_register(&pci_dev->dev, &cobalt->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pr_err("cobalt: v4l2_device_register of card %d failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) cobalt->instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) kfree(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) snprintf(cobalt->v4l2_dev.name, sizeof(cobalt->v4l2_dev.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "cobalt-%d", cobalt->instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) cobalt->v4l2_dev.notify = cobalt_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) cobalt_info("Initializing card %d\n", cobalt->instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) cobalt->irq_work_queues =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) create_singlethread_workqueue(cobalt->v4l2_dev.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (cobalt->irq_work_queues == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) cobalt_err("Could not create workqueue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) INIT_WORK(&cobalt->irq_work_queue, cobalt_irq_work_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* PCI Device Setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) retval = cobalt_setup_pci(cobalt, pci_dev, pci_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (retval != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) goto err_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Show HDL version info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (cobalt_hdl_info_get(cobalt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) cobalt_info("Not able to read the HDL info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) cobalt_info("%s", cobalt->hdl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) retval = cobalt_i2c_init(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) goto err_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) cobalt_stream_struct_init(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) retval = cobalt_subdevs_init(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (!(cobalt_read_bar1(cobalt, COBALT_SYS_STAT_BASE) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) COBALT_SYSSTAT_HSMA_PRSNTN_MSK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) retval = cobalt_subdevs_hsma_init(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) retval = cobalt_nodes_register(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cobalt_err("Error %d registering device nodes\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) cobalt_set_interrupt(cobalt, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) v4l2_device_call_all(&cobalt->v4l2_dev, 0, core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) interrupt_service_routine, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) cobalt_info("Initialized cobalt card\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) cobalt_flash_probe(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) err_i2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) cobalt_i2c_exit(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) err_pci:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) cobalt_free_msi(cobalt, pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) cobalt_pci_iounmap(cobalt, pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) pci_release_regions(cobalt->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pci_disable_device(cobalt->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) err_wq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) destroy_workqueue(cobalt->irq_work_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) cobalt_err("error %d on initialization\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) v4l2_device_unregister(&cobalt->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) kfree(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static void cobalt_remove(struct pci_dev *pci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct cobalt *cobalt = to_cobalt(v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) cobalt_flash_remove(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) cobalt_set_interrupt(cobalt, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) flush_workqueue(cobalt->irq_work_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) cobalt_nodes_unregister(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) for (i = 0; i < COBALT_NUM_ADAPTERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct v4l2_subdev *sd = cobalt->streams[i].sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (sd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) i2c_unregister_device(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) cobalt_i2c_exit(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) cobalt_free_msi(cobalt, pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) cobalt_pci_iounmap(cobalt, pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pci_release_regions(cobalt->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pci_disable_device(cobalt->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) destroy_workqueue(cobalt->irq_work_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) cobalt_info("removed cobalt card\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) v4l2_device_unregister(v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) kfree(cobalt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* define a pci_driver for card detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static struct pci_driver cobalt_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .name = "cobalt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .id_table = cobalt_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .probe = cobalt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .remove = cobalt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) module_pci_driver(cobalt_pci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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