^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * wm8739
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 T. Adachi <tadachi@tadachi-net.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2005 Hans Verkuil <hverkuil@xs4all.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - Cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MODULE_DESCRIPTION("wm8739 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MODULE_AUTHOR("T. Adachi, Hans Verkuil");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_PARM_DESC(debug, "Debug level (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) R0 = 0, R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) R5 = 5, R6, R7, R8, R9, R15 = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) TOT_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct wm8739_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* audio cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct v4l2_ctrl *volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct v4l2_ctrl *mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct v4l2_ctrl *balance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline struct wm8739_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return container_of(sd, struct wm8739_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return &container_of(ctrl->handler, struct wm8739_state, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int wm8739_write(struct v4l2_subdev *sd, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (reg < 0 || reg >= TOT_REGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) v4l2_err(sd, "Invalid register R%d\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) v4l2_dbg(1, debug, sd, "write: %02x %02x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (i2c_smbus_write_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (reg << 1) | (val >> 8), val & 0xff) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) v4l2_err(sd, "I2C: cannot write %03x to register R%d\n", val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int wm8739_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct wm8739_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int work_l, work_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 vol_l; /* +12dB to -34.5dB 1.5dB step (5bit) def:0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 vol_r; /* +12dB to -34.5dB 1.5dB step (5bit) def:0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u16 mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case V4L2_CID_AUDIO_VOLUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* normalize ( 65535 to 0 -> 31 to 0 (12dB to -34.5dB) ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) work_l = (min(65536 - state->balance->val, 32768) * state->volume->val) / 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) work_r = (min(state->balance->val, 32768) * state->volume->val) / 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) vol_l = (long)work_l * 31 / 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) vol_r = (long)work_r * 31 / 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* set audio volume etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mute = state->mute->val ? 0x80 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Volume setting: bits 0-4, 0x1f = 12 dB, 0x00 = -34.5 dB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Default setting: 0x17 = 0 dB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) wm8739_write(sd, R0, (vol_l & 0x1f) | mute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) wm8739_write(sd, R1, (vol_r & 0x1f) | mute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int wm8739_s_clock_freq(struct v4l2_subdev *sd, u32 audiofreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct wm8739_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) state->clock_freq = audiofreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* de-activate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) wm8739_write(sd, R9, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) switch (audiofreq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* 256fps, fs=44.1k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) wm8739_write(sd, R8, 0x020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* 256fps, fs=48k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) wm8739_write(sd, R8, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* 256fps, fs=32k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) wm8739_write(sd, R8, 0x018);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* activate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) wm8739_write(sd, R9, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int wm8739_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct wm8739_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) v4l2_info(sd, "Frequency: %u Hz\n", state->clock_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct v4l2_ctrl_ops wm8739_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .s_ctrl = wm8739_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct v4l2_subdev_core_ops wm8739_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .log_status = wm8739_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct v4l2_subdev_audio_ops wm8739_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .s_clock_freq = wm8739_s_clock_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct v4l2_subdev_ops wm8739_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .core = &wm8739_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .audio = &wm8739_audio_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* i2c implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int wm8739_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct wm8739_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) v4l_info(client, "chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) v4l2_i2c_subdev_init(sd, client, &wm8739_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) v4l2_ctrl_handler_init(&state->hdl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) state->volume = v4l2_ctrl_new_std(&state->hdl, &wm8739_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) V4L2_CID_AUDIO_VOLUME, 0, 65535, 65535 / 100, 50736);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) state->mute = v4l2_ctrl_new_std(&state->hdl, &wm8739_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) state->balance = v4l2_ctrl_new_std(&state->hdl, &wm8739_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) V4L2_CID_AUDIO_BALANCE, 0, 65535, 65535 / 100, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) sd->ctrl_handler = &state->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (state->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int err = state->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) v4l2_ctrl_cluster(3, &state->volume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) state->clock_freq = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Initialize wm8739 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) wm8739_write(sd, R15, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* filter setting, high path, offet clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) wm8739_write(sd, R5, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* ADC, OSC, Power Off mode Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) wm8739_write(sd, R6, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Digital Audio interface format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) Enable Master mode, 24 bit, MSB first/left justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) wm8739_write(sd, R7, 0x049);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* sampling control: normal, 256fs, 48KHz sampling rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) wm8739_write(sd, R8, 0x000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* activate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) wm8739_write(sd, R9, 0x001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* set volume/mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) v4l2_ctrl_handler_setup(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int wm8739_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct wm8739_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct i2c_device_id wm8739_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { "wm8739", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MODULE_DEVICE_TABLE(i2c, wm8739_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct i2c_driver wm8739_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = "wm8739",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .probe = wm8739_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .remove = wm8739_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .id_table = wm8739_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) module_i2c_driver(wm8739_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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