^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * vs6624.c ST VS6624 CMOS image sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "vs6624_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX_FRAME_RATE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct vs6624 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct v4l2_fract frame_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct v4l2_mbus_framefmt fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned ce_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct vs6624_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 mbus_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum v4l2_colorspace colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) } vs6624_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const struct v4l2_mbus_framefmt vs6624_default_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .width = VGA_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .height = VGA_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .code = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .field = V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const u16 vs6624_p1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0x8104, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0x8105, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0xc900, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0xc904, 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0xc905, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0xc906, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0xc907, 0x3a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0x903a, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0x903b, 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0x903c, 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0xc908, 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0xc909, 0xdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0xc90a, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0xc90b, 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x9044, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0x9045, 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x9046, 0xe2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0xc90c, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0xc90d, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0xc90e, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0xc90f, 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0x9047, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0x9048, 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0x9049, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 0x904a, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0x904b, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0x904c, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0x904d, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0x904e, 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0x904f, 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0x9050, 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x9051, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0x9052, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0x9053, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x9054, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0x9055, 0xE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0x9056, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x9057, 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x9058, 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0x9059, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x905a, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0x905b, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0x905c, 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0xc910, 0x5d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0xc911, 0xca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0xc912, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0xc913, 0x5d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x905d, 0xa3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0x905e, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0x905f, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x9060, 0xa3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x9061, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x9062, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0x9063, 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0xc914, 0x72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0xc915, 0x92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0xc916, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0xc917, 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x9064, 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x9065, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x9066, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x9067, 0x72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x9068, 0x95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0xc918, 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0xc919, 0xf2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0xc91a, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0xc91b, 0x69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x9169, 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0x916a, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x916b, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x916c, 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x916d, 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 0x916e, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 0x916f, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0x9170, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0x9171, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0x9172, 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x9173, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x9174, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0x9175, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x9176, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x9177, 0xd3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x9178, 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x9179, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x917a, 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 0xc91c, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 0xc91d, 0xbe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0xc91e, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 0xc91f, 0x73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 0x9073, 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0x9074, 0xa3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 0x9075, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 0x9076, 0xf5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x9077, 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0x9078, 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0x9079, 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0x907a, 0xa3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x907b, 0xa3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 0x907c, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 0x907d, 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 0x907e, 0xa3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0x907f, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0x9080, 0xc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0x9081, 0x9f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 0x9082, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 0x9083, 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 0x9084, 0x9e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 0x9085, 0xfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0x9086, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 0x9087, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 0x9088, 0xea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0xc920, 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 0xc921, 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 0xc922, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 0xc923, 0x89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0x9089, 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 0x908a, 0xd3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0x908b, 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0x908c, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 0x908d, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0x908e, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0x908f, 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0x9090, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 0x9091, 0xd3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0x9092, 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0x9093, 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 0x9094, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 0x9095, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 0x9096, 0x47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0x9097, 0x3d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 0xc924, 0x45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 0xc925, 0xca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0xc926, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0xc927, 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0x9098, 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0x9099, 0x77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x909a, 0xd6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 0x909b, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0x909c, 0x45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0x909d, 0xcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0xc928, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 0xc929, 0xd5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 0xc92a, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0xc92b, 0x9e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 0x909e, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x909f, 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 0x90a0, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 0x90a1, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 0x90a2, 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0x90a3, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0x90a4, 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 0x90a5, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 0x90a6, 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 0x90a7, 0xbf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0x90a8, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 0x90a9, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 0x90aa, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0x90ab, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0x90ac, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 0x90ad, 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 0x90ae, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0x90af, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0x90b0, 0xc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 0x90b1, 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 0x90b2, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0x90b3, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x90b4, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0x90b5, 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0x90b6, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 0x90b7, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 0x90b8, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 0x90b9, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0x90ba, 0xda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 0xc92c, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0xc92d, 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 0xc92e, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0xc92f, 0xbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0x90bb, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0x90bc, 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 0x90bd, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0x90be, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 0x90bf, 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0x90c0, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 0x90c1, 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0x90c2, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0x90c3, 0xc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0x90c4, 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0x90c5, 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x90c6, 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0x90c7, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x90c8, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0x90c9, 0xd3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x90ca, 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0x90cb, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x90cc, 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 0x90cd, 0xbf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0xc930, 0x72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0xc931, 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0xc932, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0xc933, 0x3b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0x913b, 0x7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0x913c, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0x913d, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0x913e, 0x7b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0x913f, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 0x9140, 0x72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0x9141, 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0xc934, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0xc935, 0xae,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0xc936, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 0xc937, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0x90d2, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0x90d3, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0x90d4, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0x90d5, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0x90d6, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0x90d7, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0x90d8, 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0xc938, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0xc939, 0xb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0xc93a, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0xc93b, 0xd9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x90d9, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0x90da, 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x90db, 0xba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 0x90dc, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 0x90dd, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 0x90de, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 0x90df, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x90e0, 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 0x90e1, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0x90e2, 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 0x90e3, 0xef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x90e4, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x90e5, 0xa3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 0x90e6, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0x90e7, 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0x90e8, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x90e9, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x90ea, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0x90eb, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0x90ec, 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x90ed, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0x90ee, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0x90ef, 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0xc93c, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0xc93d, 0x79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0xc93e, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0xc93f, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x90f0, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0x90f1, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0x90f2, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0x90f3, 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 0x90f4, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x90f5, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0x90f6, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0xc940, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0xc941, 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0xc942, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0xc943, 0xf7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0x90f7, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0x90f8, 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0x90f9, 0xba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 0x90fa, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0x90fb, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0x90fc, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x90fd, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 0x90fe, 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0x90ff, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 0x9100, 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0x9101, 0xef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0x9102, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0x9103, 0xa3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 0x9104, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0x9105, 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0x9106, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0x9107, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0x9108, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0x9109, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 0x910a, 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0x910b, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0x910c, 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0x910d, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0xc944, 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0xc945, 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0xc946, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0xc947, 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0x910e, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0x910f, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 0x9110, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0x9111, 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0x9112, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0x9113, 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0x9114, 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0xc948, 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0xc949, 0x45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 0xc94a, 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0xc94b, 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0x9115, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x9116, 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 0x9117, 0xba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0x9118, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0x9119, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 0x911a, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0x911b, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x911c, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0x911d, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 0x911e, 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0x911f, 0xef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 0x9120, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0x9121, 0xa3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x9122, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0x9123, 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x9124, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x9125, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0x9126, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0x9127, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x9128, 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0x9129, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x912a, 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0x912b, 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0xc900, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0x0000, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const u16 vs6624_p2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x806f, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0x058c, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0x0000, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const u16 vs6624_run_setup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0x1d18, 0x00, /* Enableconstrainedwhitebalance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) VS6624_PEAK_MIN_OUT_G_MSB, 0x3c, /* Damper PeakGain Output MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) VS6624_PEAK_MIN_OUT_G_LSB, 0x66, /* Damper PeakGain Output LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) VS6624_CM_LOW_THR_MSB, 0x65, /* Damper Low MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) VS6624_CM_LOW_THR_LSB, 0xd1, /* Damper Low LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) VS6624_CM_HIGH_THR_MSB, 0x66, /* Damper High MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) VS6624_CM_HIGH_THR_LSB, 0x62, /* Damper High LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) VS6624_CM_MIN_OUT_MSB, 0x00, /* Damper Min output MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) VS6624_CM_MIN_OUT_LSB, 0x00, /* Damper Min output LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) VS6624_NORA_DISABLE, 0x00, /* Nora fDisable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) VS6624_NORA_USAGE, 0x04, /* Nora usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) VS6624_NORA_LOW_THR_MSB, 0x63, /* Damper Low MSB Changed 0x63 to 0x65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) VS6624_NORA_LOW_THR_LSB, 0xd1, /* Damper Low LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) VS6624_NORA_HIGH_THR_MSB, 0x68, /* Damper High MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) VS6624_NORA_HIGH_THR_LSB, 0xdd, /* Damper High LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) VS6624_NORA_MIN_OUT_MSB, 0x3a, /* Damper Min output MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) VS6624_NORA_MIN_OUT_LSB, 0x00, /* Damper Min output LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) VS6624_F2B_DISABLE, 0x00, /* Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 0x1d8a, 0x30, /* MAXWeightHigh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 0x1d91, 0x62, /* fpDamperLowThresholdHigh MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 0x1d92, 0x4a, /* fpDamperLowThresholdHigh LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 0x1d95, 0x65, /* fpDamperHighThresholdHigh MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0x1d96, 0x0e, /* fpDamperHighThresholdHigh LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0x1da1, 0x3a, /* fpMinimumDamperOutputLow MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0x1da2, 0xb8, /* fpMinimumDamperOutputLow LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0x1e08, 0x06, /* MAXWeightLow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0x1e0a, 0x0a, /* MAXWeightHigh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0x1601, 0x3a, /* Red A MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0x1602, 0x14, /* Red A LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x1605, 0x3b, /* Blue A MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0x1606, 0x85, /* BLue A LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0x1609, 0x3b, /* RED B MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 0x160a, 0x85, /* RED B LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 0x160d, 0x3a, /* Blue B MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 0x160e, 0x14, /* Blue B LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0x1611, 0x30, /* Max Distance from Locus MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0x1612, 0x8f, /* Max Distance from Locus MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x1614, 0x01, /* Enable constrainer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0x0000, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const u16 vs6624_default[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) VS6624_CONTRAST0, 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) VS6624_SATURATION0, 0x75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) VS6624_GAMMA0, 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) VS6624_CONTRAST1, 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) VS6624_SATURATION1, 0x75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) VS6624_GAMMA1, 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) VS6624_MAN_RG, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) VS6624_MAN_GG, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) VS6624_MAN_BG, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) VS6624_WB_MODE, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) VS6624_EXPO_COMPENSATION, 0xfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) VS6624_EXPO_METER, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) VS6624_LIGHT_FREQ, 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) VS6624_PEAK_GAIN, 0xe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) VS6624_PEAK_LOW_THR, 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) VS6624_HMIRROR0, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) VS6624_VFLIP0, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) VS6624_ZOOM_HSTEP0_MSB, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) VS6624_ZOOM_HSTEP0_LSB, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) VS6624_ZOOM_VSTEP0_MSB, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) VS6624_ZOOM_VSTEP0_LSB, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) VS6624_PAN_HSTEP0_MSB, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) VS6624_PAN_HSTEP0_LSB, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) VS6624_PAN_VSTEP0_MSB, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) VS6624_PAN_VSTEP0_LSB, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) VS6624_SENSOR_MODE, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) VS6624_SYNC_CODE_SETUP, 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) VS6624_DISABLE_FR_DAMPER, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) VS6624_FR_DEN, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) VS6624_FR_NUM_LSB, 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) VS6624_INIT_PIPE_SETUP, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) VS6624_IMG_FMT0, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) VS6624_YUV_SETUP, 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) VS6624_IMAGE_SIZE0, 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 0x0000, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static inline struct vs6624 *to_vs6624(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return container_of(sd, struct vs6624, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return &container_of(ctrl->handler, struct vs6624, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int vs6624_read(struct v4l2_subdev *sd, u16 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) buf[0] = index >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) buf[1] = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) i2c_master_send(client, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) i2c_master_recv(client, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int vs6624_write(struct v4l2_subdev *sd, u16 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) buf[0] = index >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) buf[1] = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) buf[2] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return i2c_master_send(client, buf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int vs6624_writeregs(struct v4l2_subdev *sd, const u16 *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) while (*regs != 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) reg = *regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) data = *regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) vs6624_write(sd, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int vs6624_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) vs6624_write(sd, VS6624_CONTRAST0, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) vs6624_write(sd, VS6624_SATURATION0, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) vs6624_write(sd, VS6624_HMIRROR0, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) vs6624_write(sd, VS6624_VFLIP0, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int vs6624_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (code->pad || code->index >= ARRAY_SIZE(vs6624_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) code->code = vs6624_formats[code->index].mbus_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int vs6624_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct v4l2_mbus_framefmt *fmt = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct vs6624 *sensor = to_vs6624(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (index = 0; index < ARRAY_SIZE(vs6624_formats); index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (vs6624_formats[index].mbus_code == fmt->code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (index >= ARRAY_SIZE(vs6624_formats)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* default to first format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) fmt->code = vs6624_formats[0].mbus_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* sensor mode is VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (fmt->width > VGA_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) fmt->width = VGA_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (fmt->height > VGA_HEIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) fmt->height = VGA_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) fmt->width = fmt->width & (~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) fmt->height = fmt->height & (~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) fmt->colorspace = vs6624_formats[index].colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) cfg->try_fmt = *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* set image format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) switch (fmt->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) vs6624_write(sd, VS6624_IMG_FMT0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) vs6624_write(sd, VS6624_YUV_SETUP, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case MEDIA_BUS_FMT_YUYV8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) vs6624_write(sd, VS6624_IMG_FMT0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) vs6624_write(sd, VS6624_YUV_SETUP, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case MEDIA_BUS_FMT_RGB565_2X8_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) vs6624_write(sd, VS6624_IMG_FMT0, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) vs6624_write(sd, VS6624_RGB_SETUP, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* set image size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if ((fmt->width == VGA_WIDTH) && (fmt->height == VGA_HEIGHT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) else if ((fmt->width == QVGA_WIDTH) && (fmt->height == QVGA_HEIGHT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) else if ((fmt->width == QQVGA_WIDTH) && (fmt->height == QQVGA_HEIGHT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else if ((fmt->width == CIF_WIDTH) && (fmt->height == CIF_HEIGHT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) else if ((fmt->width == QCIF_WIDTH) && (fmt->height == QCIF_HEIGHT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) else if ((fmt->width == QQCIF_WIDTH) && (fmt->height == QQCIF_HEIGHT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) vs6624_write(sd, VS6624_IMAGE_SIZE0, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) vs6624_write(sd, VS6624_MAN_HSIZE0_MSB, fmt->width >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) vs6624_write(sd, VS6624_MAN_HSIZE0_LSB, fmt->width & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) vs6624_write(sd, VS6624_MAN_VSIZE0_MSB, fmt->height >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) vs6624_write(sd, VS6624_MAN_VSIZE0_LSB, fmt->height & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) vs6624_write(sd, VS6624_CROP_CTRL0, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sensor->fmt = *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int vs6624_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct vs6624 *sensor = to_vs6624(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) format->format = sensor->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static int vs6624_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct v4l2_subdev_frame_interval *ival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct vs6624 *sensor = to_vs6624(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ival->interval.numerator = sensor->frame_rate.denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ival->interval.denominator = sensor->frame_rate.numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int vs6624_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct v4l2_subdev_frame_interval *ival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct vs6624 *sensor = to_vs6624(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct v4l2_fract *tpf = &ival->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (tpf->numerator == 0 || tpf->denominator == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) || (tpf->denominator > tpf->numerator * MAX_FRAME_RATE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* reset to max frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) tpf->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) tpf->denominator = MAX_FRAME_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) sensor->frame_rate.numerator = tpf->denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) sensor->frame_rate.denominator = tpf->numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) vs6624_write(sd, VS6624_DISABLE_FR_DAMPER, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) vs6624_write(sd, VS6624_FR_NUM_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) sensor->frame_rate.numerator >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) vs6624_write(sd, VS6624_FR_NUM_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) sensor->frame_rate.numerator & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) vs6624_write(sd, VS6624_FR_DEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) sensor->frame_rate.denominator & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int vs6624_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) vs6624_write(sd, VS6624_USER_CMD, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) vs6624_write(sd, VS6624_USER_CMD, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int vs6624_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) reg->val = vs6624_read(sd, reg->reg & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int vs6624_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) vs6624_write(sd, reg->reg & 0xffff, reg->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const struct v4l2_ctrl_ops vs6624_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .s_ctrl = vs6624_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static const struct v4l2_subdev_core_ops vs6624_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .g_register = vs6624_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .s_register = vs6624_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const struct v4l2_subdev_video_ops vs6624_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .s_frame_interval = vs6624_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .g_frame_interval = vs6624_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .s_stream = vs6624_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const struct v4l2_subdev_pad_ops vs6624_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .enum_mbus_code = vs6624_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .get_fmt = vs6624_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .set_fmt = vs6624_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const struct v4l2_subdev_ops vs6624_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .core = &vs6624_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .video = &vs6624_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .pad = &vs6624_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int vs6624_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct vs6624 *sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct v4l2_ctrl_handler *hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) const unsigned *ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ce = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ce == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = devm_gpio_request_one(&client->dev, *ce, GPIOF_OUT_INIT_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "VS6624 Chip Enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) v4l_err(client, "failed to request GPIO %d\n", *ce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* wait 100ms before any further i2c writes are performed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (sensor == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) sd = &sensor->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) v4l2_i2c_subdev_init(sd, client, &vs6624_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) vs6624_writeregs(sd, vs6624_p1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) vs6624_write(sd, VS6624_MICRO_EN, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) vs6624_write(sd, VS6624_DIO_EN, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) vs6624_writeregs(sd, vs6624_p2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) vs6624_writeregs(sd, vs6624_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) vs6624_write(sd, VS6624_HSYNC_SETUP, 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) vs6624_writeregs(sd, vs6624_run_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* set frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) sensor->frame_rate.numerator = MAX_FRAME_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) sensor->frame_rate.denominator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) vs6624_write(sd, VS6624_DISABLE_FR_DAMPER, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) vs6624_write(sd, VS6624_FR_NUM_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) sensor->frame_rate.numerator >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) vs6624_write(sd, VS6624_FR_NUM_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) sensor->frame_rate.numerator & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) vs6624_write(sd, VS6624_FR_DEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) sensor->frame_rate.denominator & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) sensor->fmt = vs6624_default_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) sensor->ce_pin = *ce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) v4l_info(client, "chip found @ 0x%02x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) hdl = &sensor->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) v4l2_ctrl_handler_init(hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) v4l2_ctrl_new_std(hdl, &vs6624_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) V4L2_CID_CONTRAST, 0, 0xFF, 1, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) v4l2_ctrl_new_std(hdl, &vs6624_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) V4L2_CID_SATURATION, 0, 0xFF, 1, 0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) v4l2_ctrl_new_std(hdl, &vs6624_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) v4l2_ctrl_new_std(hdl, &vs6624_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* hook the control handler into the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) sd->ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int err = hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* initialize the hardware to the default control values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ret = v4l2_ctrl_handler_setup(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int vs6624_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) v4l2_ctrl_handler_free(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct i2c_device_id vs6624_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {"vs6624", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) MODULE_DEVICE_TABLE(i2c, vs6624_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static struct i2c_driver vs6624_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .name = "vs6624",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .probe = vs6624_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .remove = vs6624_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .id_table = vs6624_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) module_i2c_driver(vs6624_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) MODULE_DESCRIPTION("VS6624 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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