^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * video-i2c.c - Support for I2C transport video devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Matt Ranostay <matt.ranostay@konsulko.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Supported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - Panasonic AMG88xx Grid-Eye Sensors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * - Melexis MLX90640 Thermal Cameras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/freezer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-fh.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/videobuf2-v4l2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/videobuf2-vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VIDEO_I2C_DRIVER "video-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct video_i2c_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct video_i2c_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct vb2_v4l2_buffer vb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct video_i2c_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct video_i2c_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct mutex queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct v4l2_device v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct video_device vdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct vb2_queue vb_vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct task_struct *kthread_vid_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct list_head vid_cap_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct v4l2_fract frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const struct v4l2_fmtdesc amg88xx_format = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .pixelformat = V4L2_PIX_FMT_Y12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct v4l2_frmsize_discrete amg88xx_size = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .height = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct v4l2_fmtdesc mlx90640_format = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .pixelformat = V4L2_PIX_FMT_Y16_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct v4l2_frmsize_discrete mlx90640_size = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .width = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .height = 26, /* 24 lines of pixel data + 2 lines of processing data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct regmap_config amg88xx_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .max_register = 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct regmap_config mlx90640_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct video_i2c_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* video dimensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const struct v4l2_fmtdesc *format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const struct v4l2_frmsize_discrete *size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* available frame intervals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const struct v4l2_fract *frame_intervals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int num_frame_intervals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* pixel buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* pixel size in bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct regmap_config *regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct nvmem_config *nvmem_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* setup function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int (*setup)(struct video_i2c_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* xfer function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int (*xfer)(struct video_i2c_data *data, char *buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* power control function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int (*set_power)(struct video_i2c_data *data, bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* hwmon init function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int (*hwmon_init)(struct video_i2c_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int mlx90640_nvram_read(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct video_i2c_data *data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return regmap_bulk_read(data->regmap, 0x2400 + offset, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct nvmem_config mlx90640_nvram_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "mlx90640_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .word_size = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .size = 1664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .reg_read = mlx90640_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Power control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AMG88XX_REG_PCTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AMG88XX_PCTL_NORMAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AMG88XX_PCTL_SLEEP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AMG88XX_REG_RST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AMG88XX_RST_FLAG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AMG88XX_RST_INIT 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Frame rate register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AMG88XX_REG_FPSC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AMG88XX_FPSC_1FPS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Thermistor register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AMG88XX_REG_TTHL 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Temperature register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AMG88XX_REG_T01L 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MLX90640_REG_CTL1 0x800d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MLX90640_REG_CTL1_MASK 0x0380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MLX90640_REG_CTL1_MASK_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int amg88xx_xfer(struct video_i2c_data *data, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return regmap_bulk_read(data->regmap, AMG88XX_REG_T01L, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) data->chip->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int mlx90640_xfer(struct video_i2c_data *data, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return regmap_bulk_read(data->regmap, 0x400, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) data->chip->buffer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int amg88xx_setup(struct video_i2c_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int mask = AMG88XX_FPSC_1FPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (data->frame_interval.numerator == data->frame_interval.denominator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) val = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return regmap_update_bits(data->regmap, AMG88XX_REG_FPSC, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int mlx90640_setup(struct video_i2c_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int n, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) for (n = 0; n < data->chip->num_frame_intervals - 1; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (V4L2_FRACT_COMPARE(data->frame_interval, ==,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) data->chip->frame_intervals[n]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) idx = data->chip->num_frame_intervals - n - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return regmap_update_bits(data->regmap, MLX90640_REG_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MLX90640_REG_CTL1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) idx << MLX90640_REG_CTL1_MASK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int amg88xx_set_power_on(struct video_i2c_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret = regmap_write(data->regmap, AMG88XX_REG_PCTL, AMG88XX_PCTL_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = regmap_write(data->regmap, AMG88XX_REG_RST, AMG88XX_RST_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = regmap_write(data->regmap, AMG88XX_REG_RST, AMG88XX_RST_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Wait two frames before reading thermistor and temperature registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int amg88xx_set_power_off(struct video_i2c_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = regmap_write(data->regmap, AMG88XX_REG_PCTL, AMG88XX_PCTL_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Wait for a while to avoid resuming normal mode immediately after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * entering sleep mode, otherwise the device occasionally goes wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * (thermistor and temperature registers are not updated at all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int amg88xx_set_power(struct video_i2c_data *data, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return amg88xx_set_power_on(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return amg88xx_set_power_off(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #if IS_REACHABLE(CONFIG_HWMON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const u32 amg88xx_temp_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) HWMON_T_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct hwmon_channel_info amg88xx_temp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .type = hwmon_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .config = amg88xx_temp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct hwmon_channel_info *amg88xx_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) &amg88xx_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static umode_t amg88xx_is_visible(const void *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int amg88xx_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct video_i2c_data *data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __le16 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tmp = pm_runtime_get_sync(regmap_get_device(data->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (tmp < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pm_runtime_put_noidle(regmap_get_device(data->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tmp = regmap_bulk_read(data->regmap, AMG88XX_REG_TTHL, &buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pm_runtime_mark_last_busy(regmap_get_device(data->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pm_runtime_put_autosuspend(regmap_get_device(data->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tmp = le16_to_cpu(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * Check for sign bit, this isn't a two's complement value but an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * absolute temperature that needs to be inverted in the case of being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * negative.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (tmp & BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) tmp = -(tmp & 0x7ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *val = (tmp * 625) / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct hwmon_ops amg88xx_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .is_visible = amg88xx_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .read = amg88xx_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct hwmon_chip_info amg88xx_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .ops = &amg88xx_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .info = amg88xx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int amg88xx_hwmon_init(struct video_i2c_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct device *dev = regmap_get_device(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void *hwmon = devm_hwmon_device_register_with_info(dev, "amg88xx", data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) &amg88xx_chip_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return PTR_ERR_OR_ZERO(hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define amg88xx_hwmon_init NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) AMG88XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MLX90640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const struct v4l2_fract amg88xx_frame_intervals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 1, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct v4l2_fract mlx90640_frame_intervals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { 1, 64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { 1, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { 1, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { 1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { 1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { 1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { 2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct video_i2c_chip video_i2c_chip[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [AMG88XX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .size = &amg88xx_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .format = &amg88xx_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .frame_intervals = amg88xx_frame_intervals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .num_frame_intervals = ARRAY_SIZE(amg88xx_frame_intervals),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .buffer_size = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .regmap_config = &amg88xx_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .setup = &amg88xx_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .xfer = &amg88xx_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .set_power = amg88xx_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .hwmon_init = amg88xx_hwmon_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [MLX90640] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .size = &mlx90640_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .format = &mlx90640_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .frame_intervals = mlx90640_frame_intervals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .num_frame_intervals = ARRAY_SIZE(mlx90640_frame_intervals),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .buffer_size = 1664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .regmap_config = &mlx90640_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .nvmem_config = &mlx90640_nvram_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .setup = mlx90640_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .xfer = mlx90640_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct v4l2_file_operations video_i2c_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .open = v4l2_fh_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .release = vb2_fop_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .poll = vb2_fop_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .read = vb2_fop_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .mmap = vb2_fop_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .unlocked_ioctl = video_ioctl2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int queue_setup(struct vb2_queue *vq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned int *nbuffers, unsigned int *nplanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int sizes[], struct device *alloc_devs[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct video_i2c_data *data = vb2_get_drv_priv(vq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int size = data->chip->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (vq->num_buffers + *nbuffers < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *nbuffers = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (*nplanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return sizes[0] < size ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *nplanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) sizes[0] = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int buffer_prepare(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct video_i2c_data *data = vb2_get_drv_priv(vb->vb2_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int size = data->chip->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (vb2_plane_size(vb, 0) < size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) vbuf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) vb2_set_plane_payload(vb, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static void buffer_queue(struct vb2_buffer *vb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct video_i2c_data *data = vb2_get_drv_priv(vb->vb2_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct video_i2c_buffer *buf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) container_of(vbuf, struct video_i2c_buffer, vb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) spin_lock(&data->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) list_add_tail(&buf->list, &data->vid_cap_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) spin_unlock(&data->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int video_i2c_thread_vid_cap(void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct video_i2c_data *data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int delay = mult_frac(HZ, data->frame_interval.numerator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) data->frame_interval.denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) set_freezable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned long start_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct video_i2c_buffer *vid_cap_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int schedule_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) try_to_freeze();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) spin_lock(&data->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!list_empty(&data->vid_cap_active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) vid_cap_buf = list_last_entry(&data->vid_cap_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct video_i2c_buffer, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) list_del(&vid_cap_buf->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) spin_unlock(&data->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (vid_cap_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct vb2_buffer *vb2_buf = &vid_cap_buf->vb.vb2_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) void *vbuf = vb2_plane_vaddr(vb2_buf, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = data->chip->xfer(data, vbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) vb2_buf->timestamp = ktime_get_ns();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) vid_cap_buf->vb.sequence = data->sequence++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) vb2_buffer_done(vb2_buf, ret ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) schedule_delay = delay - (jiffies - start_jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (time_after(jiffies, start_jiffies + delay))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) schedule_delay = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) schedule_timeout_interruptible(schedule_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } while (!kthread_should_stop());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static void video_i2c_del_list(struct vb2_queue *vq, enum vb2_buffer_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct video_i2c_data *data = vb2_get_drv_priv(vq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct video_i2c_buffer *buf, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) spin_lock(&data->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) list_for_each_entry_safe(buf, tmp, &data->vid_cap_active, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) list_del(&buf->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) vb2_buffer_done(&buf->vb.vb2_buf, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) spin_unlock(&data->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int start_streaming(struct vb2_queue *vq, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct video_i2c_data *data = vb2_get_drv_priv(vq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct device *dev = regmap_get_device(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (data->kthread_vid_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) goto error_del_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = data->chip->setup(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto error_rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) data->sequence = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) data->kthread_vid_cap = kthread_run(video_i2c_thread_vid_cap, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "%s-vid-cap", data->v4l2_dev.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = PTR_ERR_OR_ZERO(data->kthread_vid_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) error_rpm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) error_del_list:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) video_i2c_del_list(vq, VB2_BUF_STATE_QUEUED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void stop_streaming(struct vb2_queue *vq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct video_i2c_data *data = vb2_get_drv_priv(vq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (data->kthread_vid_cap == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) kthread_stop(data->kthread_vid_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) data->kthread_vid_cap = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pm_runtime_mark_last_busy(regmap_get_device(data->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pm_runtime_put_autosuspend(regmap_get_device(data->regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) video_i2c_del_list(vq, VB2_BUF_STATE_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct vb2_ops video_i2c_video_qops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .queue_setup = queue_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .buf_prepare = buffer_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .buf_queue = buffer_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .start_streaming = start_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .stop_streaming = stop_streaming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .wait_prepare = vb2_ops_wait_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .wait_finish = vb2_ops_wait_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int video_i2c_querycap(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct v4l2_capability *vcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct video_i2c_data *data = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct device *dev = regmap_get_device(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) strscpy(vcap->driver, data->v4l2_dev.name, sizeof(vcap->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) strscpy(vcap->card, data->vdev.name, sizeof(vcap->card));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) sprintf(vcap->bus_info, "I2C:%d-%d", client->adapter->nr, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int video_i2c_g_input(struct file *file, void *fh, unsigned int *inp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *inp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int video_i2c_s_input(struct file *file, void *fh, unsigned int inp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return (inp > 0) ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int video_i2c_enum_input(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct v4l2_input *vin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (vin->index > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) strscpy(vin->name, "Camera", sizeof(vin->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) vin->type = V4L2_INPUT_TYPE_CAMERA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int video_i2c_enum_fmt_vid_cap(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct v4l2_fmtdesc *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct video_i2c_data *data = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) enum v4l2_buf_type type = fmt->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (fmt->index > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) *fmt = *data->chip->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) fmt->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int video_i2c_enum_framesizes(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct v4l2_frmsizeenum *fsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) const struct video_i2c_data *data = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) const struct v4l2_frmsize_discrete *size = data->chip->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* currently only one frame size is allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (fsize->index > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (fsize->pixel_format != data->chip->format->pixelformat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) fsize->discrete.width = size->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) fsize->discrete.height = size->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int video_i2c_enum_frameintervals(struct file *file, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct v4l2_frmivalenum *fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) const struct video_i2c_data *data = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) const struct v4l2_frmsize_discrete *size = data->chip->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (fe->index >= data->chip->num_frame_intervals)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (fe->width != size->width || fe->height != size->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) fe->type = V4L2_FRMIVAL_TYPE_DISCRETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) fe->discrete = data->chip->frame_intervals[fe->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int video_i2c_try_fmt_vid_cap(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct v4l2_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) const struct video_i2c_data *data = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) const struct v4l2_frmsize_discrete *size = data->chip->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct v4l2_pix_format *pix = &fmt->fmt.pix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned int bpp = data->chip->bpp / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pix->width = size->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pix->height = size->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pix->pixelformat = data->chip->format->pixelformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) pix->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) pix->bytesperline = pix->width * bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pix->sizeimage = pix->bytesperline * pix->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pix->colorspace = V4L2_COLORSPACE_RAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int video_i2c_s_fmt_vid_cap(struct file *file, void *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct v4l2_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct video_i2c_data *data = video_drvdata(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (vb2_is_busy(&data->vb_vidq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return video_i2c_try_fmt_vid_cap(file, fh, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int video_i2c_g_parm(struct file *filp, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct v4l2_streamparm *parm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct video_i2c_data *data = video_drvdata(filp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) parm->parm.capture.readbuffers = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) parm->parm.capture.timeperframe = data->frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int video_i2c_s_parm(struct file *filp, void *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct v4l2_streamparm *parm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct video_i2c_data *data = video_drvdata(filp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) for (i = 0; i < data->chip->num_frame_intervals - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (V4L2_FRACT_COMPARE(parm->parm.capture.timeperframe, <=,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) data->chip->frame_intervals[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) data->frame_interval = data->chip->frame_intervals[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return video_i2c_g_parm(filp, priv, parm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const struct v4l2_ioctl_ops video_i2c_ioctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .vidioc_querycap = video_i2c_querycap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .vidioc_g_input = video_i2c_g_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .vidioc_s_input = video_i2c_s_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .vidioc_enum_input = video_i2c_enum_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .vidioc_enum_fmt_vid_cap = video_i2c_enum_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .vidioc_enum_framesizes = video_i2c_enum_framesizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .vidioc_enum_frameintervals = video_i2c_enum_frameintervals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .vidioc_g_fmt_vid_cap = video_i2c_try_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .vidioc_s_fmt_vid_cap = video_i2c_s_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .vidioc_g_parm = video_i2c_g_parm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .vidioc_s_parm = video_i2c_s_parm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .vidioc_try_fmt_vid_cap = video_i2c_try_fmt_vid_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .vidioc_reqbufs = vb2_ioctl_reqbufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .vidioc_create_bufs = vb2_ioctl_create_bufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .vidioc_querybuf = vb2_ioctl_querybuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .vidioc_qbuf = vb2_ioctl_qbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .vidioc_dqbuf = vb2_ioctl_dqbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .vidioc_streamon = vb2_ioctl_streamon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .vidioc_streamoff = vb2_ioctl_streamoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static void video_i2c_release(struct video_device *vdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct video_i2c_data *data = video_get_drvdata(vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) v4l2_device_unregister(&data->v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mutex_destroy(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) mutex_destroy(&data->queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) regmap_exit(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int video_i2c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct video_i2c_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct v4l2_device *v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct vb2_queue *queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (dev_fwnode(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) data->chip = device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) else if (id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) data->chip = &video_i2c_chip[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) goto error_free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) data->regmap = regmap_init_i2c(client, data->chip->regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) goto error_free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) v4l2_dev = &data->v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) strscpy(v4l2_dev->name, VIDEO_I2C_DRIVER, sizeof(v4l2_dev->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = v4l2_device_register(&client->dev, v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) goto error_regmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mutex_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mutex_init(&data->queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) queue = &data->vb_vidq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) queue->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) queue->io_modes = VB2_DMABUF | VB2_MMAP | VB2_USERPTR | VB2_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) queue->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) queue->drv_priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) queue->buf_struct_size = sizeof(struct video_i2c_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) queue->min_buffers_needed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) queue->ops = &video_i2c_video_qops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) queue->mem_ops = &vb2_vmalloc_memops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = vb2_queue_init(queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) goto error_unregister_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) data->vdev.queue = queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) data->vdev.queue->lock = &data->queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) snprintf(data->vdev.name, sizeof(data->vdev.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "I2C %d-%d Transport Video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) client->adapter->nr, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) data->vdev.v4l2_dev = v4l2_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) data->vdev.fops = &video_i2c_fops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) data->vdev.lock = &data->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) data->vdev.ioctl_ops = &video_i2c_ioctl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) data->vdev.release = video_i2c_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) data->vdev.device_caps = V4L2_CAP_VIDEO_CAPTURE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) spin_lock_init(&data->slock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) INIT_LIST_HEAD(&data->vid_cap_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) data->frame_interval = data->chip->frame_intervals[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) video_set_drvdata(&data->vdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (data->chip->set_power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ret = data->chip->set_power(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) goto error_unregister_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) pm_runtime_get_noresume(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) pm_runtime_set_active(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pm_runtime_enable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pm_runtime_set_autosuspend_delay(&client->dev, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) pm_runtime_use_autosuspend(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (data->chip->hwmon_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ret = data->chip->hwmon_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "failed to register hwmon device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (data->chip->nvmem_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct nvmem_config *config = data->chip->nvmem_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct nvmem_device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) config->priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) config->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) device = devm_nvmem_register(&client->dev, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (IS_ERR(device)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) "failed to register nvmem device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret = video_register_device(&data->vdev, VFL_TYPE_VIDEO, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) goto error_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) pm_runtime_mark_last_busy(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) pm_runtime_put_autosuspend(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) error_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (data->chip->set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) data->chip->set_power(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) error_unregister_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) v4l2_device_unregister(v4l2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mutex_destroy(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) mutex_destroy(&data->queue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) error_regmap_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) regmap_exit(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) error_free_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int video_i2c_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct video_i2c_data *data = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (data->chip->set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) data->chip->set_power(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) video_unregister_device(&data->vdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int video_i2c_pm_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct video_i2c_data *data = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (!data->chip->set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return data->chip->set_power(data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int video_i2c_pm_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct video_i2c_data *data = i2c_get_clientdata(to_i2c_client(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!data->chip->set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return data->chip->set_power(data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static const struct dev_pm_ops video_i2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) SET_RUNTIME_PM_OPS(video_i2c_pm_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) video_i2c_pm_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const struct i2c_device_id video_i2c_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) { "amg88xx", AMG88XX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) { "mlx90640", MLX90640 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) MODULE_DEVICE_TABLE(i2c, video_i2c_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static const struct of_device_id video_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { .compatible = "panasonic,amg88xx", .data = &video_i2c_chip[AMG88XX] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { .compatible = "melexis,mlx90640", .data = &video_i2c_chip[MLX90640] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) MODULE_DEVICE_TABLE(of, video_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static struct i2c_driver video_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .name = VIDEO_I2C_DRIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .of_match_table = video_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .pm = &video_i2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .probe = video_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .remove = video_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .id_table = video_i2c_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) module_i2c_driver(video_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) MODULE_DESCRIPTION("I2C transport video support");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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