^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * upd64031A - NEC Electronics Ghost Reduction for NTSC in Japan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 2003 by T.Adachi <tadachi@tadachi-net.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2003 by Takeru KOMORIYA <komoriya@paken.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2006 by Hans Verkuil <hverkuil@xs4all.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/i2c/upd64031a.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* --------------------- read registers functions define -------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GR_MODE_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DIRECT_3DYCS_CONNECT_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SYNC_CIRCUIT_MASK 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_DESCRIPTION("uPD64031A driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_AUTHOR("T. Adachi, Takeru KOMORIYA, Hans Verkuil");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_PARM_DESC(debug, "Debug level (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) R00 = 0, R01, R02, R03, R04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) R05, R06, R07, R08, R09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) R0A, R0B, R0C, R0D, R0E, R0F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* unused registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) R10, R11, R12, R13, R14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) R15, R16, R17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) TOT_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct upd64031a_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u8 regs[TOT_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u8 gr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 direct_3dycs_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 ext_comp_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 ext_vert_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline struct upd64031a_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return container_of(sd, struct upd64031a_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static u8 upd64031a_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0x00, 0xb8, 0x48, 0xd2, 0xe6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0x03, 0x10, 0x0b, 0xaf, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x00, 0x00, 0x1d, 0x5e, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static u8 upd64031a_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (reg >= sizeof(buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) i2c_master_recv(client, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return buf[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void upd64031a_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) buf[0] = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) v4l2_dbg(1, debug, sd, "write reg: %02X val: %02X\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (i2c_master_send(client, buf, 2) != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) v4l2_err(sd, "I/O error write 0x%02x/0x%02x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* The input changed due to new input or channel changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int upd64031a_s_frequency(struct v4l2_subdev *sd, const struct v4l2_frequency *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct upd64031a_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 reg = state->regs[R00];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) v4l2_dbg(1, debug, sd, "changed input or channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) upd64031a_write(sd, R00, reg | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) upd64031a_write(sd, R00, reg & ~0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int upd64031a_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct upd64031a_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 r00, r05, r08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) state->gr_mode = (input & 3) << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) state->direct_3dycs_connect = (input & 0xc) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) state->ext_comp_sync =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) (input & UPD64031A_COMPOSITE_EXTERNAL) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) state->ext_vert_sync =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) (input & UPD64031A_VERTICAL_EXTERNAL) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) r00 = (state->regs[R00] & ~GR_MODE_MASK) | state->gr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) r05 = (state->regs[R00] & ~SYNC_CIRCUIT_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) state->ext_comp_sync | state->ext_vert_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) r08 = (state->regs[R08] & ~DIRECT_3DYCS_CONNECT_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) state->direct_3dycs_connect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) upd64031a_write(sd, R00, r00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) upd64031a_write(sd, R05, r05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) upd64031a_write(sd, R08, r08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return upd64031a_s_frequency(sd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int upd64031a_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) v4l2_info(sd, "Status: SA00=0x%02x SA01=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) upd64031a_read(sd, 0), upd64031a_read(sd, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int upd64031a_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg->val = upd64031a_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int upd64031a_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) upd64031a_write(sd, reg->reg & 0xff, reg->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct v4l2_subdev_core_ops upd64031a_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .log_status = upd64031a_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .g_register = upd64031a_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .s_register = upd64031a_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct v4l2_subdev_tuner_ops upd64031a_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .s_frequency = upd64031a_s_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct v4l2_subdev_video_ops upd64031a_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .s_routing = upd64031a_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct v4l2_subdev_ops upd64031a_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .core = &upd64031a_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .tuner = &upd64031a_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .video = &upd64031a_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* i2c implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int upd64031a_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct upd64031a_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) v4l_info(client, "chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) v4l2_i2c_subdev_init(sd, client, &upd64031a_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) memcpy(state->regs, upd64031a_init, sizeof(state->regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) state->gr_mode = UPD64031A_GR_ON << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) state->direct_3dycs_connect = UPD64031A_3DYCS_COMPOSITE << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) state->ext_comp_sync = state->ext_vert_sync = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for (i = 0; i < TOT_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) upd64031a_write(sd, i, state->regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int upd64031a_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct i2c_device_id upd64031a_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { "upd64031a", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MODULE_DEVICE_TABLE(i2c, upd64031a_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct i2c_driver upd64031a_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .name = "upd64031a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .probe = upd64031a_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .remove = upd64031a_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .id_table = upd64031a_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) module_i2c_driver(upd64031a_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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