^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tw9910 Video Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Kuninori Morimoto <morimoto.kuninori@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on ov772x driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 2008 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/i2c/tw9910.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GET_ID(val) ((val & 0xF8) >> 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GET_REV(val) (val & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ID 0x00 /* Product ID Code Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STATUS1 0x01 /* Chip Status Register I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define INFORM 0x02 /* Input Format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OPFORM 0x03 /* Output Format Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OUTCTR1 0x05 /* Output Control I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ACNTL1 0x06 /* Analog Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CROP_HI 0x07 /* Cropping Register, High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VDELAY_LO 0x08 /* Vertical Delay Register, Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VACTIVE_LO 0x09 /* Vertical Active Register, Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CNTRL1 0x0C /* Control Register I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCALE_HI 0x0E /* Scaling Register, High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BRIGHT 0x10 /* BRIGHTNESS Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CONTRAST 0x11 /* CONTRAST Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SHARPNESS 0x12 /* SHARPNESS Control Register I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SAT_U 0x13 /* Chroma (U) Gain Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SAT_V 0x14 /* Chroma (V) Gain Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HUE 0x15 /* Hue Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CORING1 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CORING2 0x18 /* Coring and IF compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VBICNTL 0x19 /* VBI Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ACNTL2 0x1A /* Analog Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OUTCTR2 0x1B /* Output Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SDT 0x1C /* Standard Selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDTR 0x1D /* Standard Recognition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEST 0x1F /* Test Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLMPG 0x20 /* Clamping Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IAGC 0x21 /* Individual AGC Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AGCGAIN 0x22 /* AGC Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PEAKWT 0x23 /* White Peak Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLMPL 0x24 /* Clamp level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SYNCT 0x25 /* Sync Amplitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MISSCNT 0x26 /* Sync Miss Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCLAMP 0x27 /* Clamp Position Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VCNTL1 0x28 /* Vertical Control I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VCNTL2 0x29 /* Vertical Control II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CKILL 0x2A /* Color Killer Level Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define COMB 0x2B /* Comb Filter Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LDLY 0x2C /* Luma Delay and H Filter Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MISC1 0x2D /* Miscellaneous Control I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LOOP 0x2E /* LOOP Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MISC2 0x2F /* Miscellaneous Control II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MVSN 0x30 /* Macrovision Detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define STATUS2 0x31 /* Chip STATUS II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HFREF 0x32 /* H monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLMD 0x33 /* CLAMP MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IDCNTL 0x34 /* ID Detection Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLCNTL1 0x35 /* Clamp Control I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ANAPLLCTL 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VBIMIN 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HSLOWCTL 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define WSS3 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define FILLDATA 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SDID 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DID 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define WSS1 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define WSS2 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define VVBI 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LCTL6 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LCTL7 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LCTL8 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LCTL9 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LCTL10 0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LCTL11 0x5B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LCTL12 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LCTL13 0x5D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LCTL14 0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LCTL15 0x5F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LCTL16 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LCTL17 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LCTL18 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LCTL19 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LCTL20 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LCTL21 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LCTL22 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LCTL23 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LCTL24 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LCTL25 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LCTL26 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HSBEGIN 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HSEND 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OVSDLY 0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OVSEND 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VBIDELAY 0x6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * register detail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* INFORM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define FC27_FF 0x00 /* 0 : Square pixel mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Must use 24.54MHz for 60Hz field rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* source or 29.5MHz for 50Hz field rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IFSEL_S 0x10 /* 01 : S-video decoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IFSEL_C 0x00 /* 00 : Composite video decoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Y input video selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define YSEL_M0 0x00 /* 00 : Mux0 selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define YSEL_M1 0x04 /* 01 : Mux1 selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define YSEL_M2 0x08 /* 10 : Mux2 selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define YSEL_M3 0x10 /* 11 : Mux3 selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* OPFORM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* 1 : ITU-R-656 compatible data sequence format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* 1 : 16-bit YCrCb 4:2:2 output format.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LLCMODE 0x20 /* 1 : LLC output mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* 0 : free-run output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AINC 0x10 /* Serial interface auto-indexing control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* 0 : auto-increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* 1 : non-auto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* 0 : Vertical out ctrl by HACTIVE and DVALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OEN_TRI_SEL_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* OUTCTR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* VS pin output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VSSL_VSYNC 0x00 /* 0 : VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VSSL_VACT 0x10 /* 1 : VACT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VSSL_FIELD 0x20 /* 2 : FIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VSSL_VVALID 0x30 /* 3 : VVALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VSSL_ZERO 0x70 /* 7 : 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* HS pin output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HSSL_HACT 0x00 /* 0 : HACT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HSSL_HSYNC 0x01 /* 1 : HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define HSSL_DVALID 0x02 /* 2 : DVALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HSSL_HLOCK 0x03 /* 3 : HLOCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HSSL_ZERO 0x07 /* 7 : 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* ACNTL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SRESET 0x80 /* resets the device to its default state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * but all register content remain unchanged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * This bit is self-resetting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ACNTL1_PDN_MASK 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_PDN 0x08 /* system clock power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define Y_PDN 0x04 /* Luma ADC power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define C_PDN 0x02 /* Chroma ADC power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* ACNTL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ACNTL2_PDN_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PLL_PDN 0x40 /* PLL power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* VBICNTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* RTSEL : control the real time signal output from the MPOUT pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RTSEL_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RTSEL_VLOSS 0x00 /* 0000 = Video loss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define RTSEL_HLOCK 0x01 /* 0001 = H-lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RTSEL_SLOCK 0x02 /* 0010 = S-lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RTSEL_VLOCK 0x03 /* 0011 = V-lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RTSEL_MONO 0x04 /* 0100 = MONO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RTSEL_DET50 0x05 /* 0101 = DET50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RTSEL_FIELD 0x06 /* 0110 = FIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* HSYNC start and end are constant for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define HSYNC_START 0x0260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HSYNC_END 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct regval_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned char reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned char value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct tw9910_scale_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned short width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned short height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u16 hscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 vscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct tw9910_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct tw9910_video_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct gpio_desc *pdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct gpio_desc *rstb_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) const struct tw9910_scale_ctrl *scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) v4l2_std_id norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "NTSC SQ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .hscale = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .vscale = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "NTSC CCIR601",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .hscale = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .vscale = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = "NTSC SQ (CIF)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .width = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .height = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .hscale = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .vscale = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "NTSC CCIR601 (CIF)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .width = 360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .height = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .hscale = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .vscale = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .name = "NTSC SQ (QCIF)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .width = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .height = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .hscale = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .vscale = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = "NTSC CCIR601 (QCIF)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .width = 180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .height = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .hscale = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .vscale = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct tw9910_scale_ctrl tw9910_pal_scales[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .name = "PAL SQ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .width = 768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .height = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .hscale = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .vscale = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .name = "PAL CCIR601",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .height = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .hscale = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .vscale = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .name = "PAL SQ (CIF)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .width = 384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .height = 288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .hscale = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .vscale = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .name = "PAL CCIR601 (CIF)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .width = 360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .height = 288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .hscale = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .vscale = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = "PAL SQ (QCIF)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .width = 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .height = 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .hscale = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .vscale = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .name = "PAL CCIR601 (QCIF)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .width = 180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .height = 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .hscale = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .vscale = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * general function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct tw9910_priv *to_tw9910(const struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return container_of(i2c_get_clientdata(client), struct tw9910_priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int tw9910_mask_set(struct i2c_client *client, u8 command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 mask, u8 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) s32 val = i2c_smbus_read_byte_data(client, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) val |= set & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return i2c_smbus_write_byte_data(client, command, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int tw9910_set_scale(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) const struct tw9910_scale_ctrl *scale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = i2c_smbus_write_byte_data(client, SCALE_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) (scale->vscale & 0x0F00) >> 4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) (scale->hscale & 0x0F00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = i2c_smbus_write_byte_data(client, HSCALE_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) scale->hscale & 0x00FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = i2c_smbus_write_byte_data(client, VSCALE_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) scale->vscale & 0x00FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int tw9910_set_hsync(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* bit 10 - 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = i2c_smbus_write_byte_data(client, HSBEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (HSYNC_START & 0x07F8) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* bit 10 - 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = i2c_smbus_write_byte_data(client, HSEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) (HSYNC_END & 0x07F8) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* So far only revisions 0 and 1 have been seen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* bit 2 - 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (priv->revision == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = tw9910_mask_set(client, HSLOWCTL, 0x77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) (HSYNC_START & 0x0007) << 4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) (HSYNC_END & 0x0007));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void tw9910_reset(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) tw9910_mask_set(client, ACNTL1, SRESET, SRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) usleep_range(1000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int tw9910_power(struct i2c_client *client, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u8 acntl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u8 acntl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) acntl1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) acntl2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) acntl1 = CLK_PDN | Y_PDN | C_PDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) acntl2 = PLL_PDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct tw9910_scale_ctrl *tw9910_select_norm(v4l2_std_id norm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 width, u32 height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) const struct tw9910_scale_ctrl *scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) const struct tw9910_scale_ctrl *ret = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) __u32 diff = 0xffffffff, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int size, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (norm & V4L2_STD_NTSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) scale = tw9910_ntsc_scales;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) size = ARRAY_SIZE(tw9910_ntsc_scales);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } else if (norm & V4L2_STD_PAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) scale = tw9910_pal_scales;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) size = ARRAY_SIZE(tw9910_pal_scales);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) tmp = abs(width - scale[i].width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) abs(height - scale[i].height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (tmp < diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) diff = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = scale + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * subdevice operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int tw9910_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) switch (priv->revision) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) val = OEN_TRI_SEL_ALL_OFF_r0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) val = OEN_TRI_SEL_ALL_OFF_r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(&client->dev, "un-supported revision\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) val = OEN_TRI_SEL_ALL_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!priv->scale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(&client->dev, "norm select error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_dbg(&client->dev, "%s %dx%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) priv->scale->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) priv->scale->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) priv->scale->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return tw9910_power(client, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int tw9910_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *norm = priv->norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) const unsigned int hact = 720;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) const unsigned int hdelay = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned int vact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int vdelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!(norm & (V4L2_STD_NTSC | V4L2_STD_PAL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) priv->norm = norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (norm & V4L2_STD_525_60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) vact = 240;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) vdelay = 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = tw9910_mask_set(client, VVBI, 0x10, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) vact = 288;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) vdelay = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = tw9910_mask_set(client, VVBI, 0x10, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = i2c_smbus_write_byte_data(client, CROP_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ((vdelay >> 2) & 0xc0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ((vact >> 4) & 0x30) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ((hdelay >> 6) & 0x0c) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ((hact >> 8) & 0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = i2c_smbus_write_byte_data(client, VDELAY_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) vdelay & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = i2c_smbus_write_byte_data(client, VACTIVE_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) vact & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int tw9910_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (reg->reg > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ret = i2c_smbus_read_byte_data(client, reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * ret = int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * reg->val = __u64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) reg->val = (__u64)ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int tw9910_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (reg->reg > 0xff ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) reg->val > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static void tw9910_set_gpio_value(struct gpio_desc *desc, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) gpiod_set_value(desc, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int tw9910_power_on(struct tw9910_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (priv->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) tw9910_set_gpio_value(priv->pdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * FIXME: The reset signal is connected to a shared GPIO on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * platforms (namely the SuperH Migo-R). Until a framework becomes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * available to handle this cleanly, request the GPIO temporarily
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * to avoid conflicts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) priv->rstb_gpio = gpiod_get_optional(&client->dev, "rstb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (IS_ERR(priv->rstb_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_info(&client->dev, "Unable to get GPIO \"rstb\"");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) tw9910_set_gpio_value(priv->pdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return PTR_ERR(priv->rstb_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (priv->rstb_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) tw9910_set_gpio_value(priv->rstb_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) tw9910_set_gpio_value(priv->rstb_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) gpiod_put(priv->rstb_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int tw9910_power_off(struct tw9910_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) tw9910_set_gpio_value(priv->pdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int tw9910_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return on ? tw9910_power_on(priv) : tw9910_power_off(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int tw9910_set_frame(struct v4l2_subdev *sd, u32 *width, u32 *height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Select suitable norm. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) priv->scale = tw9910_select_norm(priv->norm, *width, *height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!priv->scale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) goto tw9910_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Reset hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) tw9910_reset(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Set bus width. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) val = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (priv->info->buswidth == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) val = LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = tw9910_mask_set(client, OPFORM, LEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) goto tw9910_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Select MPOUT behavior. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) switch (priv->info->mpout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case TW9910_MPO_VLOSS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) val = RTSEL_VLOSS; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case TW9910_MPO_HLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) val = RTSEL_HLOCK; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case TW9910_MPO_SLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) val = RTSEL_SLOCK; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case TW9910_MPO_VLOCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) val = RTSEL_VLOCK; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case TW9910_MPO_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) val = RTSEL_MONO; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) case TW9910_MPO_DET50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) val = RTSEL_DET50; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case TW9910_MPO_FIELD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) val = RTSEL_FIELD; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case TW9910_MPO_RTCO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) val = RTSEL_RTCO; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) goto tw9910_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Set scale. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = tw9910_set_scale(client, priv->scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) goto tw9910_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Set hsync. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = tw9910_set_hsync(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) goto tw9910_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *width = priv->scale->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) *height = priv->scale->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) tw9910_set_fmt_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) tw9910_reset(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) priv->scale = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int tw9910_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (priv->norm & V4L2_STD_NTSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) sel->r.width = 640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) sel->r.height = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) sel->r.width = 768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) sel->r.height = 576;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int tw9910_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!priv->scale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) priv->scale = tw9910_select_norm(priv->norm, 640, 480);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (!priv->scale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mf->width = priv->scale->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mf->height = priv->scale->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mf->field = V4L2_FIELD_INTERLACED_BT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int tw9910_s_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct v4l2_mbus_framefmt *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 width = mf->width, height = mf->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) WARN_ON(mf->field != V4L2_FIELD_ANY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) mf->field != V4L2_FIELD_INTERLACED_BT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* Check color format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (mf->code != MEDIA_BUS_FMT_UYVY8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ret = tw9910_set_frame(sd, &width, &height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mf->width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) mf->height = height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int tw9910_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) const struct tw9910_scale_ctrl *scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (mf->field == V4L2_FIELD_ANY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mf->field = V4L2_FIELD_INTERLACED_BT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) } else if (mf->field != V4L2_FIELD_INTERLACED_BT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_err(&client->dev, "Field type %d invalid\n", mf->field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Select suitable norm. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) scale = tw9910_select_norm(priv->norm, mf->width, mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (!scale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mf->width = scale->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) mf->height = scale->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return tw9910_s_fmt(sd, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) cfg->try_fmt = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int tw9910_video_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) s32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* TW9910 only use 8 or 16 bit bus width. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (priv->info->buswidth != 16 && priv->info->buswidth != 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_err(&client->dev, "bus width error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ret = tw9910_s_power(&priv->subdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * Check and show Product ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * So far only revisions 0 and 1 have been seen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) id = i2c_smbus_read_byte_data(client, ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) priv->revision = GET_REV(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) id = GET_ID(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (id != 0x0b || priv->revision > 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dev_err(&client->dev, "Product ID error %x:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) id, priv->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_info(&client->dev, "tw9910 Product ID %0x:%0x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) id, priv->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) priv->norm = V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) priv->scale = &tw9910_ntsc_scales[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) tw9910_s_power(&priv->subdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static const struct v4l2_subdev_core_ops tw9910_subdev_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .g_register = tw9910_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .s_register = tw9910_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .s_power = tw9910_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int tw9910_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (code->pad || code->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) code->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static int tw9910_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) *norm = V4L2_STD_NTSC | V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static const struct v4l2_subdev_video_ops tw9910_subdev_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .s_std = tw9910_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .g_std = tw9910_g_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .s_stream = tw9910_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .g_tvnorms = tw9910_g_tvnorms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const struct v4l2_subdev_pad_ops tw9910_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .enum_mbus_code = tw9910_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .get_selection = tw9910_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .get_fmt = tw9910_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .set_fmt = tw9910_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static const struct v4l2_subdev_ops tw9910_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .core = &tw9910_subdev_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .video = &tw9910_subdev_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .pad = &tw9910_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * i2c_driver function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int tw9910_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) const struct i2c_device_id *did)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct tw9910_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct tw9910_video_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (!client->dev.platform_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_err(&client->dev, "TW9910: missing platform data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) info = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE_DATA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) priv->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) priv->clk = clk_get(&client->dev, "xti");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (PTR_ERR(priv->clk) == -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) priv->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) } else if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dev_err(&client->dev, "Unable to get xti clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) priv->pdn_gpio = gpiod_get_optional(&client->dev, "pdn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (IS_ERR(priv->pdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev_info(&client->dev, "Unable to get GPIO \"pdn\"");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = PTR_ERR(priv->pdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) goto error_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ret = tw9910_video_probe(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) goto error_gpio_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret = v4l2_async_register_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) goto error_gpio_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) error_gpio_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (priv->pdn_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) gpiod_put(priv->pdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) error_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int tw9910_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct tw9910_priv *priv = to_tw9910(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (priv->pdn_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) gpiod_put(priv->pdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) v4l2_async_unregister_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const struct i2c_device_id tw9910_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) { "tw9910", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) MODULE_DEVICE_TABLE(i2c, tw9910_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static struct i2c_driver tw9910_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .name = "tw9910",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .probe = tw9910_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .remove = tw9910_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .id_table = tw9910_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) module_i2c_driver(tw9910_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) MODULE_DESCRIPTION("V4L2 driver for TW9910 video decoder");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) MODULE_AUTHOR("Kuninori Morimoto");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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