^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2005-2006 Micronas USA Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TW2804_REG_AUTOGAIN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TW2804_REG_HUE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TW2804_REG_SATURATION 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TW2804_REG_CONTRAST 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TW2804_REG_BRIGHTNESS 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TW2804_REG_COLOR_KILLER 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TW2804_REG_GAIN 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TW2804_REG_CHROMA_GAIN 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TW2804_REG_BLUE_BALANCE 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TW2804_REG_RED_BALANCE 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct tw2804 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 channel:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 input:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const u8 global_registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 0x39, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 0x3a, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 0x3b, 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0x3c, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0x3d, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 0x3e, 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 0x3f, 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 0x78, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 0xff, 0xff, /* Terminator (reg 0xff does not exist) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const u8 channel_registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0x01, 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x02, 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 0x03, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x04, 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0x05, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0x06, 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0x07, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 0x08, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 0x09, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 0x0a, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 0x0b, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 0x0c, 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 0x0d, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 0x0e, 0xd2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 0x0f, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0x10, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0x11, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0x12, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x13, 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0x14, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0x15, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0x16, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0x17, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0x18, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x19, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0x1a, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0x1b, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0x1c, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x1d, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0x1e, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x1f, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0x20, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0x21, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0x22, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0x23, 0x91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0x24, 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0x25, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0x26, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 0x27, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0x28, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0x29, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0x2a, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0x2b, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0x2c, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0x2d, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x2e, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0x2f, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0x30, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x31, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0x32, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0x33, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x34, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x35, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0x36, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x37, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0xff, 0xff, /* Terminator (reg 0xff does not exist) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int write_reg(struct i2c_client *client, u8 reg, u8 value, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return i2c_smbus_write_byte_data(client, reg | (channel << 6), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int write_regs(struct i2c_client *client, const u8 *regs, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (i = 0; regs[i] != 0xff; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = i2c_smbus_write_byte_data(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) regs[i] | (channel << 6), regs[i + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int read_reg(struct i2c_client *client, u8 reg, u8 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return i2c_smbus_read_byte_data(client, (reg) | (channel << 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline struct tw2804 *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return container_of(sd, struct tw2804, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline struct tw2804 *to_state_from_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return container_of(ctrl->handler, struct tw2804, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int tw2804_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct tw2804 *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) v4l2_info(sd, "Standard: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) state->norm & V4L2_STD_525_60 ? "60 Hz" : "50 Hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) v4l2_info(sd, "Channel: %d\n", state->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) v4l2_info(sd, "Input: %d\n", state->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return v4l2_ctrl_subdev_log_status(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * These volatile controls are needed because all four channels share
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * these controls. So a change made to them through one channel would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * require another channel to be updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Normally this would have been done in a different way, but since the one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * board that uses this driver sees this single chip as if it was on four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * different i2c adapters (each adapter belonging to a separate instance of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * the same USB driver) there is no reliable method that I have found to let
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * the instances know about each other.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * So implementing these global registers as volatile is the best we can do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int tw2804_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct tw2804 *state = to_state_from_ctrl(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct i2c_client *client = v4l2_get_subdevdata(&state->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ctrl->val = read_reg(client, TW2804_REG_GAIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case V4L2_CID_CHROMA_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ctrl->val = read_reg(client, TW2804_REG_CHROMA_GAIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case V4L2_CID_BLUE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ctrl->val = read_reg(client, TW2804_REG_BLUE_BALANCE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case V4L2_CID_RED_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ctrl->val = read_reg(client, TW2804_REG_RED_BALANCE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int tw2804_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct tw2804 *state = to_state_from_ctrl(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct i2c_client *client = v4l2_get_subdevdata(&state->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) addr = TW2804_REG_AUTOGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) reg = read_reg(client, addr, state->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ctrl->val == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) reg &= ~(1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) reg |= 1 << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return write_reg(client, addr, reg, state->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case V4L2_CID_COLOR_KILLER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) addr = TW2804_REG_COLOR_KILLER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) reg = read_reg(client, addr, state->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) reg = (reg & ~(0x03)) | (ctrl->val == 0 ? 0x02 : 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return write_reg(client, addr, reg, state->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return write_reg(client, TW2804_REG_GAIN, ctrl->val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case V4L2_CID_CHROMA_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return write_reg(client, TW2804_REG_CHROMA_GAIN, ctrl->val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case V4L2_CID_BLUE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return write_reg(client, TW2804_REG_BLUE_BALANCE, ctrl->val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case V4L2_CID_RED_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return write_reg(client, TW2804_REG_RED_BALANCE, ctrl->val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return write_reg(client, TW2804_REG_BRIGHTNESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ctrl->val, state->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return write_reg(client, TW2804_REG_CONTRAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ctrl->val, state->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return write_reg(client, TW2804_REG_SATURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ctrl->val, state->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return write_reg(client, TW2804_REG_HUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ctrl->val, state->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int tw2804_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct tw2804 *dec = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bool is_60hz = norm & V4L2_STD_525_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u8 regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x01, is_60hz ? 0xc4 : 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 0x09, is_60hz ? 0x07 : 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0x0a, is_60hz ? 0xf0 : 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0x0b, is_60hz ? 0x07 : 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0x0c, is_60hz ? 0xf0 : 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0x0d, is_60hz ? 0x40 : 0x4a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0x16, is_60hz ? 0x00 : 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0x17, is_60hz ? 0x00 : 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0x20, is_60hz ? 0x07 : 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0x21, is_60hz ? 0x07 : 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0xff, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) write_regs(client, regs, dec->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dec->norm = norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int tw2804_s_video_routing(struct v4l2_subdev *sd, u32 input, u32 output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct tw2804 *dec = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (config && config - 1 != dec->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (config > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "channel %d is not between 1 and 4!\n", config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dec->channel = config - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_dbg(&client->dev, "initializing TW2804 channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dec->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (dec->channel == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) write_regs(client, global_registers, 0) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "error initializing TW2804 global registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (write_regs(client, channel_registers, dec->channel) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "error initializing TW2804 channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dec->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (input > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (input == dec->input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) reg = read_reg(client, 0x22, dec->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (reg >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (input == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) reg &= ~(1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) reg |= 1 << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) reg = write_reg(client, 0x22, reg, dec->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (reg >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dec->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct v4l2_ctrl_ops tw2804_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .g_volatile_ctrl = tw2804_g_volatile_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .s_ctrl = tw2804_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct v4l2_subdev_video_ops tw2804_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .s_std = tw2804_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .s_routing = tw2804_s_video_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct v4l2_subdev_core_ops tw2804_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .log_status = tw2804_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct v4l2_subdev_ops tw2804_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .core = &tw2804_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .video = &tw2804_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int tw2804_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct tw2804 *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) v4l2_i2c_subdev_init(sd, client, &tw2804_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) state->channel = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) state->norm = V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) v4l2_ctrl_handler_init(&state->hdl, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) V4L2_CID_CONTRAST, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) V4L2_CID_SATURATION, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) V4L2_CID_HUE, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) V4L2_CID_COLOR_KILLER, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) V4L2_CID_AUTOGAIN, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ctrl = v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) V4L2_CID_GAIN, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ctrl = v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) V4L2_CID_CHROMA_GAIN, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ctrl = v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) V4L2_CID_BLUE_BALANCE, 0, 255, 1, 122);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ctrl = v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) V4L2_CID_RED_BALANCE, 0, 255, 1, 122);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sd->ctrl_handler = &state->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) err = state->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) v4l_info(client, "chip found @ 0x%02x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int tw2804_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct tw2804 *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct i2c_device_id tw2804_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { "tw2804", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MODULE_DEVICE_TABLE(i2c, tw2804_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static struct i2c_driver tw2804_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .name = "tw2804",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .probe = tw2804_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .remove = tw2804_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .id_table = tw2804_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) module_i2c_driver(tw2804_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MODULE_DESCRIPTION("TW2804/TW2802 V4L2 i2c driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MODULE_AUTHOR("Micronas USA Inc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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