^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Digitizer with Horizontal PLL registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Texas Instruments Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This code is partially based upon the TVP5150 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * written by Mauro Carvalho Chehab <mchehab@kernel.org>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Muralidharan Karicheri and Snehaprabha Narnakaje (TI).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/i2c/tvp7002.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "tvp7002_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* I2C retry attempts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2C_RETRY_COUNT (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* End of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TVP7002_EOR 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Read write definition for registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TVP7002_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TVP7002_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TVP7002_RESERVED 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Interlaced vs progressive mask and shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TVP7002_IP_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TVP7002_INPR_MASK (0x01 << TVP7002_IP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Shift for CPL and LPF registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TVP7002_CL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TVP7002_CL_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Debug functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static bool debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) module_param(debug, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_PARM_DESC(debug, "Debug level (0-2)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Structure for register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct i2c_reg_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Register default values (according to tvp7002 datasheet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * In the case of read-only registers, the value (0xff) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * never written. R/W functionality is controlled by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * writable bit in the register struct definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct i2c_reg_value tvp7002_init_default[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { TVP7002_CHIP_REV, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { 0x29, 0x08, TVP7002_RESERVED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* PWR_CTL is controlled only by the probe and reset functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0x32, 0x18, TVP7002_RESERVED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0x33, 0x60, TVP7002_RESERVED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { TVP7002_HSYNC_W, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { TVP7002_VSYNC_W, 0xff, TVP7002_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 0x3e, 0x60, TVP7002_RESERVED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* This signals end of register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { TVP7002_EOR, 0xff, TVP7002_RESERVED }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Register parameters for 480P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct i2c_reg_value tvp7002_parms_480P[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { TVP7002_EOR, 0xff, TVP7002_RESERVED }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Register parameters for 576P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct i2c_reg_value tvp7002_parms_576P[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { TVP7002_EOR, 0xff, TVP7002_RESERVED }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Register parameters for 1080I60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct i2c_reg_value tvp7002_parms_1080I60[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { TVP7002_EOR, 0xff, TVP7002_RESERVED }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Register parameters for 1080P60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct i2c_reg_value tvp7002_parms_1080P60[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { TVP7002_EOR, 0xff, TVP7002_RESERVED }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Register parameters for 1080I50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct i2c_reg_value tvp7002_parms_1080I50[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { TVP7002_EOR, 0xff, TVP7002_RESERVED }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Register parameters for 720P60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const struct i2c_reg_value tvp7002_parms_720P60[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { TVP7002_EOR, 0xff, TVP7002_RESERVED }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Register parameters for 720P50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct i2c_reg_value tvp7002_parms_720P50[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { TVP7002_EOR, 0xff, TVP7002_RESERVED }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Timings definition for handling device operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct tvp7002_timings_definition {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) const struct i2c_reg_value *p_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) enum v4l2_colorspace color_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) enum v4l2_field scanmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u16 progressive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u16 lines_per_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u16 cpl_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u16 cpl_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Struct list for digital video timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct tvp7002_timings_definition tvp7002_timings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) V4L2_DV_BT_CEA_1280X720P60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) tvp7002_parms_720P60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) V4L2_COLORSPACE_REC709,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0x2EE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) V4L2_DV_BT_CEA_1920X1080I60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) tvp7002_parms_1080I60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) V4L2_COLORSPACE_REC709,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) V4L2_FIELD_INTERLACED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 181,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) V4L2_DV_BT_CEA_1920X1080I50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tvp7002_parms_1080I50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) V4L2_COLORSPACE_REC709,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) V4L2_FIELD_INTERLACED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 217,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) V4L2_DV_BT_CEA_1280X720P50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) tvp7002_parms_720P50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) V4L2_COLORSPACE_REC709,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x2EE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 163,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) V4L2_DV_BT_CEA_1920X1080P60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) tvp7002_parms_1080P60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) V4L2_COLORSPACE_REC709,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0x465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) V4L2_DV_BT_CEA_720X480P59_94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) tvp7002_parms_480P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) V4L2_COLORSPACE_SMPTE170M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x20D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) V4L2_DV_BT_CEA_720X576P50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) tvp7002_parms_576P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) V4L2_COLORSPACE_SMPTE170M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x271,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Device definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct tvp7002 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) const struct tvp7002_config *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) const struct tvp7002_timings_definition *current_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * to_tvp7002 - Obtain device handler TVP7002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * @sd: ptr to v4l2_subdev struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * Returns device handler tvp7002.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return container_of(sd, struct tvp7002, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return &container_of(ctrl->handler, struct tvp7002, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * tvp7002_read - Read a value from a register in an TVP7002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @sd: ptr to v4l2_subdev struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @addr: TVP7002 register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @dst: pointer to 8-bit destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Returns value read if successful, or non-zero (-1) otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct i2c_client *c = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) error = i2c_smbus_read_byte_data(c, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (error >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) *dst = (u8)error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) msleep_interruptible(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) v4l2_err(sd, "TVP7002 read error %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * tvp7002_read_err() - Read a register value with error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * @sd: pointer to standard V4L2 sub-device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * @reg: destination register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * @val: value to be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * @err: pointer to error value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * Read a value in a register and save error value in pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Also update the register table if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u8 *dst, int *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!*err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) *err = tvp7002_read(sd, reg, dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * tvp7002_write() - Write a value to a register in TVP7002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * @sd: ptr to v4l2_subdev struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * @addr: TVP7002 register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * @value: value to be written to the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * Write a value to a register in an TVP7002 decoder device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * Returns zero if successful, or non-zero otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct i2c_client *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) c = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) error = i2c_smbus_write_byte_data(c, addr, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (error >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) v4l2_warn(sd, "Write: retry ... %d\n", retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) msleep_interruptible(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) v4l2_err(sd, "TVP7002 write error %d\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * tvp7002_write_err() - Write a register value with error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * @sd: pointer to standard V4L2 sub-device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * @reg: destination register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * @val: value to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * @err: pointer to error value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Write a value in a register and save error value in pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * Also update the register table if successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u8 val, int *err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!*err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) *err = tvp7002_write(sd, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * tvp7002_write_inittab() - Write initialization values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * @sd: ptr to v4l2_subdev struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * @regs: ptr to i2c_reg_value struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * Write initialization values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * Returns zero or -EINVAL if read operation fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int tvp7002_write_inittab(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) const struct i2c_reg_value *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Initialize the first (defined) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) while (TVP7002_EOR != regs->reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (TVP7002_WRITE == regs->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) tvp7002_write_err(sd, regs->reg, regs->value, &error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int tvp7002_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct v4l2_dv_timings *dv_timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct tvp7002 *device = to_tvp7002(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) const struct v4l2_bt_timings *bt = &dv_timings->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (dv_timings->type != V4L2_DV_BT_656_1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) for (i = 0; i < NUM_TIMINGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!memcmp(bt, t, &bt->standards - &bt->width)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) device->current_timings = &tvp7002_timings[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int tvp7002_g_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct v4l2_dv_timings *dv_timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct tvp7002 *device = to_tvp7002(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) *dv_timings = device->current_timings->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * tvp7002_s_ctrl() - Set a control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * @ctrl: ptr to v4l2_ctrl struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * Set a control in TVP7002 decoder device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * Returns zero when successful or -EINVAL if register access fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case V4L2_CID_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * tvp7002_query_dv() - query DV timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * @sd: pointer to standard V4L2 sub-device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * @index: index into the tvp7002_timings array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * Returns the current DV timings detected by TVP7002. If no active input is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * detected, returns -EINVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) const struct tvp7002_timings_definition *timings = tvp7002_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u8 progressive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u32 lpfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u32 cpln;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u8 lpf_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u8 lpf_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u8 cpl_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u8 cpl_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Return invalid index if no active input is detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) *index = NUM_TIMINGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Read standards from device registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Get lines per frame, clocks per line and interlaced/progresive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Do checking of video modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (lpfr == timings->lines_per_frame &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) progressive == timings->progressive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (timings->cpl_min == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (cpln >= timings->cpl_min && cpln <= timings->cpl_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (*index == NUM_TIMINGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) lpfr, cpln);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* Update lines per frame and clocks per line info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int tvp7002_query_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int err = tvp7002_query_dv(sd, &index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *timings = tvp7002_timings[index].timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * tvp7002_g_register() - Get the value of a register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * @sd: ptr to v4l2_subdev struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * @reg: ptr to v4l2_dbg_register struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * Get the value of a TVP7002 decoder device register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Returns zero when successful, -EINVAL if register read fails or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * access to I2C client fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int tvp7002_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = tvp7002_read(sd, reg->reg & 0xff, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) reg->val = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * tvp7002_s_register() - set a control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * @sd: ptr to v4l2_subdev struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * @reg: ptr to v4l2_dbg_register struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * Get the value of a TVP7002 decoder device register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * Returns zero when successful, -EINVAL if register read fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int tvp7002_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * @sd: pointer to standard V4L2 sub-device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * @enable: streaming enable or disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * Sets streaming to enable or disable, if possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct tvp7002 *device = to_tvp7002(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (device->streaming == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* low impedance: on, high impedance: off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) error = tvp7002_write(sd, TVP7002_MISC_CTL_2, enable ? 0x00 : 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) v4l2_dbg(1, debug, sd, "Fail to set streaming\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) device->streaming = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * tvp7002_log_status() - Print information about register settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * @sd: ptr to v4l2_subdev struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * Log register values of a TVP7002 decoder device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * Returns zero or -EINVAL if read operation fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int tvp7002_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct tvp7002 *device = to_tvp7002(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) const struct v4l2_bt_timings *bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int detected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* Find my current timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) tvp7002_query_dv(sd, &detected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) bt = &device->current_timings->timings.bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (detected == NUM_TIMINGS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) v4l2_info(sd, "Detected DV Timings: None\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) bt = &tvp7002_timings[detected].timings.bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) v4l2_info(sd, "Detected DV Timings: %ux%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) bt->width, bt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) v4l2_info(sd, "Streaming enabled: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) device->streaming ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Print the current value of the gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) v4l2_ctrl_handler_log_status(&device->hdl, sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct v4l2_enum_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (timings->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Check requested format index is within range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (timings->index >= NUM_TIMINGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) timings->timings = tvp7002_timings[timings->index].timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .s_ctrl = tvp7002_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * tvp7002_enum_mbus_code() - Enum supported digital video format on pad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * @sd: pointer to standard V4L2 sub-device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * @cfg: pad configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * @code: pointer to subdev enum mbus code struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * Enumerate supported digital video formats for pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) tvp7002_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Check requested format index is within range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) code->code = MEDIA_BUS_FMT_YUYV10_1X20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * tvp7002_get_pad_format() - get video format on pad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * @sd: pointer to standard V4L2 sub-device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * @cfg: pad configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * @fmt: pointer to subdev format struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * get video format for pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) tvp7002_get_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct tvp7002 *tvp7002 = to_tvp7002(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) fmt->format.code = MEDIA_BUS_FMT_YUYV10_1X20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) fmt->format.width = tvp7002->current_timings->timings.bt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) fmt->format.height = tvp7002->current_timings->timings.bt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) fmt->format.field = tvp7002->current_timings->scanmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) fmt->format.colorspace = tvp7002->current_timings->color_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * tvp7002_set_pad_format() - set video format on pad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * @sd: pointer to standard V4L2 sub-device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * @cfg: pad configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * @fmt: pointer to subdev format struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * set video format for pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) tvp7002_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return tvp7002_get_pad_format(sd, cfg, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* V4L2 core operation handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static const struct v4l2_subdev_core_ops tvp7002_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .log_status = tvp7002_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .g_register = tvp7002_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .s_register = tvp7002_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Specific video subsystem operation handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const struct v4l2_subdev_video_ops tvp7002_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .g_dv_timings = tvp7002_g_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .s_dv_timings = tvp7002_s_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .query_dv_timings = tvp7002_query_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .s_stream = tvp7002_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* media pad related operation handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const struct v4l2_subdev_pad_ops tvp7002_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .enum_mbus_code = tvp7002_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .get_fmt = tvp7002_get_pad_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .set_fmt = tvp7002_set_pad_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .enum_dv_timings = tvp7002_enum_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* V4L2 top level operation handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const struct v4l2_subdev_ops tvp7002_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .core = &tvp7002_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .video = &tvp7002_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .pad = &tvp7002_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static struct tvp7002_config *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) tvp7002_get_pdata(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct tvp7002_config *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) flags = bus_cfg.bus.parallel.flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) pdata->hs_polarity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) pdata->vs_polarity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pdata->clk_polarity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (flags & V4L2_MBUS_FIELD_EVEN_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pdata->fid_polarity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (flags & V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) pdata->sog_polarity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) of_node_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * tvp7002_probe - Probe a TVP7002 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * @c: ptr to i2c_client struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * @id: ptr to i2c_device_id struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * Initialize the TVP7002 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * Returns zero when successful, -EINVAL if register read fails or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * -EIO if i2c access is not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int tvp7002_probe(struct i2c_client *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct tvp7002_config *pdata = tvp7002_get_pdata(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct tvp7002 *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) int polarity_a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) int polarity_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u8 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_err(&c->dev, "No platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (!i2c_check_functionality(c->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (!device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) sd = &device->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) device->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) device->current_timings = tvp7002_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* Tell v4l2 the device is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) v4l2_i2c_subdev_init(sd, c, &tvp7002_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) c->addr, c->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* Get revision number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) v4l2_info(sd, "Rev. %02x detected.\n", revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (revision != 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) v4l2_info(sd, "Unknown revision detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Initializes TVP7002 to its default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) error = tvp7002_write_inittab(sd, tvp7002_init_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Set polarity information after registers have been set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) polarity_a = 0x20 | device->pdata->hs_polarity << 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) | device->pdata->vs_polarity << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) polarity_b = 0x01 | device->pdata->fid_polarity << 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) | device->pdata->sog_polarity << 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) | device->pdata->clk_polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* Set registers according to default video mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) timings = device->current_timings->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) error = tvp7002_s_dv_timings(sd, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) device->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) device->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) device->sd.entity.function = MEDIA_ENT_F_ATV_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) error = media_entity_pads_init(&device->sd.entity, 1, &device->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) v4l2_ctrl_handler_init(&device->hdl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) V4L2_CID_GAIN, 0, 255, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) sd->ctrl_handler = &device->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (device->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) error = device->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) v4l2_ctrl_handler_setup(&device->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) error = v4l2_async_register_subdev(&device->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) v4l2_ctrl_handler_free(&device->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) media_entity_cleanup(&device->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * tvp7002_remove - Remove TVP7002 device support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * @c: ptr to i2c_client struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * Reset the TVP7002 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * Returns zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int tvp7002_remove(struct i2c_client *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct v4l2_subdev *sd = i2c_get_clientdata(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct tvp7002 *device = to_tvp7002(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) "on address 0x%x\n", c->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) v4l2_async_unregister_subdev(&device->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) media_entity_cleanup(&device->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) v4l2_ctrl_handler_free(&device->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* I2C Device ID table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static const struct i2c_device_id tvp7002_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) { "tvp7002", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) MODULE_DEVICE_TABLE(i2c, tvp7002_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static const struct of_device_id tvp7002_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) { .compatible = "ti,tvp7002", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) MODULE_DEVICE_TABLE(of, tvp7002_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* I2C driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static struct i2c_driver tvp7002_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .of_match_table = of_match_ptr(tvp7002_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .name = TVP7002_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .probe_new = tvp7002_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .remove = tvp7002_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .id_table = tvp7002_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) module_i2c_driver(tvp7002_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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