Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * tvp5150 - Texas Instruments TVP5150A/AM1 video decoder registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2005,2006 Mauro Carvalho Chehab <mchehab@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define TVP5150_VD_IN_SRC_SEL_1      0x00 /* Video input source selection #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define TVP5150_ANAL_CHL_CTL         0x01 /* Analog channel controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define TVP5150_OP_MODE_CTL          0x02 /* Operation mode controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define TVP5150_MISC_CTL             0x03 /* Miscellaneous controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define TVP5150_MISC_CTL_VBLK_GPCL	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define TVP5150_MISC_CTL_GPCL		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define TVP5150_MISC_CTL_INTREQ_OE	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define TVP5150_MISC_CTL_HVLK		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define TVP5150_MISC_CTL_YCBCR_OE	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define TVP5150_MISC_CTL_SYNC_OE	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TVP5150_MISC_CTL_VBLANK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TVP5150_MISC_CTL_CLOCK_OE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TVP5150_AUTOSW_MSK           0x04 /* Autoswitch mask: TVP5150A / TVP5150AM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* Reserved 05h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TVP5150_COLOR_KIL_THSH_CTL   0x06 /* Color killer threshold control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TVP5150_LUMA_PROC_CTL_1      0x07 /* Luminance processing control #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TVP5150_LUMA_PROC_CTL_2      0x08 /* Luminance processing control #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TVP5150_BRIGHT_CTL           0x09 /* Brightness control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TVP5150_SATURATION_CTL       0x0a /* Color saturation control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TVP5150_HUE_CTL              0x0b /* Hue control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TVP5150_CONTRAST_CTL         0x0c /* Contrast control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TVP5150_DATA_RATE_SEL        0x0d /* Outputs and data rates select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TVP5150_LUMA_PROC_CTL_3      0x0e /* Luminance processing control #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TVP5150_CONF_SHARED_PIN      0x0f /* Configuration shared pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* Reserved 10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TVP5150_ACT_VD_CROP_ST_MSB   0x11 /* Active video cropping start MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TVP5150_ACT_VD_CROP_ST_LSB   0x12 /* Active video cropping start LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TVP5150_ACT_VD_CROP_STP_MSB  0x13 /* Active video cropping stop MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TVP5150_ACT_VD_CROP_STP_LSB  0x14 /* Active video cropping stop LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TVP5150_GENLOCK              0x15 /* Genlock/RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TVP5150_HORIZ_SYNC_START     0x16 /* Horizontal sync start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Reserved 17h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TVP5150_VERT_BLANKING_START 0x18 /* Vertical blanking start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TVP5150_VERT_BLANKING_STOP  0x19 /* Vertical blanking stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TVP5150_CHROMA_PROC_CTL_1   0x1a /* Chrominance processing control #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TVP5150_CHROMA_PROC_CTL_2   0x1b /* Chrominance processing control #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TVP5150_INT_RESET_REG_B     0x1c /* Interrupt reset register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TVP5150_INT_ENABLE_REG_B    0x1d /* Interrupt enable register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TVP5150_INTT_CONFIG_REG_B   0x1e /* Interrupt configuration register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* Reserved 1Fh-27h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define VIDEO_STD_MASK			 (0x07 >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TVP5150_VIDEO_STD                0x28 /* Video standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define VIDEO_STD_AUTO_SWITCH_BIT	 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define VIDEO_STD_NTSC_MJ_BIT		 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define VIDEO_STD_PAL_BDGHIN_BIT	 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define VIDEO_STD_PAL_M_BIT		 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define VIDEO_STD_PAL_COMBINATION_N_BIT	 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define VIDEO_STD_NTSC_4_43_BIT		 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define VIDEO_STD_SECAM_BIT		 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define VIDEO_STD_NTSC_MJ_BIT_AS                 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define VIDEO_STD_PAL_BDGHIN_BIT_AS              0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define VIDEO_STD_PAL_M_BIT_AS			 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define VIDEO_STD_PAL_COMBINATION_N_BIT_AS	 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define VIDEO_STD_NTSC_4_43_BIT_AS		 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define VIDEO_STD_SECAM_BIT_AS			 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* Reserved 29h-2bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define TVP5150_CB_GAIN_FACT        0x2c /* Cb gain factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define TVP5150_CR_GAIN_FACTOR      0x2d /* Cr gain factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TVP5150_MACROVISION_ON_CTR  0x2e /* Macrovision on counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define TVP5150_MACROVISION_OFF_CTR 0x2f /* Macrovision off counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define TVP5150_REV_SELECT          0x30 /* revision select (TVP5150AM1 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* Reserved	31h-7Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define TVP5150_MSB_DEV_ID          0x80 /* MSB of device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define TVP5150_LSB_DEV_ID          0x81 /* LSB of device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TVP5150_ROM_MAJOR_VER       0x82 /* ROM major version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define TVP5150_ROM_MINOR_VER       0x83 /* ROM minor version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TVP5150_VERT_LN_COUNT_MSB   0x84 /* Vertical line count MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define TVP5150_VERT_LN_COUNT_LSB   0x85 /* Vertical line count LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TVP5150_INT_STATUS_REG_B    0x86 /* Interrupt status register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TVP5150_INT_ACTIVE_REG_B    0x87 /* Interrupt active register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TVP5150_STATUS_REG_1        0x88 /* Status register #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TVP5150_STATUS_REG_2        0x89 /* Status register #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TVP5150_STATUS_REG_3        0x8a /* Status register #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define TVP5150_STATUS_REG_4        0x8b /* Status register #4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TVP5150_STATUS_REG_5        0x8c /* Status register #5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /* Reserved	8Dh-8Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  /* Closed caption data registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TVP5150_CC_DATA_INI         0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TVP5150_CC_DATA_END         0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  /* WSS data registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TVP5150_WSS_DATA_INI        0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TVP5150_WSS_DATA_END        0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* VPS data registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TVP5150_VPS_DATA_INI        0x9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TVP5150_VPS_DATA_END        0xa6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* VITC data registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TVP5150_VITC_DATA_INI       0xa7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TVP5150_VITC_DATA_END       0xaf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TVP5150_VBI_FIFO_READ_DATA  0xb0 /* VBI FIFO read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Teletext filter 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TVP5150_TELETEXT_FIL1_INI  0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TVP5150_TELETEXT_FIL1_END  0xb5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Teletext filter 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TVP5150_TELETEXT_FIL2_INI  0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TVP5150_TELETEXT_FIL2_END  0xba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TVP5150_TELETEXT_FIL_ENA    0xbb /* Teletext filter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Reserved	BCh-BFh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TVP5150_INT_STATUS_REG_A    0xc0 /* Interrupt status register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define   TVP5150_INT_A_LOCK_STATUS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define   TVP5150_INT_A_LOCK        BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TVP5150_INT_ENABLE_REG_A    0xc1 /* Interrupt enable register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TVP5150_INT_CONF            0xc2 /* Interrupt configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define   TVP5150_VDPOE             BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TVP5150_VDP_CONF_RAM_DATA   0xc3 /* VDP configuration RAM data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TVP5150_CONF_RAM_ADDR_LOW   0xc4 /* Configuration RAM address low byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TVP5150_CONF_RAM_ADDR_HIGH  0xc5 /* Configuration RAM address high byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TVP5150_VDP_STATUS_REG      0xc6 /* VDP status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TVP5150_FIFO_WORD_COUNT     0xc7 /* FIFO word count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TVP5150_FIFO_INT_THRESHOLD  0xc8 /* FIFO interrupt threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TVP5150_FIFO_RESET          0xc9 /* FIFO reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TVP5150_LINE_NUMBER_INT     0xca /* Line number interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TVP5150_PIX_ALIGN_REG_LOW   0xcb /* Pixel alignment register low byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TVP5150_PIX_ALIGN_REG_HIGH  0xcc /* Pixel alignment register high byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TVP5150_FIFO_OUT_CTRL       0xcd /* FIFO output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Reserved	CEh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TVP5150_FULL_FIELD_ENA      0xcf /* Full field enable 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Line mode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TVP5150_LINE_MODE_INI       0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TVP5150_LINE_MODE_END       0xfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TVP5150_FULL_FIELD_MODE_REG 0xfc /* Full field mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Reserved	FDh-FFh */