^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // tvp5150 - Texas Instruments TVP5150A/AM1 and TVP5151 video decoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2005,2006 Mauro Carvalho Chehab <mchehab@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <dt-bindings/media/tvp5150.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-mc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-rect.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "tvp5150_reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TVP5150_H_MAX 720U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TVP5150_V_MAX_525_60 480U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TVP5150_V_MAX_OTHERS 576U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TVP5150_MAX_CROP_LEFT 511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TVP5150_MAX_CROP_TOP 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TVP5150_CROP_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TVP5150_MBUS_FMT MEDIA_BUS_FMT_UYVY8_2X8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TVP5150_FIELD V4L2_FIELD_ALTERNATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TVP5150_COLORSPACE V4L2_COLORSPACE_SMPTE170M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TVP5150_STD_MASK (V4L2_STD_NTSC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) V4L2_STD_NTSC_443 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) V4L2_STD_PAL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) V4L2_STD_PAL_M | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) V4L2_STD_PAL_N | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) V4L2_STD_PAL_Nc | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) V4L2_STD_SECAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TVP5150_MAX_CONNECTORS 3 /* Check dt-bindings for more information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_DESCRIPTION("Texas Instruments TVP5150A/TVP5150AM1/TVP5151 video decoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_AUTHOR("Mauro Carvalho Chehab");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_PARM_DESC(debug, "Debug level (0-2)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define dprintk0(__dev, __arg...) dev_dbg_lvl(__dev, 0, 0, __arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum tvp5150_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) TVP5150_PAD_AIP1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) TVP5150_PAD_AIP1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) TVP5150_PAD_VID_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) TVP5150_NUM_PADS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct tvp5150_connector {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct v4l2_fwnode_connector base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct media_entity ent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct tvp5150 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct media_pad pads[TVP5150_NUM_PADS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct tvp5150_connector connectors[TVP5150_MAX_CONNECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tvp5150_connector *cur_connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int connectors_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct v4l2_rect rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) v4l2_std_id norm; /* Current set standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) v4l2_std_id detected_norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bool lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u16 dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 rom_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) enum v4l2_mbus_type mbus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline struct tvp5150 *to_tvp5150(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return container_of(sd, struct tvp5150, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return &container_of(ctrl->handler, struct tvp5150, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int tvp5150_read(struct v4l2_subdev *sd, unsigned char addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = regmap_read(decoder->regmap, addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void dump_reg_range(struct v4l2_subdev *sd, char *s, u8 init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const u8 end, int max_line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 buf[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int i = 0, j, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (max_line > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dprintk0(sd->dev, "too much data to dump\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) for (i = init; i < end; i += max_line) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) len = (end - i > max_line) ? max_line : end - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (j = 0; j < len; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) buf[j] = tvp5150_read(sd, i + j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dprintk0(sd->dev, "%s reg %02x = %*ph\n", s, i, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int tvp5150_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dprintk0(sd->dev, "tvp5150: Video input source selection #1 = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tvp5150_read(sd, TVP5150_VD_IN_SRC_SEL_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dprintk0(sd->dev, "tvp5150: Analog channel controls = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tvp5150_read(sd, TVP5150_ANAL_CHL_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dprintk0(sd->dev, "tvp5150: Operation mode controls = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) tvp5150_read(sd, TVP5150_OP_MODE_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dprintk0(sd->dev, "tvp5150: Miscellaneous controls = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tvp5150_read(sd, TVP5150_MISC_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dprintk0(sd->dev, "tvp5150: Autoswitch mask= 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tvp5150_read(sd, TVP5150_AUTOSW_MSK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dprintk0(sd->dev, "tvp5150: Color killer threshold control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tvp5150_read(sd, TVP5150_COLOR_KIL_THSH_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dprintk0(sd->dev, "tvp5150: Luminance processing controls #1 #2 and #3 = %02x %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dprintk0(sd->dev, "tvp5150: Brightness control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tvp5150_read(sd, TVP5150_BRIGHT_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dprintk0(sd->dev, "tvp5150: Color saturation control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tvp5150_read(sd, TVP5150_SATURATION_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dprintk0(sd->dev, "tvp5150: Hue control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tvp5150_read(sd, TVP5150_HUE_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dprintk0(sd->dev, "tvp5150: Contrast control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tvp5150_read(sd, TVP5150_CONTRAST_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dprintk0(sd->dev, "tvp5150: Outputs and data rates select = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tvp5150_read(sd, TVP5150_DATA_RATE_SEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dprintk0(sd->dev, "tvp5150: Configuration shared pins = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) tvp5150_read(sd, TVP5150_CONF_SHARED_PIN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dprintk0(sd->dev, "tvp5150: Active video cropping start = 0x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_LSB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dprintk0(sd->dev, "tvp5150: Active video cropping stop = 0x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_LSB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dprintk0(sd->dev, "tvp5150: Genlock/RTC = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tvp5150_read(sd, TVP5150_GENLOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dprintk0(sd->dev, "tvp5150: Horizontal sync start = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tvp5150_read(sd, TVP5150_HORIZ_SYNC_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dprintk0(sd->dev, "tvp5150: Vertical blanking start = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) tvp5150_read(sd, TVP5150_VERT_BLANKING_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dprintk0(sd->dev, "tvp5150: Vertical blanking stop = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) tvp5150_read(sd, TVP5150_VERT_BLANKING_STOP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dprintk0(sd->dev, "tvp5150: Chrominance processing control #1 and #2 = %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dprintk0(sd->dev, "tvp5150: Interrupt reset register B = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) tvp5150_read(sd, TVP5150_INT_RESET_REG_B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dprintk0(sd->dev, "tvp5150: Interrupt enable register B = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) tvp5150_read(sd, TVP5150_INT_ENABLE_REG_B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dprintk0(sd->dev, "tvp5150: Interrupt configuration register B = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tvp5150_read(sd, TVP5150_INTT_CONFIG_REG_B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dprintk0(sd->dev, "tvp5150: Video standard = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) tvp5150_read(sd, TVP5150_VIDEO_STD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dprintk0(sd->dev, "tvp5150: Chroma gain factor: Cb=0x%02x Cr=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) tvp5150_read(sd, TVP5150_CB_GAIN_FACT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tvp5150_read(sd, TVP5150_CR_GAIN_FACTOR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dprintk0(sd->dev, "tvp5150: Macrovision on counter = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) tvp5150_read(sd, TVP5150_MACROVISION_ON_CTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dprintk0(sd->dev, "tvp5150: Macrovision off counter = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tvp5150_read(sd, TVP5150_MACROVISION_OFF_CTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dprintk0(sd->dev, "tvp5150: ITU-R BT.656.%d timing(TVP5150AM1 only)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) (tvp5150_read(sd, TVP5150_REV_SELECT) & 1) ? 3 : 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dprintk0(sd->dev, "tvp5150: Device ID = %02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) tvp5150_read(sd, TVP5150_MSB_DEV_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) tvp5150_read(sd, TVP5150_LSB_DEV_ID));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dprintk0(sd->dev, "tvp5150: ROM version = (hex) %02x.%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tvp5150_read(sd, TVP5150_ROM_MAJOR_VER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) tvp5150_read(sd, TVP5150_ROM_MINOR_VER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dprintk0(sd->dev, "tvp5150: Vertical line count = 0x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) tvp5150_read(sd, TVP5150_VERT_LN_COUNT_MSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) tvp5150_read(sd, TVP5150_VERT_LN_COUNT_LSB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dprintk0(sd->dev, "tvp5150: Interrupt status register B = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tvp5150_read(sd, TVP5150_INT_STATUS_REG_B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dprintk0(sd->dev, "tvp5150: Interrupt active register B = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tvp5150_read(sd, TVP5150_INT_ACTIVE_REG_B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dprintk0(sd->dev, "tvp5150: Status regs #1 to #5 = %02x %02x %02x %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tvp5150_read(sd, TVP5150_STATUS_REG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tvp5150_read(sd, TVP5150_STATUS_REG_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) tvp5150_read(sd, TVP5150_STATUS_REG_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tvp5150_read(sd, TVP5150_STATUS_REG_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tvp5150_read(sd, TVP5150_STATUS_REG_5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dump_reg_range(sd, "Teletext filter 1", TVP5150_TELETEXT_FIL1_INI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) TVP5150_TELETEXT_FIL1_END, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dump_reg_range(sd, "Teletext filter 2", TVP5150_TELETEXT_FIL2_INI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) TVP5150_TELETEXT_FIL2_END, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dprintk0(sd->dev, "tvp5150: Teletext filter enable = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) tvp5150_read(sd, TVP5150_TELETEXT_FIL_ENA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dprintk0(sd->dev, "tvp5150: Interrupt status register A = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tvp5150_read(sd, TVP5150_INT_STATUS_REG_A));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dprintk0(sd->dev, "tvp5150: Interrupt enable register A = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tvp5150_read(sd, TVP5150_INT_ENABLE_REG_A));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dprintk0(sd->dev, "tvp5150: Interrupt configuration = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tvp5150_read(sd, TVP5150_INT_CONF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dprintk0(sd->dev, "tvp5150: VDP status register = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tvp5150_read(sd, TVP5150_VDP_STATUS_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dprintk0(sd->dev, "tvp5150: FIFO word count = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tvp5150_read(sd, TVP5150_FIFO_WORD_COUNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dprintk0(sd->dev, "tvp5150: FIFO interrupt threshold = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tvp5150_read(sd, TVP5150_FIFO_INT_THRESHOLD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dprintk0(sd->dev, "tvp5150: FIFO reset = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) tvp5150_read(sd, TVP5150_FIFO_RESET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dprintk0(sd->dev, "tvp5150: Line number interrupt = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tvp5150_read(sd, TVP5150_LINE_NUMBER_INT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dprintk0(sd->dev, "tvp5150: Pixel alignment register = 0x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_LOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dprintk0(sd->dev, "tvp5150: FIFO output control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) tvp5150_read(sd, TVP5150_FIFO_OUT_CTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dprintk0(sd->dev, "tvp5150: Full field enable = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tvp5150_read(sd, TVP5150_FULL_FIELD_ENA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dprintk0(sd->dev, "tvp5150: Full field mode register = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) tvp5150_read(sd, TVP5150_FULL_FIELD_MODE_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dump_reg_range(sd, "CC data", TVP5150_CC_DATA_INI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) TVP5150_CC_DATA_END, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dump_reg_range(sd, "WSS data", TVP5150_WSS_DATA_INI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) TVP5150_WSS_DATA_END, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dump_reg_range(sd, "VPS data", TVP5150_VPS_DATA_INI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) TVP5150_VPS_DATA_END, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dump_reg_range(sd, "VITC data", TVP5150_VITC_DATA_INI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) TVP5150_VITC_DATA_END, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dump_reg_range(sd, "Line mode", TVP5150_LINE_MODE_INI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) TVP5150_LINE_MODE_END, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) Basic functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void tvp5150_selmux(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int opmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int input = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Only tvp5150am1 and tvp5151 have signal generator support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if ((decoder->dev_id == 0x5150 && decoder->rom_ver == 0x0400) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (decoder->dev_id == 0x5151 && decoder->rom_ver == 0x0100)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!decoder->enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) input = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) switch (decoder->input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case TVP5150_COMPOSITE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) input |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case TVP5150_COMPOSITE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case TVP5150_SVIDEO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) input |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_dbg_lvl(sd->dev, 1, debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "Selecting video route: route input=%s, output=%s => tvp5150 input=0x%02x, opmode=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) decoder->input == 0 ? "aip1a" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) decoder->input == 2 ? "aip1b" : "svideo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) decoder->output == 0 ? "normal" : "black-frame-gen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) input, opmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) regmap_write(decoder->regmap, TVP5150_OP_MODE_CTL, opmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) regmap_write(decoder->regmap, TVP5150_VD_IN_SRC_SEL_1, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Setup the FID/GLCO/VLK/HVLK and INTREQ/GPCL/VBLK output signals. For
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * S-Video we output the vertical lock (VLK) signal on FID/GLCO/VLK/HVLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * and set INTREQ/GPCL/VBLK to logic 0. For composite we output the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * field indicator (FID) signal on FID/GLCO/VLK/HVLK and set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * INTREQ/GPCL/VBLK to logic 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mask = TVP5150_MISC_CTL_GPCL | TVP5150_MISC_CTL_HVLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (decoder->input == TVP5150_SVIDEO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) val = TVP5150_MISC_CTL_HVLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val = TVP5150_MISC_CTL_GPCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) regmap_update_bits(decoder->regmap, TVP5150_MISC_CTL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct i2c_reg_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned char value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Default values as sugested at TVP5150AM1 datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct i2c_reg_value tvp5150_init_default[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { /* 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) TVP5150_VD_IN_SRC_SEL_1, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { /* 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) TVP5150_ANAL_CHL_CTL, 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { /* 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) TVP5150_OP_MODE_CTL, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { /* 0x03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) TVP5150_MISC_CTL, 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { /* 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) TVP5150_COLOR_KIL_THSH_CTL, 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { /* 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) TVP5150_LUMA_PROC_CTL_1, 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { /* 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) TVP5150_LUMA_PROC_CTL_2, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { /* 0x09 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) TVP5150_BRIGHT_CTL, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { /* 0x0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) TVP5150_SATURATION_CTL, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { /* 0x0b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) TVP5150_HUE_CTL, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { /* 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) TVP5150_CONTRAST_CTL, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { /* 0x0d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) TVP5150_DATA_RATE_SEL, 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { /* 0x0e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) TVP5150_LUMA_PROC_CTL_3, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { /* 0x0f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) TVP5150_CONF_SHARED_PIN, 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { /* 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) TVP5150_ACT_VD_CROP_ST_MSB, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { /* 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) TVP5150_ACT_VD_CROP_ST_LSB, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { /* 0x13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) TVP5150_ACT_VD_CROP_STP_MSB, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { /* 0x14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) TVP5150_ACT_VD_CROP_STP_LSB, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { /* 0x15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) TVP5150_GENLOCK, 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { /* 0x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) TVP5150_HORIZ_SYNC_START, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { /* 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) TVP5150_VERT_BLANKING_START, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { /* 0x19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) TVP5150_VERT_BLANKING_STOP, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { /* 0x1a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) TVP5150_CHROMA_PROC_CTL_1, 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { /* 0x1b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) TVP5150_CHROMA_PROC_CTL_2, 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { /* 0x1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) TVP5150_INT_RESET_REG_B, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { /* 0x1d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) TVP5150_INT_ENABLE_REG_B, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { /* 0x1e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) TVP5150_INTT_CONFIG_REG_B, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { /* 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) TVP5150_VIDEO_STD, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { /* 0x2e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) TVP5150_MACROVISION_ON_CTR, 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { /* 0x2f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) TVP5150_MACROVISION_OFF_CTR, 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { /* 0xbb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) TVP5150_TELETEXT_FIL_ENA, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { /* 0xc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) TVP5150_INT_STATUS_REG_A, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { /* 0xc1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) TVP5150_INT_ENABLE_REG_A, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { /* 0xc2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) TVP5150_INT_CONF, 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { /* 0xc8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) TVP5150_FIFO_INT_THRESHOLD, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { /* 0xc9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) TVP5150_FIFO_RESET, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { /* 0xca */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) TVP5150_LINE_NUMBER_INT, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { /* 0xcb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) TVP5150_PIX_ALIGN_REG_LOW, 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { /* 0xcc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) TVP5150_PIX_ALIGN_REG_HIGH, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { /* 0xcd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) TVP5150_FIFO_OUT_CTRL, 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { /* 0xcf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) TVP5150_FULL_FIELD_ENA, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { /* 0xd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) TVP5150_LINE_MODE_INI, 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { /* 0xfc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) TVP5150_FULL_FIELD_MODE_REG, 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { /* end of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 0xff, 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Default values as sugested at TVP5150AM1 datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const struct i2c_reg_value tvp5150_init_enable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { /* Automatic offset and AGC enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) TVP5150_ANAL_CHL_CTL, 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }, { /* Activate YCrCb output 0x9 or 0xd ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) TVP5150_MISC_CTL, TVP5150_MISC_CTL_GPCL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) TVP5150_MISC_CTL_INTREQ_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) TVP5150_MISC_CTL_YCBCR_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) TVP5150_MISC_CTL_SYNC_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) TVP5150_MISC_CTL_VBLANK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) TVP5150_MISC_CTL_CLOCK_OE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }, { /* Activates video std autodetection for all standards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) TVP5150_AUTOSW_MSK, 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }, { /* Default format: 0x47. For 4:2:2: 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) TVP5150_DATA_RATE_SEL, 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) TVP5150_CHROMA_PROC_CTL_1, 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) TVP5150_CHROMA_PROC_CTL_2, 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }, { /* Non documented, but initialized on WinTV USB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 0x27, 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 0xff, 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct tvp5150_vbi_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned int vbi_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned int ini_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned int end_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned int by_field :1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct i2c_vbi_ram_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct tvp5150_vbi_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned char values[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* This struct have the values for each supported VBI Standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) tvp5150_vbi_types should follow the same order as vbi_ram_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * value 0 means rom position 0x10, value 1 means rom position 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * and so on. There are 16 possible locations from 0 to 15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static struct i2c_vbi_ram_value vbi_ram_default[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * FIXME: Current api doesn't handle all VBI types, those not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * yet supported are placed under #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) [0] = {0x010, /* Teletext, SECAM, WST System A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {V4L2_SLICED_TELETEXT_SECAM, 6, 23, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 0xe6, 0xb4, 0x0e, 0x00, 0x00, 0x00, 0x10, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) [1] = {0x030, /* Teletext, PAL, WST System B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {V4L2_SLICED_TELETEXT_B, 6, 22, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x2b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 0xa6, 0x72, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [2] = {0x050, /* Teletext, PAL, WST System C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {V4L2_SLICED_TELETEXT_PAL_C, 6, 22, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 0xa6, 0x98, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) [3] = {0x070, /* Teletext, NTSC, WST System B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {V4L2_SLICED_TELETEXT_NTSC_B, 10, 21, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) [4] = {0x090, /* Tetetext, NTSC NABTS System C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {V4L2_SLICED_TELETEXT_NTSC_C, 10, 21, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x15, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [5] = {0x0b0, /* Teletext, NTSC-J, NABTS System D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {V4L2_SLICED_TELETEXT_NTSC_D, 10, 21, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) { 0xaa, 0xaa, 0xff, 0xff, 0xa7, 0x2e, 0x20, 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) [6] = {0x0d0, /* Closed Caption, PAL/SECAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {V4L2_SLICED_CAPTION_625, 22, 22, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 0xa6, 0x7b, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) [7] = {0x0f0, /* Closed Caption, NTSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {V4L2_SLICED_CAPTION_525, 21, 21, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 0x69, 0x8c, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [8] = {0x110, /* Wide Screen Signal, PAL/SECAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {V4L2_SLICED_WSS_625, 23, 23, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { 0x5b, 0x55, 0xc5, 0xff, 0x00, 0x71, 0x6e, 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0xa6, 0xcd, 0x0f, 0x00, 0x00, 0x00, 0x3a, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) [9] = {0x130, /* Wide Screen Signal, NTSC C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {V4L2_SLICED_WSS_525, 20, 20, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { 0x38, 0x00, 0x3f, 0x00, 0x00, 0x71, 0x6e, 0x43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0x69, 0x7c, 0x08, 0x00, 0x00, 0x00, 0x39, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) [10] = {0x150, /* Vertical Interval Timecode (VITC), PAL/SECAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {V4l2_SLICED_VITC_625, 6, 22, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0xa6, 0x85, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) [11] = {0x170, /* Vertical Interval Timecode (VITC), NTSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {V4l2_SLICED_VITC_525, 10, 20, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 0x69, 0x94, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) [12] = {0x190, /* Video Program System (VPS), PAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {V4L2_SLICED_VPS, 16, 16, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { 0xaa, 0xaa, 0xff, 0xff, 0xba, 0xce, 0x2b, 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 0xa6, 0xda, 0x0b, 0x00, 0x00, 0x00, 0x60, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* 0x1d0 User programmable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int tvp5150_write_inittab(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) const struct i2c_reg_value *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) while (regs->reg != 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) regmap_write(decoder->regmap, regs->reg, regs->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int tvp5150_vdp_init(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct regmap *map = decoder->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Disable Full Field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) regmap_write(map, TVP5150_FULL_FIELD_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Before programming, Line mode should be at 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) regmap_write(map, i, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Load Ram Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) for (j = 0; j < ARRAY_SIZE(vbi_ram_default); j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) const struct i2c_vbi_ram_value *regs = &vbi_ram_default[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!regs->type.vbi_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) regmap_write(map, TVP5150_CONF_RAM_ADDR_HIGH, regs->reg >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) regmap_write(map, TVP5150_CONF_RAM_ADDR_LOW, regs->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) for (i = 0; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) regmap_write(map, TVP5150_VDP_CONF_RAM_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) regs->values[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Fills VBI capabilities based on i2c_vbi_ram_value struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int tvp5150_g_sliced_vbi_cap(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct v4l2_sliced_vbi_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int line, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_dbg_lvl(sd->dev, 1, debug, "g_sliced_vbi_cap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) memset(cap, 0, sizeof(*cap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) for (i = 0; i < ARRAY_SIZE(vbi_ram_default); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) const struct i2c_vbi_ram_value *regs = &vbi_ram_default[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!regs->type.vbi_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) for (line = regs->type.ini_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) line <= regs->type.end_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) line++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) cap->service_lines[0][line] |= regs->type.vbi_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) cap->service_set |= regs->type.vbi_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* Set vbi processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * type - one of tvp5150_vbi_types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * line - line to gather data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * fields: bit 0 field1, bit 1, field2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * flags (default=0xf0) is a bitmask, were set means:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * bit 7: enable filtering null bytes on CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * bit 6: send data also to FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * bit 5: don't allow data with errors on FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * bit 4: enable ECC when possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * pix_align = pix alignment:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * LSB = field1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * MSB = field2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int tvp5150_set_vbi(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned int type, u8 flags, int line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) const int fields)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) v4l2_std_id std = decoder->norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int i, pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (std == V4L2_STD_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_err(sd->dev, "VBI can't be configured without knowing number of lines\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) } else if (std & V4L2_STD_625_50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Don't follow NTSC Line number convension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) line += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (line < 6 || line > 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) for (i = 0; i < ARRAY_SIZE(vbi_ram_default); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) const struct i2c_vbi_ram_value *regs = &vbi_ram_default[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!regs->type.vbi_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if ((type & regs->type.vbi_type) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) (line >= regs->type.ini_line) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) (line <= regs->type.end_line))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) type = pos | (flags & 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (fields & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) regmap_write(decoder->regmap, reg, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (fields & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) regmap_write(decoder->regmap, reg + 1, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int tvp5150_get_vbi(struct v4l2_subdev *sd, int line)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) v4l2_std_id std = decoder->norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int pos, type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (std == V4L2_STD_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_err(sd->dev, "VBI can't be configured without knowing number of lines\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } else if (std & V4L2_STD_625_50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Don't follow NTSC Line number convension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) line += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (line < 6 || line > 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) for (i = 0; i <= 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ret = tvp5150_read(sd, reg + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_err(sd->dev, "%s: failed with error = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) pos = ret & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (pos < ARRAY_SIZE(vbi_ram_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) type |= vbi_ram_default[pos].type.vbi_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static int tvp5150_set_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int fmt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* First tests should be against specific std */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (std == V4L2_STD_NTSC_443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) fmt = VIDEO_STD_NTSC_4_43_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) } else if (std == V4L2_STD_PAL_M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) fmt = VIDEO_STD_PAL_M_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else if (std == V4L2_STD_PAL_N || std == V4L2_STD_PAL_Nc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) fmt = VIDEO_STD_PAL_COMBINATION_N_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Then, test against generic ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (std & V4L2_STD_NTSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) fmt = VIDEO_STD_NTSC_MJ_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) else if (std & V4L2_STD_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) fmt = VIDEO_STD_PAL_BDGHIN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) else if (std & V4L2_STD_SECAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) fmt = VIDEO_STD_SECAM_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev_dbg_lvl(sd->dev, 1, debug, "Set video std register to %d.\n", fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) regmap_write(decoder->regmap, TVP5150_VIDEO_STD, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int tvp5150_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) *std = decoder->norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int tvp5150_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct tvp5150_connector *cur_con = decoder->cur_connector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) v4l2_std_id supported_stds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (decoder->norm == std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* In case of no of-connectors are available no limitations are made */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!decoder->connectors_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) supported_stds = V4L2_STD_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) supported_stds = cur_con->base.connector.analog.sdtv_stds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * Check if requested std or group of std's is/are supported by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * connector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if ((supported_stds & std) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Change cropping height limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (std & V4L2_STD_525_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) decoder->rect.height = TVP5150_V_MAX_525_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) decoder->rect.height = TVP5150_V_MAX_OTHERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* Set only the specific supported std in case of group of std's. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) decoder->norm = supported_stds & std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return tvp5150_set_std(sd, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static v4l2_std_id tvp5150_read_std(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int val = tvp5150_read(sd, TVP5150_STATUS_REG_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) switch (val & 0x0F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case 0x05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return V4L2_STD_PAL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case 0x07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return V4L2_STD_PAL_N | V4L2_STD_PAL_Nc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case 0x09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return V4L2_STD_NTSC_443;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case 0xb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return V4L2_STD_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int query_lock(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (decoder->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return decoder->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) regmap_read(decoder->regmap, TVP5150_STATUS_REG_1, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* For standard detection, we need the 3 locks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return (status & 0x0e) == 0x0e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int tvp5150_querystd(struct v4l2_subdev *sd, v4l2_std_id *std_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) *std_id = query_lock(sd) ? tvp5150_read_std(sd) : V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const struct v4l2_event tvp5150_ev_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .type = V4L2_EVENT_SOURCE_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static irqreturn_t tvp5150_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct tvp5150 *decoder = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct regmap *map = decoder->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) unsigned int mask, active = 0, status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mask = TVP5150_MISC_CTL_YCBCR_OE | TVP5150_MISC_CTL_SYNC_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) TVP5150_MISC_CTL_CLOCK_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) regmap_read(map, TVP5150_INT_STATUS_REG_A, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) regmap_write(map, TVP5150_INT_STATUS_REG_A, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (status & TVP5150_INT_A_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) decoder->lock = !!(status & TVP5150_INT_A_LOCK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dev_dbg_lvl(decoder->sd.dev, 1, debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) "sync lo%s signal\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) decoder->lock ? "ck" : "ss");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) v4l2_subdev_notify_event(&decoder->sd, &tvp5150_ev_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) regmap_update_bits(map, TVP5150_MISC_CTL, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) decoder->lock ? decoder->oe : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) regmap_read(map, TVP5150_INT_ACTIVE_REG_B, &active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) regmap_read(map, TVP5150_INT_STATUS_REG_B, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) regmap_write(map, TVP5150_INT_RESET_REG_B, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int tvp5150_reset(struct v4l2_subdev *sd, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct regmap *map = decoder->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* Initializes TVP5150 to its default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) tvp5150_write_inittab(sd, tvp5150_init_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (decoder->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Configure pins: FID, VSYNC, INTREQ, SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) regmap_write(map, TVP5150_CONF_SHARED_PIN, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Set interrupt polarity to active high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) regmap_write(map, TVP5150_INT_CONF, TVP5150_VDPOE | 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) regmap_write(map, TVP5150_INTT_CONFIG_REG_B, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Configure pins: FID, VSYNC, GPCL/VBLK, SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) regmap_write(map, TVP5150_CONF_SHARED_PIN, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Keep interrupt polarity active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) regmap_write(map, TVP5150_INT_CONF, TVP5150_VDPOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) regmap_write(map, TVP5150_INTT_CONFIG_REG_B, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Initializes VDP registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) tvp5150_vdp_init(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Selects decoder input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) tvp5150_selmux(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* Initialize image preferences */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) v4l2_ctrl_handler_setup(&decoder->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int tvp5150_enable(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) v4l2_std_id std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* Initializes TVP5150 to stream enabled values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) tvp5150_write_inittab(sd, tvp5150_init_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (decoder->norm == V4L2_STD_ALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) std = tvp5150_read_std(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) std = decoder->norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Disable autoswitch mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) tvp5150_set_std(sd, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * Enable the YCbCr and clock outputs. In discrete sync mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * (non-BT.656) additionally enable the the sync outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) switch (decoder->mbus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) case V4L2_MBUS_PARALLEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* 8-bit 4:2:2 YUV with discrete sync output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) regmap_update_bits(decoder->regmap, TVP5150_DATA_RATE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) 0x7, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) decoder->oe = TVP5150_MISC_CTL_YCBCR_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) TVP5150_MISC_CTL_CLOCK_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) TVP5150_MISC_CTL_SYNC_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) case V4L2_MBUS_BT656:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) decoder->oe = TVP5150_MISC_CTL_YCBCR_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) TVP5150_MISC_CTL_CLOCK_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int tvp5150_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) regmap_write(decoder->regmap, TVP5150_BRIGHT_CTL, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) regmap_write(decoder->regmap, TVP5150_CONTRAST_CTL, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) regmap_write(decoder->regmap, TVP5150_SATURATION_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) regmap_write(decoder->regmap, TVP5150_HUE_CTL, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) decoder->enable = ctrl->val ? false : true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) tvp5150_selmux(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static void tvp5150_set_default(v4l2_std_id std, struct v4l2_rect *crop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* Default is no cropping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) crop->top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) crop->left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) crop->width = TVP5150_H_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (std & V4L2_STD_525_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) crop->height = TVP5150_V_MAX_525_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) crop->height = TVP5150_V_MAX_OTHERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static struct v4l2_rect *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) tvp5150_get_pad_crop(struct tvp5150 *decoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct v4l2_subdev_pad_config *cfg, unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) enum v4l2_subdev_format_whence which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) case V4L2_SUBDEV_FORMAT_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return &decoder->rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) case V4L2_SUBDEV_FORMAT_TRY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #if defined(CONFIG_VIDEO_V4L2_SUBDEV_API)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return v4l2_subdev_get_try_crop(&decoder->sd, cfg, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static int tvp5150_fill_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct v4l2_mbus_framefmt *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (!format || (format->pad != TVP5150_PAD_VID_OUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) f = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) f->width = decoder->rect.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) f->height = decoder->rect.height / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) f->code = TVP5150_MBUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) f->field = TVP5150_FIELD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) f->colorspace = TVP5150_COLORSPACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dev_dbg_lvl(sd->dev, 1, debug, "width = %d, height = %d\n", f->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) f->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static unsigned int tvp5150_get_hmax(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) v4l2_std_id std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* Calculate height based on current standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (decoder->norm == V4L2_STD_ALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) std = tvp5150_read_std(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) std = decoder->norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return (std & V4L2_STD_525_60) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) TVP5150_V_MAX_525_60 : TVP5150_V_MAX_OTHERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static void tvp5150_set_hw_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct v4l2_rect *rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) unsigned int hmax = tvp5150_get_hmax(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) regmap_write(decoder->regmap, TVP5150_VERT_BLANKING_START, rect->top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) regmap_write(decoder->regmap, TVP5150_VERT_BLANKING_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) rect->top + rect->height - hmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) regmap_write(decoder->regmap, TVP5150_ACT_VD_CROP_ST_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) rect->left >> TVP5150_CROP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) regmap_write(decoder->regmap, TVP5150_ACT_VD_CROP_ST_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) rect->left | (1 << TVP5150_CROP_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) regmap_write(decoder->regmap, TVP5150_ACT_VD_CROP_STP_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) (rect->left + rect->width - TVP5150_MAX_CROP_LEFT) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) TVP5150_CROP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) regmap_write(decoder->regmap, TVP5150_ACT_VD_CROP_STP_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) rect->left + rect->width - TVP5150_MAX_CROP_LEFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static int tvp5150_set_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct v4l2_rect *rect = &sel->r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct v4l2_rect *crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) unsigned int hmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (sel->target != V4L2_SEL_TGT_CROP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev_dbg_lvl(sd->dev, 1, debug, "%s left=%d, top=%d, width=%d, height=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) __func__, rect->left, rect->top, rect->width, rect->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* tvp5150 has some special limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) rect->left = clamp(rect->left, 0, TVP5150_MAX_CROP_LEFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) rect->top = clamp(rect->top, 0, TVP5150_MAX_CROP_TOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) hmax = tvp5150_get_hmax(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * alignments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * - width = 2 due to UYVY colorspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * - height, image = no special alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) v4l_bound_align_image(&rect->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) TVP5150_H_MAX - TVP5150_MAX_CROP_LEFT - rect->left,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) TVP5150_H_MAX - rect->left, 1, &rect->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) hmax - TVP5150_MAX_CROP_TOP - rect->top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) hmax - rect->top, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (!IS_ENABLED(CONFIG_VIDEO_V4L2_SUBDEV_API) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) sel->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) crop = tvp5150_get_pad_crop(decoder, cfg, sel->pad, sel->which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (IS_ERR(crop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return PTR_ERR(crop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * Update output image size if the selection (crop) rectangle size or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * position has been modified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) !v4l2_rect_equal(rect, crop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) tvp5150_set_hw_selection(sd, rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) *crop = *rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static int tvp5150_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct tvp5150 *decoder = container_of(sd, struct tvp5150, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct v4l2_rect *crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) v4l2_std_id std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) switch (sel->target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) case V4L2_SEL_TGT_CROP_BOUNDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) sel->r.width = TVP5150_H_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Calculate height based on current standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (decoder->norm == V4L2_STD_ALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) std = tvp5150_read_std(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) std = decoder->norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (std & V4L2_STD_525_60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) sel->r.height = TVP5150_V_MAX_525_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) sel->r.height = TVP5150_V_MAX_OTHERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) case V4L2_SEL_TGT_CROP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) crop = tvp5150_get_pad_crop(decoder, cfg, sel->pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) sel->which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (IS_ERR(crop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return PTR_ERR(crop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) sel->r = *crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static int tvp5150_get_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) cfg->type = decoder->mbus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) | V4L2_MBUS_FIELD_EVEN_LOW | V4L2_MBUS_DATA_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) V4L2 subdev pad ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static int tvp5150_init_cfg(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct v4l2_subdev_pad_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) v4l2_std_id std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * Reset selection to maximum on subdev_open() if autodetection is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * and a standard change is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (decoder->norm == V4L2_STD_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) std = tvp5150_read_std(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (std != decoder->detected_norm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) decoder->detected_norm = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) tvp5150_set_default(std, &decoder->rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int tvp5150_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (code->pad || code->index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) code->code = TVP5150_MBUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static int tvp5150_enum_frame_size(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (fse->index >= 8 || fse->code != TVP5150_MBUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) fse->code = TVP5150_MBUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) fse->min_width = decoder->rect.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) fse->max_width = decoder->rect.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) fse->min_height = decoder->rect.height / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) fse->max_height = decoder->rect.height / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * Media entity ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static int tvp5150_set_link(struct media_pad *connector_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct media_pad *tvp5150_pad, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct media_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) link = media_entity_find_link(connector_pad, tvp5150_pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (!link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) link->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) link->reverse->flags = link->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static int tvp5150_disable_all_input_links(struct tvp5150 *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct media_pad *connector_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) for (i = 0; i < TVP5150_NUM_PADS - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) connector_pad = media_entity_remote_pad(&decoder->pads[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (!connector_pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) err = tvp5150_set_link(connector_pad, &decoder->pads[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static int tvp5150_s_routing(struct v4l2_subdev *sd, u32 input, u32 output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) u32 config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static int tvp5150_link_setup(struct media_entity *entity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) const struct media_pad *tvp5150_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) const struct media_pad *remote, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct media_pad *other_tvp5150_pad =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) &decoder->pads[tvp5150_pad->index ^ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct v4l2_fwnode_connector *v4l2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) bool is_svideo = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * The TVP5150 state is determined by the enabled sink pad link(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * Enabling or disabling the source pad link has no effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (tvp5150_pad->flags & MEDIA_PAD_FL_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* Check if the svideo connector should be enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) for (i = 0; i < decoder->connectors_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (remote->entity == &decoder->connectors[i].ent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) v4l2c = &decoder->connectors[i].base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) is_svideo = v4l2c->type == V4L2_CONN_SVIDEO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) dev_dbg_lvl(sd->dev, 1, debug, "link setup '%s':%d->'%s':%d[%d]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) remote->entity->name, remote->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) tvp5150_pad->entity->name, tvp5150_pad->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) flags & MEDIA_LNK_FL_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (is_svideo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) dev_dbg_lvl(sd->dev, 1, debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) "link setup '%s':%d->'%s':%d[%d]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) remote->entity->name, remote->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) other_tvp5150_pad->entity->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) other_tvp5150_pad->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) flags & MEDIA_LNK_FL_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * The TVP5150 has an internal mux which allows the following setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * comp-connector1 --\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * |---> AIP1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * svideo-connector -|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * |---> AIP1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * comp-connector2 --/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * We can't rely on user space that the current connector gets disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * first before enabling the new connector. Disable all active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * connector links to be on the safe side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) err = tvp5150_disable_all_input_links(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) tvp5150_s_routing(sd, is_svideo ? TVP5150_SVIDEO : tvp5150_pad->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) flags & MEDIA_LNK_FL_ENABLED ? TVP5150_NORMAL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) TVP5150_BLACK_SCREEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (flags & MEDIA_LNK_FL_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) struct v4l2_fwnode_connector_analog *v4l2ca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) u32 new_norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * S-Video connector is conneted to both ports AIP1A and AIP1B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * Both links must be enabled in one-shot regardless which link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * the user requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (is_svideo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) err = tvp5150_set_link((struct media_pad *)remote,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) other_tvp5150_pad, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (!decoder->connectors_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /* Update the current connector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) decoder->cur_connector =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) container_of(remote, struct tvp5150_connector, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * Do nothing if the new connector supports the same tv-norms as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * the old one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) v4l2ca = &decoder->cur_connector->base.connector.analog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) new_norm = decoder->norm & v4l2ca->sdtv_stds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (decoder->norm == new_norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * Fallback to the new connector tv-norms if we can't find any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * common between the current tv-norm and the new one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) tvp5150_s_std(sd, new_norm ? new_norm : v4l2ca->sdtv_stds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static const struct media_entity_operations tvp5150_sd_media_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .link_setup = tvp5150_link_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) I2C Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static int __maybe_unused tvp5150_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (decoder->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* Disable lock interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return regmap_update_bits(decoder->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) TVP5150_INT_ENABLE_REG_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) TVP5150_INT_A_LOCK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static int __maybe_unused tvp5150_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (decoder->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* Enable lock interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return regmap_update_bits(decoder->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) TVP5150_INT_ENABLE_REG_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) TVP5150_INT_A_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) TVP5150_INT_A_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static int tvp5150_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) unsigned int mask, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) mask = TVP5150_MISC_CTL_YCBCR_OE | TVP5150_MISC_CTL_SYNC_OE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) TVP5150_MISC_CTL_CLOCK_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ret = pm_runtime_get_sync(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) pm_runtime_put_noidle(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) tvp5150_enable(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /* Enable outputs if decoder is locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (decoder->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) val = decoder->lock ? decoder->oe : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) val = decoder->oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) v4l2_subdev_notify_event(&decoder->sd, &tvp5150_ev_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) pm_runtime_put(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) regmap_update_bits(decoder->regmap, TVP5150_MISC_CTL, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static int tvp5150_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) decoder->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) decoder->output = output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (output == TVP5150_BLACK_SCREEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) decoder->enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) decoder->enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) tvp5150_selmux(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static int tvp5150_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * this is for capturing 36 raw vbi lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) * if there's a way to cut off the beginning 2 vbi lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * with the tvp5150 then the vbi line count could be lowered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * to 17 lines/field again, although I couldn't find a register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * which could do that cropping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (fmt->sample_format == V4L2_PIX_FMT_GREY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) regmap_write(decoder->regmap, TVP5150_LUMA_PROC_CTL_1, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (fmt->count[0] == 18 && fmt->count[1] == 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) regmap_write(decoder->regmap, TVP5150_VERT_BLANKING_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) regmap_write(decoder->regmap, TVP5150_VERT_BLANKING_STOP, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static int tvp5150_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (svbi->service_set != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) for (i = 0; i <= 23; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) svbi->service_lines[1][i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) svbi->service_lines[0][i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) tvp5150_set_vbi(sd, svbi->service_lines[0][i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) 0xf0, i, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* Enables FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) regmap_write(decoder->regmap, TVP5150_FIFO_OUT_CTRL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* Disables FIFO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) regmap_write(decoder->regmap, TVP5150_FIFO_OUT_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* Disable Full Field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) regmap_write(decoder->regmap, TVP5150_FULL_FIELD_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* Disable Line modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) regmap_write(decoder->regmap, i, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static int tvp5150_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) int i, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) memset(svbi->service_lines, 0, sizeof(svbi->service_lines));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) for (i = 0; i <= 23; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) svbi->service_lines[0][i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) tvp5150_get_vbi(sd, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) mask |= svbi->service_lines[0][i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) svbi->service_set = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static int tvp5150_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) res = tvp5150_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) dev_err(sd->dev, "%s: failed with error = %d\n", __func__, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) reg->val = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static int tvp5150_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return regmap_write(decoder->regmap, reg->reg & 0xff, reg->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static int tvp5150_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct v4l2_event_subscription *sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) switch (sub->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) case V4L2_EVENT_SOURCE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) case V4L2_EVENT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static int tvp5150_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) int status = tvp5150_read(sd, 0x88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) vt->signal = ((status & 0x04) && (status & 0x02)) ? 0xffff : 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static int tvp5150_registered(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) * Setup connector pads and links. Enable the link to the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) * available connector per default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) for (i = 0; i < decoder->connectors_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct media_entity *con = &decoder->connectors[i].ent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) struct media_pad *pad = &decoder->connectors[i].pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct v4l2_fwnode_connector *v4l2c =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) &decoder->connectors[i].base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct v4l2_connector_link *link =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) v4l2_connector_first_link(v4l2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) unsigned int port = link->fwnode_link.remote_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) unsigned int flags = i ? 0 : MEDIA_LNK_FL_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) bool is_svideo = v4l2c->type == V4L2_CONN_SVIDEO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) pad->flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ret = media_entity_pads_init(con, 1, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ret = media_device_register_entity(sd->v4l2_dev->mdev, con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ret = media_create_pad_link(con, 0, &sd->entity, port, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (is_svideo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) * Check tvp5150_link_setup() comments for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) * information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) link = v4l2_connector_last_link(v4l2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) port = link->fwnode_link.remote_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) ret = media_create_pad_link(con, 0, &sd->entity, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* Enable default input. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (flags == MEDIA_LNK_FL_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) decoder->input =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) is_svideo ? TVP5150_SVIDEO :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) port == 0 ? TVP5150_COMPOSITE0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) TVP5150_COMPOSITE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) tvp5150_selmux(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) decoder->cur_connector = &decoder->connectors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) tvp5150_s_std(sd, v4l2c->connector.analog.sdtv_stds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) for (i = 0; i < decoder->connectors_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) media_device_unregister_entity(&decoder->connectors[i].ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) media_entity_cleanup(&decoder->connectors[i].ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static int tvp5150_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ret = pm_runtime_get_sync(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) pm_runtime_put_noidle(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static int tvp5150_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) pm_runtime_put(sd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static const struct v4l2_ctrl_ops tvp5150_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .s_ctrl = tvp5150_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static const struct v4l2_subdev_core_ops tvp5150_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .log_status = tvp5150_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .reset = tvp5150_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .g_register = tvp5150_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .s_register = tvp5150_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .subscribe_event = tvp5150_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static const struct v4l2_subdev_tuner_ops tvp5150_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .g_tuner = tvp5150_g_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static const struct v4l2_subdev_video_ops tvp5150_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .s_std = tvp5150_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .g_std = tvp5150_g_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .querystd = tvp5150_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .s_stream = tvp5150_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .s_routing = tvp5150_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static const struct v4l2_subdev_vbi_ops tvp5150_vbi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .g_sliced_vbi_cap = tvp5150_g_sliced_vbi_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .g_sliced_fmt = tvp5150_g_sliced_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .s_sliced_fmt = tvp5150_s_sliced_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .s_raw_fmt = tvp5150_s_raw_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) static const struct v4l2_subdev_pad_ops tvp5150_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .init_cfg = tvp5150_init_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .enum_mbus_code = tvp5150_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .enum_frame_size = tvp5150_enum_frame_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .set_fmt = tvp5150_fill_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .get_fmt = tvp5150_fill_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .get_selection = tvp5150_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .set_selection = tvp5150_set_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .get_mbus_config = tvp5150_get_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) static const struct v4l2_subdev_ops tvp5150_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .core = &tvp5150_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .tuner = &tvp5150_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .video = &tvp5150_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .vbi = &tvp5150_vbi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .pad = &tvp5150_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static const struct v4l2_subdev_internal_ops tvp5150_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .registered = tvp5150_registered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .open = tvp5150_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .close = tvp5150_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) /****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) I2C Client & Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) static const struct regmap_range tvp5150_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .range_min = TVP5150_VD_IN_SRC_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .range_max = TVP5150_AUTOSW_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .range_min = TVP5150_COLOR_KIL_THSH_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .range_max = TVP5150_CONF_SHARED_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .range_min = TVP5150_ACT_VD_CROP_ST_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .range_max = TVP5150_HORIZ_SYNC_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .range_min = TVP5150_VERT_BLANKING_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .range_max = TVP5150_INTT_CONFIG_REG_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .range_min = TVP5150_VIDEO_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .range_max = TVP5150_VIDEO_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .range_min = TVP5150_CB_GAIN_FACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .range_max = TVP5150_REV_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .range_min = TVP5150_MSB_DEV_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .range_max = TVP5150_STATUS_REG_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .range_min = TVP5150_CC_DATA_INI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .range_max = TVP5150_TELETEXT_FIL_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .range_min = TVP5150_INT_STATUS_REG_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .range_max = TVP5150_FIFO_OUT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .range_min = TVP5150_FULL_FIELD_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .range_max = TVP5150_FULL_FIELD_MODE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static bool tvp5150_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) case TVP5150_VERT_LN_COUNT_MSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) case TVP5150_VERT_LN_COUNT_LSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) case TVP5150_INT_STATUS_REG_A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) case TVP5150_INT_STATUS_REG_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) case TVP5150_INT_ACTIVE_REG_B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) case TVP5150_STATUS_REG_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) case TVP5150_STATUS_REG_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) case TVP5150_STATUS_REG_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) case TVP5150_STATUS_REG_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) case TVP5150_STATUS_REG_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /* CC, WSS, VPS, VITC data? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) case TVP5150_VBI_FIFO_READ_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) case TVP5150_VDP_STATUS_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) case TVP5150_FIFO_WORD_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static const struct regmap_access_table tvp5150_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .yes_ranges = tvp5150_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .n_yes_ranges = ARRAY_SIZE(tvp5150_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static struct regmap_config tvp5150_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .max_register = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .rd_table = &tvp5150_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .volatile_reg = tvp5150_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) static int tvp5150_detect_version(struct tvp5150 *core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) struct v4l2_subdev *sd = &core->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) struct i2c_client *c = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) u8 regs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * Read consequent registers - TVP5150_MSB_DEV_ID, TVP5150_LSB_DEV_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * TVP5150_ROM_MAJOR_VER, TVP5150_ROM_MINOR_VER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) res = regmap_bulk_read(core->regmap, TVP5150_MSB_DEV_ID, regs, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) dev_err(&c->dev, "reading ID registers failed: %d\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) core->dev_id = (regs[0] << 8) | regs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) core->rom_ver = (regs[2] << 8) | regs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) dev_info(sd->dev, "tvp%04x (%u.%u) chip found @ 0x%02x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) core->dev_id, regs[2], regs[3], c->addr << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) c->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (core->dev_id == 0x5150 && core->rom_ver == 0x0321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) dev_info(sd->dev, "tvp5150a detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) } else if (core->dev_id == 0x5150 && core->rom_ver == 0x0400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) dev_info(sd->dev, "tvp5150am1 detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /* ITU-T BT.656.4 timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) regmap_write(core->regmap, TVP5150_REV_SELECT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) } else if (core->dev_id == 0x5151 && core->rom_ver == 0x0100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) dev_info(sd->dev, "tvp5151 detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) dev_info(sd->dev, "*** unknown tvp%04x chip detected.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) core->dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static int tvp5150_init(struct i2c_client *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) struct gpio_desc *pdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) pdn_gpio = devm_gpiod_get_optional(&c->dev, "pdn", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (IS_ERR(pdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return PTR_ERR(pdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (pdn_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) gpiod_set_value_cansleep(pdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* Delay time between power supplies active and reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) reset_gpio = devm_gpiod_get_optional(&c->dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (IS_ERR(reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) return PTR_ERR(reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (reset_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /* RESETB pulse duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) ndelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) gpiod_set_value_cansleep(reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* Delay time between end of reset to I2C active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) usleep_range(200, 250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static int tvp5150_mc_init(struct tvp5150 *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) struct v4l2_subdev *sd = &decoder->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) sd->entity.ops = &tvp5150_sd_media_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) for (i = 0; i < TVP5150_NUM_PADS - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) decoder->pads[i].flags = MEDIA_PAD_FL_SINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) decoder->pads[i].sig_type = PAD_SIGNAL_ANALOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) decoder->pads[i].flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) decoder->pads[i].sig_type = PAD_SIGNAL_DV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) return media_entity_pads_init(&sd->entity, TVP5150_NUM_PADS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) decoder->pads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #else /* !defined(CONFIG_MEDIA_CONTROLLER) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static inline int tvp5150_mc_init(struct tvp5150 *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #endif /* defined(CONFIG_MEDIA_CONTROLLER) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static int tvp5150_validate_connectors(struct tvp5150 *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) struct device *dev = decoder->sd.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) struct tvp5150_connector *tvpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) struct v4l2_fwnode_connector *v4l2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) if (!decoder->connectors_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) dev_err(dev, "No valid connector found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) for (i = 0; i < decoder->connectors_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) struct v4l2_connector_link *link0 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) struct v4l2_connector_link *link1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) tvpc = &decoder->connectors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) v4l2c = &tvpc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (v4l2c->type == V4L2_CONN_COMPOSITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (v4l2c->nr_of_links != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) dev_err(dev, "Composite: connector needs 1 link\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) link0 = v4l2_connector_first_link(v4l2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (!link0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) dev_err(dev, "Composite: invalid first link\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if (link0->fwnode_link.remote_id == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) dev_err(dev, "Composite: invalid endpoint id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (v4l2c->type == V4L2_CONN_SVIDEO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (v4l2c->nr_of_links != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) dev_err(dev, "SVideo: connector needs 2 links\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) link0 = v4l2_connector_first_link(v4l2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (!link0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) dev_err(dev, "SVideo: invalid first link\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) link1 = v4l2_connector_last_link(v4l2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (link0->fwnode_link.remote_port ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) link1->fwnode_link.remote_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) dev_err(dev, "SVideo: invalid link setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) if (!(v4l2c->connector.analog.sdtv_stds & TVP5150_STD_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) dev_err(dev, "Unsupported tv-norm on connector %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) v4l2c->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static int tvp5150_parse_dt(struct tvp5150 *decoder, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) struct device *dev = decoder->sd.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) struct v4l2_fwnode_endpoint bus_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .bus_type = V4L2_MBUS_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) struct device_node *ep_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) struct tvp5150_connector *tvpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) struct v4l2_fwnode_connector *v4l2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) unsigned int flags, ep_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) /* At least 1 output and 1 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) ep_num = of_graph_get_endpoint_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (ep_num < 2 || ep_num > 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) dev_err(dev, "At least 1 input and 1 output must be connected to the device.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /* Layout if all connectors are used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * tvp-5150 port@0 (AIP1A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) * endpoint@0 -----------> Comp0-Con port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * endpoint@1 --------+--> Svideo-Con port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) * tvp-5150 port@1 (AIP1B) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) * endpoint@1 --------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) * endpoint@0 -----------> Comp1-Con port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) * tvp-5150 port@2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) * endpoint (video bitstream output at YOUT[0-7] parallel bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) for_each_endpoint_of_node(np, ep_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) struct fwnode_handle *ep_fwnode = of_fwnode_handle(ep_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) unsigned int next_connector = decoder->connectors_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) struct of_endpoint ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) of_graph_parse_endpoint(ep_np, &ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (ep.port > 1 || ep.id > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) dev_dbg(dev, "Ignore connector on port@%u/ep@%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ep.port, ep.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) tvpc = &decoder->connectors[next_connector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) v4l2c = &tvpc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) if (ep.port == 0 || (ep.port == 1 && ep.id == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) ret = v4l2_fwnode_connector_parse(ep_fwnode, v4l2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) goto err_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) ret = v4l2_fwnode_connector_add_link(ep_fwnode, v4l2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) goto err_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) decoder->connectors_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) /* Adding the 2nd svideo link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) for (i = 0; i < TVP5150_MAX_CONNECTORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) tvpc = &decoder->connectors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) v4l2c = &tvpc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (v4l2c->type == V4L2_CONN_SVIDEO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) ret = v4l2_fwnode_connector_add_link(ep_fwnode, v4l2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) goto err_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) ret = tvp5150_validate_connectors(decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) for (i = 0; i < decoder->connectors_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) tvpc = &decoder->connectors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) v4l2c = &tvpc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) tvpc->ent.flags = MEDIA_ENT_FL_CONNECTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) tvpc->ent.function = v4l2c->type == V4L2_CONN_SVIDEO ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) MEDIA_ENT_F_CONN_SVIDEO : MEDIA_ENT_F_CONN_COMPOSITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) tvpc->ent.name = devm_kasprintf(dev, GFP_KERNEL, "%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) v4l2c->name, v4l2c->label ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) v4l2c->label : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) ep_np = of_graph_get_endpoint_by_regs(np, TVP5150_PAD_VID_OUT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) if (!ep_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) dev_err(dev, "Error no output endpoint available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_np), &bus_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) of_node_put(ep_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) flags = bus_cfg.bus.parallel.flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (bus_cfg.bus_type == V4L2_MBUS_PARALLEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) !(flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) flags & V4L2_MBUS_FIELD_EVEN_LOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) decoder->mbus_type = bus_cfg.bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) err_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) of_node_put(ep_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) for (i = 0; i < TVP5150_MAX_CONNECTORS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) v4l2_fwnode_connector_free(&decoder->connectors[i].base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) static const char * const tvp5150_test_patterns[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) "Black screen"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) static int tvp5150_probe(struct i2c_client *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) struct tvp5150 *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct device_node *np = c->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) if (!i2c_check_functionality(c->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) res = tvp5150_init(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) core = devm_kzalloc(&c->dev, sizeof(*core), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (!core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) map = devm_regmap_init_i2c(c, &tvp5150_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (IS_ERR(map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) core->regmap = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) sd = &core->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) v4l2_i2c_subdev_init(sd, c, &tvp5150_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) sd->internal_ops = &tvp5150_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (IS_ENABLED(CONFIG_OF) && np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) res = tvp5150_parse_dt(core, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) dev_err(sd->dev, "DT parsing error: %d\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /* Default to BT.656 embedded sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) core->mbus_type = V4L2_MBUS_BT656;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) res = tvp5150_mc_init(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) res = tvp5150_detect_version(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) * Iterate over all available connectors in case they are supported and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) * successfully parsed. Fallback to default autodetect in case they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) * aren't supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) for (i = 0; i < core->connectors_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) struct v4l2_fwnode_connector *v4l2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) v4l2c = &core->connectors[i].base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) core->norm |= v4l2c->connector.analog.sdtv_stds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) if (!core->connectors_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) core->norm = V4L2_STD_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) core->detected_norm = V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) core->input = TVP5150_COMPOSITE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) core->enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) v4l2_ctrl_handler_init(&core->hdl, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) V4L2_CID_CONTRAST, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) V4L2_CID_SATURATION, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) V4L2_CID_HUE, -128, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) V4L2_CID_PIXEL_RATE, 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) 27000000, 1, 27000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) v4l2_ctrl_new_std_menu_items(&core->hdl, &tvp5150_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) ARRAY_SIZE(tvp5150_test_patterns) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) 0, 0, tvp5150_test_patterns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) sd->ctrl_handler = &core->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) if (core->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) res = core->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) tvp5150_set_default(tvp5150_read_std(sd), &core->rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) core->irq = c->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) tvp5150_reset(sd, 0); /* Calls v4l2_ctrl_handler_setup() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (c->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) res = devm_request_threaded_irq(&c->dev, c->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) tvp5150_isr, IRQF_TRIGGER_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) IRQF_ONESHOT, "tvp5150", core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) res = v4l2_async_register_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) if (res < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) if (debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) tvp5150_log_status(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) pm_runtime_set_active(&c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) pm_runtime_enable(&c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) pm_runtime_idle(&c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) v4l2_ctrl_handler_free(&core->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static int tvp5150_remove(struct i2c_client *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) struct v4l2_subdev *sd = i2c_get_clientdata(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) struct tvp5150 *decoder = to_tvp5150(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) dev_dbg_lvl(sd->dev, 1, debug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) "tvp5150.c: removing tvp5150 adapter on address 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) c->addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) for (i = 0; i < decoder->connectors_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) v4l2_fwnode_connector_free(&decoder->connectors[i].base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) for (i = 0; i < decoder->connectors_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) media_device_unregister_entity(&decoder->connectors[i].ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) media_entity_cleanup(&decoder->connectors[i].ent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) v4l2_ctrl_handler_free(&decoder->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) pm_runtime_disable(&c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) pm_runtime_set_suspended(&c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) static const struct dev_pm_ops tvp5150_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) SET_RUNTIME_PM_OPS(tvp5150_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) tvp5150_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) static const struct i2c_device_id tvp5150_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) { "tvp5150", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) MODULE_DEVICE_TABLE(i2c, tvp5150_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) static const struct of_device_id tvp5150_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) { .compatible = "ti,tvp5150", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) MODULE_DEVICE_TABLE(of, tvp5150_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) static struct i2c_driver tvp5150_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .of_match_table = of_match_ptr(tvp5150_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .name = "tvp5150",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .pm = &tvp5150_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .probe_new = tvp5150_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .remove = tvp5150_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .id_table = tvp5150_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) module_i2c_driver(tvp5150_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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