Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * drivers/media/i2c/tvp514x_regs.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2008 Texas Instruments Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Vaibhav Hiremath <hvaibhav@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Contributors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *     Sivaraj R <sivaraj@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *     Brijesh R Jadav <brijesh.j@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *     Hardik Shah <hardik.shah@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *     Manjunath Hadli <mrh@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *     Karicheri Muralidharan <m-karicheri2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #ifndef _TVP514X_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define _TVP514X_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * TVP5146/47 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_INPUT_SEL			(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_AFE_GAIN_CTRL		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_VIDEO_STD			(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_OPERATION_MODE		(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_AUTOSWITCH_MASK		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_COLOR_KILLER		(0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_LUMA_CONTROL1		(0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_LUMA_CONTROL2		(0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REG_LUMA_CONTROL3		(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define REG_BRIGHTNESS			(0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define REG_CONTRAST			(0x0A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define REG_SATURATION			(0x0B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define REG_HUE				(0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define REG_CHROMA_CONTROL1		(0x0D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define REG_CHROMA_CONTROL2		(0x0E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* 0x0F Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define REG_COMP_PR_SATURATION		(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define REG_COMP_Y_CONTRAST		(0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define REG_COMP_PB_SATURATION		(0x12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* 0x13 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define REG_COMP_Y_BRIGHTNESS		(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* 0x15 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define REG_AVID_START_PIXEL_LSB	(0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define REG_AVID_START_PIXEL_MSB	(0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define REG_AVID_STOP_PIXEL_LSB		(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define REG_AVID_STOP_PIXEL_MSB		(0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define REG_HSYNC_START_PIXEL_LSB	(0x1A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define REG_HSYNC_START_PIXEL_MSB	(0x1B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define REG_HSYNC_STOP_PIXEL_LSB	(0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define REG_HSYNC_STOP_PIXEL_MSB	(0x1D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define REG_VSYNC_START_LINE_LSB	(0x1E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define REG_VSYNC_START_LINE_MSB	(0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define REG_VSYNC_STOP_LINE_LSB		(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define REG_VSYNC_STOP_LINE_MSB		(0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define REG_VBLK_START_LINE_LSB		(0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define REG_VBLK_START_LINE_MSB		(0x23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define REG_VBLK_STOP_LINE_LSB		(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define REG_VBLK_STOP_LINE_MSB		(0x25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* 0x26 - 0x27 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define REG_FAST_SWTICH_CONTROL		(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* 0x29 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define REG_FAST_SWTICH_SCART_DELAY	(0x2A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* 0x2B Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define REG_SCART_DELAY			(0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define REG_CTI_DELAY			(0x2D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define REG_CTI_CONTROL			(0x2E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* 0x2F - 0x31 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define REG_SYNC_CONTROL		(0x32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define REG_OUTPUT_FORMATTER1		(0x33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define REG_OUTPUT_FORMATTER2		(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define REG_OUTPUT_FORMATTER3		(0x35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define REG_OUTPUT_FORMATTER4		(0x36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define REG_OUTPUT_FORMATTER5		(0x37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define REG_OUTPUT_FORMATTER6		(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define REG_CLEAR_LOST_LOCK		(0x39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define REG_STATUS1			(0x3A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define REG_STATUS2			(0x3B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_AGC_GAIN_STATUS_LSB		(0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_AGC_GAIN_STATUS_MSB		(0x3D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* 0x3E Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define REG_VIDEO_STD_STATUS		(0x3F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define REG_GPIO_INPUT1			(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_GPIO_INPUT2			(0x41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* 0x42 - 0x45 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_AFE_COARSE_GAIN_CH1		(0x46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define REG_AFE_COARSE_GAIN_CH2		(0x47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define REG_AFE_COARSE_GAIN_CH3		(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define REG_AFE_COARSE_GAIN_CH4		(0x49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define REG_AFE_FINE_GAIN_PB_B_LSB	(0x4A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define REG_AFE_FINE_GAIN_PB_B_MSB	(0x4B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB	(0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB	(0x4D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define REG_AFE_FINE_GAIN_PR_R_LSB	(0x4E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define REG_AFE_FINE_GAIN_PR_R_MSB	(0x4F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define REG_AFE_FINE_GAIN_CVBS_LUMA_LSB	(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define REG_AFE_FINE_GAIN_CVBS_LUMA_MSB	(0x51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* 0x52 - 0x68 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define REG_FBIT_VBIT_CONTROL1		(0x69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* 0x6A - 0x6B Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define REG_BACKEND_AGC_CONTROL		(0x6C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* 0x6D - 0x6E Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define REG_AGC_DECREMENT_SPEED_CONTROL	(0x6F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define REG_ROM_VERSION			(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* 0x71 - 0x73 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define REG_AGC_WHITE_PEAK_PROCESSING	(0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define REG_FBIT_VBIT_CONTROL2		(0x75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define REG_VCR_TRICK_MODE_CONTROL	(0x76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define REG_HORIZONTAL_SHAKE_INCREMENT	(0x77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define REG_AGC_INCREMENT_SPEED		(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define REG_AGC_INCREMENT_DELAY		(0x79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* 0x7A - 0x7F Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define REG_CHIP_ID_MSB			(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define REG_CHIP_ID_LSB			(0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* 0x82 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define REG_CPLL_SPEED_CONTROL		(0x83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* 0x84 - 0x96 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define REG_STATUS_REQUEST		(0x97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* 0x98 - 0x99 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define REG_VERTICAL_LINE_COUNT_LSB	(0x9A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define REG_VERTICAL_LINE_COUNT_MSB	(0x9B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* 0x9C - 0x9D Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define REG_AGC_DECREMENT_DELAY		(0x9E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* 0x9F - 0xB0 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define REG_VDP_TTX_FILTER_1_MASK1	(0xB1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define REG_VDP_TTX_FILTER_1_MASK2	(0xB2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define REG_VDP_TTX_FILTER_1_MASK3	(0xB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define REG_VDP_TTX_FILTER_1_MASK4	(0xB4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define REG_VDP_TTX_FILTER_1_MASK5	(0xB5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define REG_VDP_TTX_FILTER_2_MASK1	(0xB6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define REG_VDP_TTX_FILTER_2_MASK2	(0xB7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define REG_VDP_TTX_FILTER_2_MASK3	(0xB8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define REG_VDP_TTX_FILTER_2_MASK4	(0xB9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define REG_VDP_TTX_FILTER_2_MASK5	(0xBA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define REG_VDP_TTX_FILTER_CONTROL	(0xBB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define REG_VDP_FIFO_WORD_COUNT		(0xBC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define REG_VDP_FIFO_INTERRUPT_THRLD	(0xBD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* 0xBE Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define REG_VDP_FIFO_RESET		(0xBF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define REG_VDP_FIFO_OUTPUT_CONTROL	(0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define REG_VDP_LINE_NUMBER_INTERRUPT	(0xC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define REG_VDP_PIXEL_ALIGNMENT_LSB	(0xC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define REG_VDP_PIXEL_ALIGNMENT_MSB	(0xC3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* 0xC4 - 0xD5 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define REG_VDP_LINE_START		(0xD6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define REG_VDP_LINE_STOP		(0xD7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define REG_VDP_GLOBAL_LINE_MODE	(0xD8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define REG_VDP_FULL_FIELD_ENABLE	(0xD9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define REG_VDP_FULL_FIELD_MODE		(0xDA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* 0xDB - 0xDF Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR	(0xE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR	(0xE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define REG_FIFO_READ_DATA			(0xE2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* 0xE3 - 0xE7 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define REG_VBUS_ADDRESS_ACCESS1	(0xE8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define REG_VBUS_ADDRESS_ACCESS2	(0xE9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define REG_VBUS_ADDRESS_ACCESS3	(0xEA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* 0xEB - 0xEF Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define REG_INTERRUPT_RAW_STATUS0	(0xF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define REG_INTERRUPT_RAW_STATUS1	(0xF1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define REG_INTERRUPT_STATUS0		(0xF2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define REG_INTERRUPT_STATUS1		(0xF3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define REG_INTERRUPT_MASK0		(0xF4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define REG_INTERRUPT_MASK1		(0xF5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define REG_INTERRUPT_CLEAR0		(0xF6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define REG_INTERRUPT_CLEAR1		(0xF7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* 0xF8 - 0xFF Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  * Mask and bit definitions of TVP5146/47 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* The ID values we are looking for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TVP514X_CHIP_ID_MSB		(0x51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TVP5146_CHIP_ID_LSB		(0x46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TVP5147_CHIP_ID_LSB		(0x47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define VIDEO_STD_MASK			(0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define VIDEO_STD_AUTO_SWITCH_BIT	(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define VIDEO_STD_NTSC_MJ_BIT		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define VIDEO_STD_PAL_BDGHIN_BIT	(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define VIDEO_STD_PAL_M_BIT		(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define VIDEO_STD_PAL_COMBINATION_N_BIT	(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define VIDEO_STD_NTSC_4_43_BIT		(0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define VIDEO_STD_SECAM_BIT		(0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define VIDEO_STD_PAL_60_BIT		(0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  * Status bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define STATUS_TV_VCR_BIT		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define STATUS_HORZ_SYNC_LOCK_BIT	(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define STATUS_VIRT_SYNC_LOCK_BIT	(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define STATUS_CLR_SUBCAR_LOCK_BIT	(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define STATUS_LOST_LOCK_DETECT_BIT	(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define STATUS_FEILD_RATE_BIT		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define STATUS_LINE_ALTERNATING_BIT	(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define STATUS_PEAK_WHITE_DETECT_BIT	(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Tokens for register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TOK_WRITE                       (0)     /* token for write operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TOK_TERM                        (1)     /* terminating token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TOK_DELAY                       (2)     /* delay token for reg list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TOK_SKIP                        (3)     /* token to skip a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  * struct tvp514x_reg - Structure for TVP5146/47 register initialization values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  * @token - Token: TOK_WRITE, TOK_TERM etc..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  * @reg - Register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  * @val - Register Value for TOK_WRITE or delay in ms for TOK_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct tvp514x_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	u8 token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif				/* ifndef _TVP514X_REGS_H */