^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for simple i2c audio chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2000 Gerd Knorr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * based on code by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Eric Sandeen (eric_sandeen@bigfoot.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Steve VanDeBogart (vandebo@uclink.berkeley.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Greg Alexander (galexand@acm.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * For the TDA9875 part:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2000 Guillaume Delvit based on Gerd Knorr source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * and Eric Sandeen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright(c) 2005-2008 Mauro Carvalho Chehab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - Some cleanups, code fixes, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * - Convert it to V4L2 API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * This code is placed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OPTIONS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * debug - set to 1 if you'd like to see debug messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/freezer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <media/i2c/tvaudio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* insmod args */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int debug; /* insmod parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UNSET (-1U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* our structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MAXREGS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct CHIPSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) typedef int (*getvalue)(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) typedef int (*checkit)(struct CHIPSTATE*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) typedef int (*initialize)(struct CHIPSTATE*);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) typedef int (*getrxsubchans)(struct CHIPSTATE *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) typedef void (*setaudmode)(struct CHIPSTATE*, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* i2c command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) typedef struct AUDIOCMD {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int count; /* # of bytes to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned char bytes[MAXREGS+1]; /* addr, data, data, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) } audiocmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* chip description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct CHIPDESC {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) char *name; /* chip name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int addr_lo, addr_hi; /* i2c address range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int registers; /* # of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int *insmodopt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) checkit checkit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) initialize initialize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CHIP_HAS_VOLUME 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CHIP_HAS_BASSTREBLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CHIP_HAS_INPUTSEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CHIP_NEED_CHECKMODE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* various i2c command sequences */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) audiocmd init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* which register has which value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int leftreg, rightreg, treblereg, bassreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* initialize with (defaults to 65535/32768/32768 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int volinit, trebleinit, bassinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* functions to convert the values (v4l -> chip) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) getvalue volfunc, treblefunc, bassfunc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* get/set mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) getrxsubchans getrxsubchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) setaudmode setaudmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* input switch register + values for v4l inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int inputreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int inputmap[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int inputmute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int inputmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* current state of the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct CHIPSTATE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* volume/balance cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_ctrl *volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_ctrl *balance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* chip-specific description - should point to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) an entry at CHIPDESC table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct CHIPDESC *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* shadow register set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) audiocmd shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* current settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 muted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int prevmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int radio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct task_struct *thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct timer_list wt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int audmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline struct CHIPSTATE *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return container_of(sd, struct CHIPSTATE, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return &container_of(ctrl->handler, struct CHIPSTATE, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* i2c I/O functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct i2c_client *c = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned char buffer[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (subaddr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) chip->shadow.bytes[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) buffer[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rc = i2c_master_send(c, buffer, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (rc != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) v4l2_warn(sd, "I/O error (write 0x%x)\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) v4l2_info(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "Tried to access a non-existent register: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) subaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) v4l2_dbg(1, debug, sd, "chip_write: reg%d=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) subaddr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) chip->shadow.bytes[subaddr+1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) buffer[0] = subaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) buffer[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) rc = i2c_master_send(c, buffer, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (rc != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) v4l2_warn(sd, "I/O error (write reg%d=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) subaddr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int chip_write_masked(struct CHIPSTATE *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int subaddr, int val, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (mask != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (subaddr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) v4l2_info(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "Tried to access a non-existent register: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) subaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return chip_write(chip, subaddr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int chip_read(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct i2c_client *c = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned char buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rc = i2c_master_recv(c, &buffer, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (rc != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) v4l2_warn(sd, "I/O error (read)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) v4l2_dbg(1, debug, sd, "chip_read: 0x%x\n", buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int chip_read2(struct CHIPSTATE *chip, int subaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct i2c_client *c = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned char write[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned char read[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct i2c_msg msgs[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .addr = c->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .buf = write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .addr = c->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .buf = read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) write[0] = subaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) rc = i2c_transfer(c->adapter, msgs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (rc != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) v4l2_warn(sd, "I/O error (read2)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) v4l2_dbg(1, debug, sd, "chip_read2: reg%d=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) subaddr, read[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return read[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct i2c_client *c = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (0 == cmd->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) v4l2_info(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "Tried to access a non-existent register range: %d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cmd->bytes[0] + 1, cmd->bytes[0] + cmd->count - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* FIXME: it seems that the shadow bytes are wrong below !*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* update our shadow register set; print bytes if (debug > 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) v4l2_dbg(1, debug, sd, "chip_cmd(%s): reg=%d, data:",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) name, cmd->bytes[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for (i = 1; i < cmd->count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) printk(KERN_CONT " 0x%x", cmd->bytes[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) printk(KERN_CONT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* send data to the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) rc = i2c_master_send(c, cmd->bytes, cmd->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (rc != cmd->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) v4l2_warn(sd, "I/O error (%s)\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* kernel thread for doing i2c stuff asyncronly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * right now it is used only to check the audio mode (mono/stereo/whatever)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * some time after switching to another TV channel, then turn on stereo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * if available, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void chip_thread_wake(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct CHIPSTATE *chip = from_timer(chip, t, wt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) wake_up_process(chip->thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int chip_thread(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct CHIPSTATE *chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct CHIPDESC *desc = chip->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int mode, selected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) v4l2_dbg(1, debug, sd, "thread started\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) set_freezable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!kthread_should_stop())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) set_current_state(TASK_RUNNING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) try_to_freeze();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (kthread_should_stop())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) v4l2_dbg(1, debug, sd, "thread wakeup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* don't do anything for radio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (chip->radio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* have a look what's going on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mode = desc->getrxsubchans(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (mode == chip->prevmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* chip detected a new audio mode - set it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) v4l2_dbg(1, debug, sd, "thread checkmode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) chip->prevmode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) selected = V4L2_TUNER_MODE_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) switch (chip->audmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case V4L2_TUNER_MODE_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (mode & V4L2_TUNER_SUB_LANG1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) selected = V4L2_TUNER_MODE_LANG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case V4L2_TUNER_MODE_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case V4L2_TUNER_MODE_LANG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (mode & V4L2_TUNER_SUB_LANG1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) selected = V4L2_TUNER_MODE_LANG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) else if (mode & V4L2_TUNER_SUB_STEREO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) selected = V4L2_TUNER_MODE_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case V4L2_TUNER_MODE_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (mode & V4L2_TUNER_SUB_LANG2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) selected = V4L2_TUNER_MODE_LANG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else if (mode & V4L2_TUNER_SUB_STEREO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) selected = V4L2_TUNER_MODE_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case V4L2_TUNER_MODE_LANG1_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (mode & V4L2_TUNER_SUB_LANG2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) selected = V4L2_TUNER_MODE_LANG1_LANG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) else if (mode & V4L2_TUNER_SUB_STEREO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) selected = V4L2_TUNER_MODE_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) desc->setaudmode(chip, selected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* schedule next check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) v4l2_dbg(1, debug, sd, "thread exiting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* audio chip descriptions - defines+functions for tda9840 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define TDA9840_SW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TDA9840_LVADJ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define TDA9840_STADJ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define TDA9840_TEST 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define TDA9840_MONO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define TDA9840_STEREO 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define TDA9840_DUALA 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define TDA9840_DUALB 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TDA9840_DUALAB 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TDA9840_DUALBA 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define TDA9840_EXTERNAL 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define TDA9840_DS_DUAL 0x20 /* Dual sound identified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define TDA9840_ST_STEREO 0x40 /* Stereo sound identified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define TDA9840_PONRES 0x80 /* Power-on reset detected if = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define TDA9840_TEST_INT1SN 0x1 /* Integration time 0.5s when set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define TDA9840_TEST_INTFU 0x02 /* Disables integrator function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int tda9840_getrxsubchans(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int val, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mode = V4L2_TUNER_SUB_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) val = chip_read(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (val & TDA9840_DS_DUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (val & TDA9840_ST_STEREO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mode = V4L2_TUNER_SUB_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "tda9840_getrxsubchans(): raw chip read: %d, return: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) val, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void tda9840_setaudmode(struct CHIPSTATE *chip, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int update = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case V4L2_TUNER_MODE_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) t |= TDA9840_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case V4L2_TUNER_MODE_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) t |= TDA9840_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case V4L2_TUNER_MODE_LANG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) t |= TDA9840_DUALA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case V4L2_TUNER_MODE_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) t |= TDA9840_DUALB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case V4L2_TUNER_MODE_LANG1_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) t |= TDA9840_DUALAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) update = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) chip_write(chip, TDA9840_SW, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int tda9840_checkit(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) rc = chip_read(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* lower 5 bits should be 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return ((rc & 0x1f) == 0) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* audio chip descriptions - defines+functions for tda985x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* subaddresses for TDA9855 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define TDA9855_VR 0x00 /* Volume, right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define TDA9855_VL 0x01 /* Volume, left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define TDA9855_BA 0x02 /* Bass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define TDA9855_TR 0x03 /* Treble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define TDA9855_SW 0x04 /* Subwoofer - not connected on DTV2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* subaddresses for TDA9850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define TDA9850_C4 0x04 /* Control 1 for TDA9850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* subaddesses for both chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define TDA985x_C5 0x05 /* Control 2 for TDA9850, Control 1 for TDA9855 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define TDA985x_C6 0x06 /* Control 3 for TDA9850, Control 2 for TDA9855 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define TDA985x_C7 0x07 /* Control 4 for TDA9850, Control 3 for TDA9855 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define TDA985x_A1 0x08 /* Alignment 1 for both chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define TDA985x_A2 0x09 /* Alignment 2 for both chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define TDA985x_A3 0x0a /* Alignment 3 for both chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Masks for bits in TDA9855 subaddresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* 0x00 - VR in TDA9855 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* 0x01 - VL in TDA9855 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* lower 7 bits control gain from -71dB (0x28) to 16dB (0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * in 1dB steps - mute is 0x27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* 0x02 - BA in TDA9855 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* lower 5 bits control bass gain from -12dB (0x06) to 16.5dB (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * in .5dB steps - 0 is 0x0E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* 0x03 - TR in TDA9855 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* 4 bits << 1 control treble gain from -12dB (0x3) to 12dB (0xb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * in 3dB steps - 0 is 0x7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Masks for bits in both chips' subaddresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* 0x04 - SW in TDA9855, C4/Control 1 in TDA9850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Unique to TDA9855: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* 4 bits << 2 control subwoofer/surround gain from -14db (0x1) to 14db (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * in 3dB steps - mute is 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Unique to TDA9850: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* lower 4 bits control stereo noise threshold, over which stereo turns off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * set to values of 0x00 through 0x0f for Ster1 through Ster16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* 0x05 - C5 - Control 1 in TDA9855 , Control 2 in TDA9850*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Unique to TDA9855: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define TDA9855_MUTE 1<<7 /* GMU, Mute at outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define TDA9855_AVL 1<<6 /* AVL, Automatic Volume Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define TDA9855_LOUD 1<<5 /* Loudness, 1==off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define TDA9855_SUR 1<<3 /* Surround / Subwoofer 1==.5(L-R) 0==.5(L+R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Bits 0 to 3 select various combinations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * of line in and line out, only the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * interesting ones are defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define TDA9855_EXT 1<<2 /* Selects inputs LIR and LIL. Pins 41 & 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define TDA9855_INT 0 /* Selects inputs LOR and LOL. (internal) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Unique to TDA9850: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* lower 4 bits control SAP noise threshold, over which SAP turns off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * set to values of 0x00 through 0x0f for SAP1 through SAP16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* 0x06 - C6 - Control 2 in TDA9855, Control 3 in TDA9850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Common to TDA9855 and TDA9850: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define TDA985x_SAP 3<<6 /* Selects SAP output, mute if not received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define TDA985x_MONOSAP 2<<6 /* Selects Mono on left, SAP on right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define TDA985x_STEREO 1<<6 /* Selects Stereo output, mono if not received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define TDA985x_MONO 0 /* Forces Mono output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define TDA985x_LMU 1<<3 /* Mute (LOR/LOL for 9855, OUTL/OUTR for 9850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Unique to TDA9855: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define TDA9855_TZCM 1<<5 /* If set, don't mute till zero crossing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define TDA9855_VZCM 1<<4 /* If set, don't change volume till zero crossing*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define TDA9855_LINEAR 0 /* Linear Stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define TDA9855_PSEUDO 1 /* Pseudo Stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define TDA9855_SPAT_30 2 /* Spatial Stereo, 30% anti-phase crosstalk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define TDA9855_SPAT_50 3 /* Spatial Stereo, 52% anti-phase crosstalk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define TDA9855_E_MONO 7 /* Forced mono - mono select elseware, so useless*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* 0x07 - C7 - Control 3 in TDA9855, Control 4 in TDA9850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Common to both TDA9855 and TDA9850: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* lower 4 bits control input gain from -3.5dB (0x0) to 4dB (0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * in .5dB steps - 0dB is 0x7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* 0x08, 0x09 - A1 and A2 (read/write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Common to both TDA9855 and TDA9850: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* lower 5 bites are wideband and spectral expander alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * from 0x00 to 0x1f - nominal at 0x0f and 0x10 (read/write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define TDA985x_STP 1<<5 /* Stereo Pilot/detect (read-only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define TDA985x_SAPP 1<<6 /* SAP Pilot/detect (read-only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define TDA985x_STS 1<<7 /* Stereo trigger 1= <35mV 0= <30mV (write-only)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* 0x0a - A3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Common to both TDA9855 and TDA9850: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* lower 3 bits control timing current for alignment: -30% (0x0), -20% (0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * -10% (0x2), nominal (0x3), +10% (0x6), +20% (0x5), +30% (0x4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define TDA985x_ADJ 1<<7 /* Stereo adjust on/off (wideband and spectral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int tda9855_volume(int val) { return val/0x2e8+0x27; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int tda9855_bass(int val) { return val/0xccc+0x06; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int tda985x_getrxsubchans(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int mode, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Add mono mode regardless of SAP and stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Allows forced mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mode = V4L2_TUNER_SUB_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) val = chip_read(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (val & TDA985x_STP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mode = V4L2_TUNER_SUB_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (val & TDA985x_SAPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mode |= V4L2_TUNER_SUB_SAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static void tda985x_setaudmode(struct CHIPSTATE *chip, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int update = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case V4L2_TUNER_MODE_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) c6 |= TDA985x_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case V4L2_TUNER_MODE_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case V4L2_TUNER_MODE_LANG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) c6 |= TDA985x_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) case V4L2_TUNER_MODE_SAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) c6 |= TDA985x_SAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case V4L2_TUNER_MODE_LANG1_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) c6 |= TDA985x_MONOSAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) update = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) chip_write(chip,TDA985x_C6,c6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* audio chip descriptions - defines+functions for tda9873h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Subaddresses for TDA9873H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define TDA9873_SW 0x00 /* Switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define TDA9873_AD 0x01 /* Adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define TDA9873_PT 0x02 /* Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Subaddress 0x00: Switching Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * B7..B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * B1, B0: Input source selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * 0, 0 internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * 1, 0 external stereo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * 0, 1 external mono
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define TDA9873_INP_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define TDA9873_INTERNAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define TDA9873_EXT_STEREO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define TDA9873_EXT_MONO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* B3, B2: output signal select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * B4 : transmission mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * 0, 0, 1 Mono
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * 1, 0, 0 Stereo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * 1, 1, 1 Stereo (reversed channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * 0, 0, 0 Dual AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * 0, 0, 1 Dual AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * 0, 1, 0 Dual BB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * 0, 1, 1 Dual BA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define TDA9873_TR_MASK (7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define TDA9873_TR_MONO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define TDA9873_TR_STEREO 1 << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define TDA9873_TR_REVERSE ((1 << 3) | (1 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define TDA9873_TR_DUALA 1 << 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define TDA9873_TR_DUALB 1 << 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define TDA9873_TR_DUALAB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* output level controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * B5: output level switch (0 = reduced gain, 1 = normal gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * B6: mute (1 = muted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * B7: auto-mute (1 = auto-mute enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define TDA9873_GAIN_NORMAL 1 << 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define TDA9873_MUTE 1 << 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define TDA9873_AUTOMUTE 1 << 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Subaddress 0x01: Adjust/standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* Lower 4 bits (C3..C0) control stereo adjustment on R channel (-0.6 - +0.7 dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * Recommended value is +0 dB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define TDA9873_STEREO_ADJ 0x06 /* 0dB gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Bits C6..C4 control FM stantard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * C6, C5, C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * 0, 0, 0 B/G (PAL FM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * 0, 0, 1 M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * 0, 1, 0 D/K(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * 0, 1, 1 D/K(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * 1, 0, 0 D/K(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * 1, 0, 1 I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define TDA9873_BG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define TDA9873_M 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define TDA9873_DK1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define TDA9873_DK2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define TDA9873_DK3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define TDA9873_I 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* C7 controls identification response time (1=fast/0=normal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define TDA9873_IDR_NORM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define TDA9873_IDR_FAST 1 << 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Subaddress 0x02: Port data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* E1, E0 free programmable ports P1/P2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 0, 0 both ports low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 0, 1 P1 high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 1, 0 P2 high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 1, 1 both ports high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define TDA9873_PORTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* E2: test port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define TDA9873_TST_PORT 1 << 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* E5..E3 control mono output channel (together with transmission mode bit B4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * E5 E4 E3 B4 OUTM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * 0 0 0 0 mono
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * 0 0 1 0 DUAL B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * 0 1 0 1 mono (from stereo decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define TDA9873_MOUT_MONO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define TDA9873_MOUT_FMONO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define TDA9873_MOUT_DUALA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define TDA9873_MOUT_DUALB 1 << 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define TDA9873_MOUT_ST 1 << 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define TDA9873_MOUT_EXTM ((1 << 4) | (1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define TDA9873_MOUT_EXTL 1 << 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define TDA9873_MOUT_EXTR ((1 << 5) | (1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define TDA9873_MOUT_EXTLR ((1 << 5) | (1 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define TDA9873_MOUT_MUTE ((1 << 5) | (1 << 4) | (1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Status bits: (chip read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define TDA9873_PONR 0 /* Power-on reset detected if = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define TDA9873_STEREO 2 /* Stereo sound is identified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define TDA9873_DUAL 4 /* Dual sound is identified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int tda9873_getrxsubchans(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int val,mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mode = V4L2_TUNER_SUB_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) val = chip_read(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (val & TDA9873_STEREO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mode = V4L2_TUNER_SUB_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (val & TDA9873_DUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "tda9873_getrxsubchans(): raw chip read: %d, return: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) val, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void tda9873_setaudmode(struct CHIPSTATE *chip, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* int adj_data = chip->shadow.bytes[TDA9873_AD+1] ; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "tda9873_setaudmode(): external input\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "tda9873_setaudmode(): chip->shadow.bytes[%d] = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) v4l2_dbg(1, debug, sd, "tda9873_setaudmode(): sw_data = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) sw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case V4L2_TUNER_MODE_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) sw_data |= TDA9873_TR_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) case V4L2_TUNER_MODE_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) sw_data |= TDA9873_TR_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case V4L2_TUNER_MODE_LANG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) sw_data |= TDA9873_TR_DUALA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) case V4L2_TUNER_MODE_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) sw_data |= TDA9873_TR_DUALB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case V4L2_TUNER_MODE_LANG1_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) sw_data |= TDA9873_TR_DUALAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) chip_write(chip, TDA9873_SW, sw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "tda9873_setaudmode(): req. mode %d; chip_write: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) mode, sw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int tda9873_checkit(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) rc = chip_read2(chip, 254);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return (rc & ~0x1f) == 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* audio chip description - defines+functions for tda9874h and tda9874a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Dariusz Kowalewski <darekk@automex.pl> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Subaddresses for TDA9874H and TDA9874A (slave rx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define TDA9874A_AGCGR 0x00 /* AGC gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define TDA9874A_GCONR 0x01 /* general config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define TDA9874A_MSR 0x02 /* monitor select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define TDA9874A_C1FRA 0x03 /* carrier 1 freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define TDA9874A_C1FRB 0x04 /* carrier 1 freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define TDA9874A_C1FRC 0x05 /* carrier 1 freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define TDA9874A_C2FRA 0x06 /* carrier 2 freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define TDA9874A_C2FRB 0x07 /* carrier 2 freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define TDA9874A_C2FRC 0x08 /* carrier 2 freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define TDA9874A_DCR 0x09 /* demodulator config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define TDA9874A_FMER 0x0a /* FM de-emphasis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define TDA9874A_FMMR 0x0b /* FM dematrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define TDA9874A_C1OLAR 0x0c /* ch.1 output level adj. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define TDA9874A_C2OLAR 0x0d /* ch.2 output level adj. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define TDA9874A_NCONR 0x0e /* NICAM config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define TDA9874A_NOLAR 0x0f /* NICAM output level adj. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define TDA9874A_NLELR 0x10 /* NICAM lower error limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define TDA9874A_NUELR 0x11 /* NICAM upper error limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define TDA9874A_AMCONR 0x12 /* audio mute control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define TDA9874A_SDACOSR 0x13 /* stereo DAC output select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define TDA9874A_AOSR 0x14 /* analog output select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define TDA9874A_DAICONR 0x15 /* digital audio interface config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define TDA9874A_I2SOSR 0x16 /* I2S-bus output select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define TDA9874A_I2SOLAR 0x17 /* I2S-bus output level adj. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define TDA9874A_MDACOSR 0x18 /* mono DAC output select (tda9874a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define TDA9874A_ESP 0xFF /* easy standard progr. (tda9874a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Subaddresses for TDA9874H and TDA9874A (slave tx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define TDA9874A_DSR 0x00 /* device status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define TDA9874A_NSR 0x01 /* NICAM status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define TDA9874A_NECR 0x02 /* NICAM error count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define TDA9874A_DR1 0x03 /* add. data LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define TDA9874A_DR2 0x04 /* add. data MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define TDA9874A_LLRA 0x05 /* monitor level read-out LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define TDA9874A_LLRB 0x06 /* monitor level read-out MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define TDA9874A_SIFLR 0x07 /* SIF level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define TDA9874A_TR2 252 /* test reg. 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define TDA9874A_TR1 253 /* test reg. 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define TDA9874A_DIC 254 /* device id. code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define TDA9874A_SIC 255 /* software id. code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int tda9874a_mode = 1; /* 0: A2, 1: NICAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int tda9874a_GCONR = 0xc0; /* default config. input pin: SIFSEL=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int tda9874a_NCONR = 0x01; /* default NICAM config.: AMSEL=0,AMUTE=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int tda9874a_ESP = 0x07; /* default standard: NICAM D/K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static int tda9874a_dic = -1; /* device id. code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* insmod options for tda9874a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static unsigned int tda9874a_SIF = UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static unsigned int tda9874a_AMSEL = UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static unsigned int tda9874a_STD = UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) module_param(tda9874a_SIF, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) module_param(tda9874a_AMSEL, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) module_param(tda9874a_STD, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * initialization table for tda9874 decoder:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * - carrier 1 freq. registers (3 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * - carrier 2 freq. registers (3 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * - demudulator config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * - FM de-emphasis register (slow identification mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * Note: frequency registers must be written in single i2c transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static struct tda9874a_MODES {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) audiocmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) } tda9874a_modelist[9] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) { "A2, B/G", /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) { "A2, M (Korea)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) { "A2, D/K (1)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) { "A2, D/K (2)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) { "A2, D/K (3)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) { "NICAM, I",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) { "NICAM, B/G",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) { "NICAM, D/K",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) { "NICAM, L",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int tda9874a_setup(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) chip_write(chip, TDA9874A_AGCGR, 0x00); /* 0 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if(tda9874a_dic == 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) chip_write(chip, TDA9874A_FMMR, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) } else { /* dic == 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) chip_write(chip, TDA9874A_FMMR, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) chip_write(chip, TDA9874A_C1OLAR, 0x00); /* 0 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) chip_write(chip, TDA9874A_C2OLAR, 0x00); /* 0 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) chip_write(chip, TDA9874A_NOLAR, 0x00); /* 0 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Note: If signal quality is poor you may want to change NICAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* error limit registers (NLELR and NUELR) to some greater values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* Then the sound would remain stereo, but won't be so clear. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) chip_write(chip, TDA9874A_NLELR, 0x14); /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) chip_write(chip, TDA9874A_NUELR, 0x50); /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if(tda9874a_dic == 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) chip_write(chip, TDA9874A_AMCONR, 0xf9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) chip_write(chip, TDA9874A_AOSR, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) } else { /* dic == 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) chip_write(chip, TDA9874A_AMCONR, 0xfb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) chip_write(chip, TDA9874A_AOSR, 0x00); /* or 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) v4l2_dbg(1, debug, sd, "tda9874a_setup(): %s [0x%02X].\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static int tda9874a_getrxsubchans(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int dsr,nsr,mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int necr; /* just for debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) mode = V4L2_TUNER_SUB_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dsr = chip_read2(chip, TDA9874A_DSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (dsr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) nsr = chip_read2(chip, TDA9874A_NSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (nsr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) necr = chip_read2(chip, TDA9874A_NECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (necr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* need to store dsr/nsr somewhere */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) chip->shadow.bytes[MAXREGS-2] = dsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) chip->shadow.bytes[MAXREGS-1] = nsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if(tda9874a_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Note: DSR.RSSF and DSR.AMSTAT bits are also checked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * If NICAM auto-muting is enabled, DSR.AMSTAT=1 indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * that sound has (temporarily) switched from NICAM to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * mono FM (or AM) on 1st sound carrier due to high NICAM bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * error count. So in fact there is no stereo in this case :-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * But changing the mode to V4L2_TUNER_MODE_MONO would switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * external 4052 multiplexer in audio_hook().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if(nsr & 0x02) /* NSR.S/MB=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mode = V4L2_TUNER_SUB_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if(nsr & 0x01) /* NSR.D/SB=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if(dsr & 0x02) /* DSR.IDSTE=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) mode = V4L2_TUNER_SUB_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if(dsr & 0x04) /* DSR.IDDUA=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "tda9874a_getrxsubchans(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dsr, nsr, necr, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static void tda9874a_setaudmode(struct CHIPSTATE *chip, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* If auto-muting is disabled, we can hear a signal of degrading quality. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (tda9874a_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) tda9874a_NCONR &= 0xfe; /* enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) tda9874a_NCONR |= 0x01; /* disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* Note: TDA9874A supports automatic FM dematrixing (FMMR register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * and has auto-select function for audio output (AOSR register).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * Old TDA9874H doesn't support these features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * TDA9874A also has additional mono output pin (OUTM), which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * on same (all?) tv-cards is not used, anyway (as well as MONOIN).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if(tda9874a_dic == 0x11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) int aosr = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int mdacosr = (tda9874a_mode) ? 0x82:0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) switch(mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) case V4L2_TUNER_MODE_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case V4L2_TUNER_MODE_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case V4L2_TUNER_MODE_LANG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) aosr = 0x80; /* auto-select, dual A/A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) mdacosr = (tda9874a_mode) ? 0x82:0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) case V4L2_TUNER_MODE_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) aosr = 0xa0; /* auto-select, dual B/B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) mdacosr = (tda9874a_mode) ? 0x83:0x81;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) case V4L2_TUNER_MODE_LANG1_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) aosr = 0x00; /* always route L to L and R to R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) mdacosr = (tda9874a_mode) ? 0x82:0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) chip_write(chip, TDA9874A_AOSR, aosr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) chip_write(chip, TDA9874A_MDACOSR, mdacosr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) "tda9874a_setaudmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) mode, aosr, mdacosr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) } else { /* dic == 0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int fmmr,aosr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) switch(mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) case V4L2_TUNER_MODE_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) fmmr = 0x00; /* mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) aosr = 0x10; /* A/A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) case V4L2_TUNER_MODE_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if(tda9874a_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) fmmr = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) aosr = 0x00; /* handled by NICAM auto-mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04; /* stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) aosr = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) case V4L2_TUNER_MODE_LANG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) fmmr = 0x02; /* dual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) aosr = 0x10; /* dual A/A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case V4L2_TUNER_MODE_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) fmmr = 0x02; /* dual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) aosr = 0x20; /* dual B/B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) case V4L2_TUNER_MODE_LANG1_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) fmmr = 0x02; /* dual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) aosr = 0x00; /* dual A/B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) chip_write(chip, TDA9874A_FMMR, fmmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) chip_write(chip, TDA9874A_AOSR, aosr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "tda9874a_setaudmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) mode, fmmr, aosr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static int tda9874a_checkit(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) int dic,sic; /* device id. and software id. codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dic = chip_read2(chip, TDA9874A_DIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (dic < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) sic = chip_read2(chip, TDA9874A_SIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (sic < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) v4l2_dbg(1, debug, sd, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if((dic == 0x11)||(dic == 0x07)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) v4l2_info(sd, "found tda9874%s.\n", (dic == 0x11) ? "a" : "h");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) tda9874a_dic = dic; /* remember device id. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return 0; /* not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int tda9874a_initialize(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (tda9874a_SIF > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) tda9874a_SIF = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) tda9874a_STD = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if(tda9874a_AMSEL > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) tda9874a_AMSEL = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if(tda9874a_SIF == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) tda9874a_GCONR = 0xc0; /* sound IF input 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) tda9874a_GCONR = 0xc1; /* sound IF input 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) tda9874a_ESP = tda9874a_STD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if(tda9874a_AMSEL == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) tda9874a_NCONR = 0x01; /* auto-mute: analog mono input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) tda9874a_NCONR = 0x05; /* auto-mute: 1st carrier FM or AM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) tda9874a_setup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* audio chip description - defines+functions for tda9875 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* The TDA9875 is made by Philips Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * http://www.semiconductors.philips.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * TDA9875: I2C-bus controlled DSP audio processor, FM demodulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* subaddresses for TDA9875 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define TDA9875_MUT 0x12 /*General mute (value --> 0b11001100*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define TDA9875_CFG 0x01 /* Config register (value --> 0b00000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define TDA9875_DACOS 0x13 /*DAC i/o select (ADC) 0b0000100*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define TDA9875_LOSR 0x16 /*Line output select regirter 0b0100 0001*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define TDA9875_CH1V 0x0c /*Channel 1 volume (mute)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define TDA9875_CH2V 0x0d /*Channel 2 volume (mute)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define TDA9875_SC1 0x14 /*SCART 1 in (mono)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define TDA9875_SC2 0x15 /*SCART 2 in (mono)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define TDA9875_ADCIS 0x17 /*ADC input select (mono) 0b0110 000*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define TDA9875_AER 0x19 /*Audio effect (AVL+Pseudo) 0b0000 0110*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define TDA9875_MCS 0x18 /*Main channel select (DAC) 0b0000100*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define TDA9875_MVL 0x1a /* Main volume gauche */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define TDA9875_MVR 0x1b /* Main volume droite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define TDA9875_MBA 0x1d /* Main Basse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define TDA9875_MTR 0x1e /* Main treble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define TDA9875_ACS 0x1f /* Auxiliary channel select (FM) 0b0000000*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define TDA9875_AVL 0x20 /* Auxiliary volume gauche */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define TDA9875_AVR 0x21 /* Auxiliary volume droite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define TDA9875_ABA 0x22 /* Auxiliary Basse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define TDA9875_ATR 0x23 /* Auxiliary treble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define TDA9875_MSR 0x02 /* Monitor select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define TDA9875_C1MSB 0x03 /* Carrier 1 (FM) frequency register MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define TDA9875_C1MIB 0x04 /* Carrier 1 (FM) frequency register (16-8]b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define TDA9875_C1LSB 0x05 /* Carrier 1 (FM) frequency register LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define TDA9875_C2MSB 0x06 /* Carrier 2 (nicam) frequency register MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define TDA9875_C2MIB 0x07 /* Carrier 2 (nicam) frequency register (16-8]b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define TDA9875_C2LSB 0x08 /* Carrier 2 (nicam) frequency register LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define TDA9875_DCR 0x09 /* Demodulateur configuration regirter*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define TDA9875_DEEM 0x0a /* FM de-emphasis regirter*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define TDA9875_FMAT 0x0b /* FM Matrix regirter*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define TDA9875_MUTE_ON 0xff /* general mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define TDA9875_MUTE_OFF 0xcc /* general no mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static int tda9875_initialize(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) chip_write(chip, TDA9875_CFG, 0xd0); /*reg de config 0 (reset)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) chip_write(chip, TDA9875_MSR, 0x03); /* Monitor 0b00000XXX*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) chip_write(chip, TDA9875_C1MSB, 0x00); /*Car1(FM) MSB XMHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) chip_write(chip, TDA9875_C1MIB, 0x00); /*Car1(FM) MIB XMHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) chip_write(chip, TDA9875_C1LSB, 0x00); /*Car1(FM) LSB XMHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) chip_write(chip, TDA9875_C2MSB, 0x00); /*Car2(NICAM) MSB XMHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) chip_write(chip, TDA9875_C2MIB, 0x00); /*Car2(NICAM) MIB XMHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) chip_write(chip, TDA9875_C2LSB, 0x00); /*Car2(NICAM) LSB XMHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) chip_write(chip, TDA9875_DCR, 0x00); /*Demod config 0x00*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) chip_write(chip, TDA9875_DEEM, 0x44); /*DE-Emph 0b0100 0100*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) chip_write(chip, TDA9875_FMAT, 0x00); /*FM Matrix reg 0x00*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) chip_write(chip, TDA9875_SC1, 0x00); /* SCART 1 (SC1)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) chip_write(chip, TDA9875_SC2, 0x01); /* SCART 2 (sc2)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) chip_write(chip, TDA9875_CH1V, 0x10); /* Channel volume 1 mute*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) chip_write(chip, TDA9875_CH2V, 0x10); /* Channel volume 2 mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) chip_write(chip, TDA9875_DACOS, 0x02); /* sig DAC i/o(in:nicam)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) chip_write(chip, TDA9875_ADCIS, 0x6f); /* sig ADC input(in:mono)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) chip_write(chip, TDA9875_LOSR, 0x00); /* line out (in:mono)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) chip_write(chip, TDA9875_AER, 0x00); /*06 Effect (AVL+PSEUDO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) chip_write(chip, TDA9875_MCS, 0x44); /* Main ch select (DAC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) chip_write(chip, TDA9875_MVL, 0x03); /* Vol Main left 10dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) chip_write(chip, TDA9875_MVR, 0x03); /* Vol Main right 10dB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) chip_write(chip, TDA9875_MBA, 0x00); /* Main Bass Main 0dB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) chip_write(chip, TDA9875_MTR, 0x00); /* Main Treble Main 0dB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) chip_write(chip, TDA9875_ACS, 0x44); /* Aux chan select (dac)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) chip_write(chip, TDA9875_AVL, 0x00); /* Vol Aux left 0dB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) chip_write(chip, TDA9875_AVR, 0x00); /* Vol Aux right 0dB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) chip_write(chip, TDA9875_ABA, 0x00); /* Aux Bass Main 0dB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) chip_write(chip, TDA9875_ATR, 0x00); /* Aux Aigus Main 0dB*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) chip_write(chip, TDA9875_MUT, 0xcc); /* General mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static int tda9875_volume(int val) { return (unsigned char)(val / 602 - 84); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static int tda9875_bass(int val) { return (unsigned char)(max(-12, val / 2115 - 15)); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static int tda9875_treble(int val) { return (unsigned char)(val / 2622 - 12); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* *********************** *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * i2c interface functions *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * *********************** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static int tda9875_checkit(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) int dic, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dic = chip_read2(chip, 254);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (dic < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) rev = chip_read2(chip, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (rev < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (dic == 0 || dic == 2) { /* tda9875 and tda9875A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) v4l2_info(sd, "found tda9875%s rev. %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dic == 0 ? "" : "A", rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* audio chip descriptions - defines+functions for tea6420 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define TEA6300_VL 0x00 /* volume left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define TEA6300_VR 0x01 /* volume right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define TEA6300_BA 0x02 /* bass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define TEA6300_TR 0x03 /* treble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define TEA6300_FA 0x04 /* fader control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define TEA6300_S 0x05 /* switch register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* values for those registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define TEA6300_S_SA 0x01 /* stereo A input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define TEA6300_S_SB 0x02 /* stereo B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define TEA6300_S_SC 0x04 /* stereo C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define TEA6300_S_GMU 0x80 /* general mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define TEA6320_V 0x00 /* volume (0-5)/loudness off (6)/zero crossing mute(7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define TEA6320_FFR 0x01 /* fader front right (0-5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define TEA6320_FFL 0x02 /* fader front left (0-5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define TEA6320_FRR 0x03 /* fader rear right (0-5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define TEA6320_FRL 0x04 /* fader rear left (0-5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define TEA6320_BA 0x05 /* bass (0-4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define TEA6320_TR 0x06 /* treble (0-4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define TEA6320_S 0x07 /* switch register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* values for those registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define TEA6320_S_SA 0x07 /* stereo A input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define TEA6320_S_SB 0x06 /* stereo B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define TEA6320_S_SC 0x05 /* stereo C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define TEA6320_S_SD 0x04 /* stereo D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define TEA6320_S_GMU 0x80 /* general mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define TEA6420_S_SA 0x00 /* stereo A input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define TEA6420_S_SB 0x01 /* stereo B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define TEA6420_S_SC 0x02 /* stereo C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define TEA6420_S_SD 0x03 /* stereo D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define TEA6420_S_SE 0x04 /* stereo E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define TEA6420_S_GMU 0x05 /* general mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static int tea6300_shift10(int val) { return val >> 10; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static int tea6300_shift12(int val) { return val >> 12; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* Assumes 16bit input (values 0x3f to 0x0c are unique, values less than */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* 0x0c mirror those immediately higher) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static int tea6320_shift11(int val) { return val >> 11; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static int tea6320_initialize(struct CHIPSTATE * chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) chip_write(chip, TEA6320_FFR, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) chip_write(chip, TEA6320_FFL, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) chip_write(chip, TEA6320_FRR, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) chip_write(chip, TEA6320_FRL, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* audio chip descriptions - defines+functions for tda8425 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define TDA8425_VL 0x00 /* volume left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define TDA8425_VR 0x01 /* volume right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define TDA8425_BA 0x02 /* bass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define TDA8425_TR 0x03 /* treble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define TDA8425_S1 0x08 /* switch functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* values for those registers: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define TDA8425_S1_OFF 0xEE /* audio off (mute on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define TDA8425_S1_CH1 0xCE /* audio channel 1 (mute off) - "linear stereo" mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define TDA8425_S1_CH2 0xCF /* audio channel 2 (mute off) - "linear stereo" mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define TDA8425_S1_MU 0x20 /* mute bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define TDA8425_S1_STEREO 0x18 /* stereo bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define TDA8425_S1_STEREO_SPATIAL 0x18 /* spatial stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define TDA8425_S1_STEREO_LINEAR 0x08 /* linear stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define TDA8425_S1_STEREO_PSEUDO 0x10 /* pseudo stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define TDA8425_S1_STEREO_MONO 0x00 /* forced mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define TDA8425_S1_ML 0x06 /* language selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define TDA8425_S1_ML_SOUND_A 0x02 /* sound a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define TDA8425_S1_ML_SOUND_B 0x04 /* sound b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define TDA8425_S1_ML_STEREO 0x06 /* stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define TDA8425_S1_IS 0x01 /* channel selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static void tda8425_setaudmode(struct CHIPSTATE *chip, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) case V4L2_TUNER_MODE_LANG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) s1 |= TDA8425_S1_ML_SOUND_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) s1 |= TDA8425_S1_STEREO_PSEUDO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) case V4L2_TUNER_MODE_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) s1 |= TDA8425_S1_ML_SOUND_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) s1 |= TDA8425_S1_STEREO_PSEUDO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) case V4L2_TUNER_MODE_LANG1_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) s1 |= TDA8425_S1_ML_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) s1 |= TDA8425_S1_STEREO_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) case V4L2_TUNER_MODE_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) s1 |= TDA8425_S1_ML_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) s1 |= TDA8425_S1_STEREO_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) case V4L2_TUNER_MODE_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) s1 |= TDA8425_S1_ML_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) s1 |= TDA8425_S1_STEREO_SPATIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) chip_write(chip,TDA8425_S1,s1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /* audio chip descriptions - defines+functions for pic16c54 (PV951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* the registers of 16C54, I2C sub address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define PIC16C54_REG_KEY_CODE 0x01 /* Not use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define PIC16C54_REG_MISC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* bit definition of the RESET register, I2C data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define PIC16C54_MISC_RESET_REMOTE_CTL 0x01 /* bit 0, Reset to receive the key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* code of remote controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define PIC16C54_MISC_MTS_MAIN 0x02 /* bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define PIC16C54_MISC_MTS_SAP 0x04 /* bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define PIC16C54_MISC_MTS_BOTH 0x08 /* bit 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define PIC16C54_MISC_SND_MUTE 0x10 /* bit 4, Mute Audio(Line-in and Tuner) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define PIC16C54_MISC_SND_NOTMUTE 0x20 /* bit 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define PIC16C54_MISC_SWITCH_TUNER 0x40 /* bit 6 , Switch to Line-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define PIC16C54_MISC_SWITCH_LINE 0x80 /* bit 7 , Switch to Tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* audio chip descriptions - defines+functions for TA8874Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* write 1st byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define TA8874Z_LED_STE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define TA8874Z_LED_BIL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define TA8874Z_LED_EXT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define TA8874Z_MONO_SET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define TA8874Z_MUTE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define TA8874Z_F_MONO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define TA8874Z_MODE_SUB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define TA8874Z_MODE_MAIN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /* write 2nd byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /*#define TA8874Z_TI 0x80 */ /* test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define TA8874Z_SEPARATION 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define TA8874Z_SEPARATION_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define TA8874Z_B1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define TA8874Z_B0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define TA8874Z_CHAG_FLAG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * B1 B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * mono L H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * stereo L L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * BIL H L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static int ta8874z_getrxsubchans(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) int val, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) mode = V4L2_TUNER_SUB_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) val = chip_read(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (val & TA8874Z_B1){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }else if (!(val & TA8874Z_B0)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) mode = V4L2_TUNER_SUB_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* v4l2_dbg(1, debug, &chip->sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) "ta8874z_getrxsubchans(): raw chip read: 0x%02x, return: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) val, mode); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static audiocmd ta8874z_both = {2, { TA8874Z_MODE_MAIN | TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static void ta8874z_setaudmode(struct CHIPSTATE *chip, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) struct v4l2_subdev *sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) int update = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) audiocmd *t = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) v4l2_dbg(1, debug, sd, "ta8874z_setaudmode(): mode: 0x%02x\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) switch(mode){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) case V4L2_TUNER_MODE_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) t = &ta8874z_mono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) case V4L2_TUNER_MODE_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) t = &ta8874z_stereo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) case V4L2_TUNER_MODE_LANG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) t = &ta8874z_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) case V4L2_TUNER_MODE_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) t = &ta8874z_sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) case V4L2_TUNER_MODE_LANG1_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) t = &ta8874z_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) update = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if(update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) chip_cmd(chip, "TA8874Z", t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static int ta8874z_checkit(struct CHIPSTATE *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) rc = chip_read(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return ((rc & 0x1f) == 0x1f) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* audio chip descriptions - struct CHIPDESC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /* insmod options to enable/disable individual audio chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static int tda8425 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static int tda9840 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static int tda9850 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static int tda9855 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static int tda9873 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static int tda9874a = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static int tda9875 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static int tea6300; /* default 0 - address clash with msp34xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static int tea6320; /* default 0 - address clash with msp34xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static int tea6420 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static int pic16c54 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static int ta8874z; /* default 0 - address clash with tda9840 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) module_param(tda8425, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) module_param(tda9840, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) module_param(tda9850, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) module_param(tda9855, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) module_param(tda9873, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) module_param(tda9874a, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) module_param(tda9875, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) module_param(tea6300, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) module_param(tea6320, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) module_param(tea6420, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) module_param(pic16c54, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) module_param(ta8874z, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static struct CHIPDESC chiplist[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .name = "tda9840",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .insmodopt = &tda9840,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .addr_lo = I2C_ADDR_TDA9840 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .addr_hi = I2C_ADDR_TDA9840 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .registers = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .flags = CHIP_NEED_CHECKMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .checkit = tda9840_checkit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .getrxsubchans = tda9840_getrxsubchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .setaudmode = tda9840_setaudmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /* ,TDA9840_SW, TDA9840_MONO */} }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .name = "tda9873h",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .insmodopt = &tda9873,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .addr_lo = I2C_ADDR_TDA985x_L >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .addr_hi = I2C_ADDR_TDA985x_H >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .registers = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) /* callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .checkit = tda9873_checkit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .getrxsubchans = tda9873_getrxsubchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .setaudmode = tda9873_setaudmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .inputreg = TDA9873_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .name = "tda9874h/a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .insmodopt = &tda9874a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .addr_lo = I2C_ADDR_TDA9874 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .addr_hi = I2C_ADDR_TDA9874 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .flags = CHIP_NEED_CHECKMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .initialize = tda9874a_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .checkit = tda9874a_checkit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .getrxsubchans = tda9874a_getrxsubchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .setaudmode = tda9874a_setaudmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .name = "tda9875",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .insmodopt = &tda9875,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .addr_lo = I2C_ADDR_TDA9875 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .addr_hi = I2C_ADDR_TDA9875 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) /* callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .initialize = tda9875_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .checkit = tda9875_checkit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .volfunc = tda9875_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .bassfunc = tda9875_bass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .treblefunc = tda9875_treble,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .leftreg = TDA9875_MVL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .rightreg = TDA9875_MVR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .bassreg = TDA9875_MBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .treblereg = TDA9875_MTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .volinit = 58880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .name = "tda9850",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .insmodopt = &tda9850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .addr_lo = I2C_ADDR_TDA985x_L >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .addr_hi = I2C_ADDR_TDA985x_H >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .registers = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .getrxsubchans = tda985x_getrxsubchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .setaudmode = tda985x_setaudmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .name = "tda9855",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .insmodopt = &tda9855,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .addr_lo = I2C_ADDR_TDA985x_L >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .addr_hi = I2C_ADDR_TDA985x_H >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .registers = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .leftreg = TDA9855_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .rightreg = TDA9855_VR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .bassreg = TDA9855_BA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .treblereg = TDA9855_TR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .volfunc = tda9855_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .bassfunc = tda9855_bass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .treblefunc = tda9855_treble,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .getrxsubchans = tda985x_getrxsubchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .setaudmode = tda985x_setaudmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) 0x07, 0x10, 0x10, 0x03 }}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .name = "tea6300",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .insmodopt = &tea6300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .addr_lo = I2C_ADDR_TEA6300 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .addr_hi = I2C_ADDR_TEA6300 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .registers = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .leftreg = TEA6300_VR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .rightreg = TEA6300_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .bassreg = TEA6300_BA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .treblereg = TEA6300_TR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /* callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .volfunc = tea6300_shift10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .bassfunc = tea6300_shift12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .treblefunc = tea6300_shift12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .inputreg = TEA6300_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .inputmute = TEA6300_S_GMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .name = "tea6320",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .insmodopt = &tea6320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .addr_lo = I2C_ADDR_TEA6300 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .addr_hi = I2C_ADDR_TEA6300 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .registers = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .leftreg = TEA6320_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .rightreg = TEA6320_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .bassreg = TEA6320_BA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .treblereg = TEA6320_TR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) /* callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .initialize = tea6320_initialize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .volfunc = tea6320_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .bassfunc = tea6320_shift11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .treblefunc = tea6320_shift11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .inputreg = TEA6320_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .inputmute = TEA6300_S_GMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .name = "tea6420",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .insmodopt = &tea6420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .addr_lo = I2C_ADDR_TEA6420 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .addr_hi = I2C_ADDR_TEA6420 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .registers = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .flags = CHIP_HAS_INPUTSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .inputreg = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .inputmute = TEA6420_S_GMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .inputmask = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .name = "tda8425",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .insmodopt = &tda8425,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .addr_lo = I2C_ADDR_TDA8425 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .addr_hi = I2C_ADDR_TDA8425 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .registers = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .leftreg = TDA8425_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .rightreg = TDA8425_VR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .bassreg = TDA8425_BA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .treblereg = TDA8425_TR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .volfunc = tda8425_shift10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .bassfunc = tda8425_shift12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .treblefunc = tda8425_shift12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .setaudmode = tda8425_setaudmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .inputreg = TDA8425_S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .inputmute = TDA8425_S1_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .name = "pic16c54 (PV951)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .insmodopt = &pic16c54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .addr_lo = I2C_ADDR_PIC16C54 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .addr_hi = I2C_ADDR_PIC16C54>> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .registers = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .flags = CHIP_HAS_INPUTSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .inputreg = PIC16C54_REG_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) PIC16C54_MISC_SND_MUTE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .inputmute = PIC16C54_MISC_SND_MUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .name = "ta8874z",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .checkit = ta8874z_checkit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .insmodopt = &ta8874z,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .addr_lo = I2C_ADDR_TDA9840 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .addr_hi = I2C_ADDR_TDA9840 >> 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .registers = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) /* callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .getrxsubchans = ta8874z_getrxsubchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .setaudmode = ta8874z_setaudmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) { .name = NULL } /* EOF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static int tvaudio_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) struct CHIPSTATE *chip = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct CHIPDESC *desc = chip->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) case V4L2_CID_AUDIO_MUTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) chip->muted = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (chip->muted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) chip_write_masked(chip,desc->inputreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) desc->inputmap[chip->input],desc->inputmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) case V4L2_CID_AUDIO_VOLUME: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) u32 volume, balance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) u32 left, right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) volume = chip->volume->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) balance = chip->balance->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) left = (min(65536U - balance, 32768U) * volume) / 32768U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) right = (min(balance, 32768U) * volume) / 32768U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) chip_write(chip, desc->leftreg, desc->volfunc(left));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) chip_write(chip, desc->rightreg, desc->volfunc(right));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) case V4L2_CID_AUDIO_BASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) chip_write(chip, desc->bassreg, desc->bassfunc(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) case V4L2_CID_AUDIO_TREBLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) chip_write(chip, desc->treblereg, desc->treblefunc(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* video4linux interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static int tvaudio_s_radio(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) struct CHIPSTATE *chip = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) chip->radio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) /* del_timer(&chip->wt); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static int tvaudio_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) struct CHIPSTATE *chip = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) struct CHIPDESC *desc = chip->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (!(desc->flags & CHIP_HAS_INPUTSEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (input >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) /* There are four inputs: tuner, radio, extern and intern. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) chip->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (chip->muted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) chip_write_masked(chip, desc->inputreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) desc->inputmap[chip->input], desc->inputmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) static int tvaudio_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *vt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) struct CHIPSTATE *chip = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) struct CHIPDESC *desc = chip->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (!desc->setaudmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) if (chip->radio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) switch (vt->audmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) case V4L2_TUNER_MODE_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) case V4L2_TUNER_MODE_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) case V4L2_TUNER_MODE_LANG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) case V4L2_TUNER_MODE_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) case V4L2_TUNER_MODE_LANG1_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) chip->audmode = vt->audmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (chip->thread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) wake_up_process(chip->thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) desc->setaudmode(chip, vt->audmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static int tvaudio_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) struct CHIPSTATE *chip = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) struct CHIPDESC *desc = chip->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (!desc->getrxsubchans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (chip->radio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) vt->audmode = chip->audmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) vt->rxsubchans = desc->getrxsubchans(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) vt->capability |= V4L2_TUNER_CAP_STEREO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static int tvaudio_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) struct CHIPSTATE *chip = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) chip->radio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static int tvaudio_s_frequency(struct v4l2_subdev *sd, const struct v4l2_frequency *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) struct CHIPSTATE *chip = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) struct CHIPDESC *desc = chip->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* For chips that provide getrxsubchans and setaudmode, and doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) automatically follows the stereo carrier, a kthread is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) created to set the audio standard. In this case, when then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) the video channel is changed, tvaudio starts on MONO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) After waiting for 2 seconds, the kernel thread is called,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) to follow whatever audio standard is pointed by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) audio carrier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (chip->thread) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) desc->setaudmode(chip, V4L2_TUNER_MODE_MONO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) chip->prevmode = -1; /* reset previous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static int tvaudio_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) struct CHIPSTATE *chip = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) struct CHIPDESC *desc = chip->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) v4l2_info(sd, "Chip: %s\n", desc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) v4l2_ctrl_handler_log_status(&chip->hdl, sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static const struct v4l2_ctrl_ops tvaudio_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .s_ctrl = tvaudio_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static const struct v4l2_subdev_core_ops tvaudio_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .log_status = tvaudio_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static const struct v4l2_subdev_tuner_ops tvaudio_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .s_radio = tvaudio_s_radio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .s_frequency = tvaudio_s_frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .s_tuner = tvaudio_s_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .g_tuner = tvaudio_g_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static const struct v4l2_subdev_audio_ops tvaudio_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .s_routing = tvaudio_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) static const struct v4l2_subdev_video_ops tvaudio_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) .s_std = tvaudio_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static const struct v4l2_subdev_ops tvaudio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .core = &tvaudio_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .tuner = &tvaudio_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .audio = &tvaudio_audio_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .video = &tvaudio_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) /* i2c registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) static int tvaudio_probe(struct i2c_client *client, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) struct CHIPSTATE *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) struct CHIPDESC *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) if (debug) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) printk(KERN_INFO "tvaudio: known chips: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) for (desc = chiplist; desc->name != NULL; desc++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) printk(KERN_CONT "%s%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) (desc == chiplist) ? "" : ", ", desc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) printk(KERN_CONT "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) sd = &chip->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) v4l2_i2c_subdev_init(sd, client, &tvaudio_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* find description for the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) v4l2_dbg(1, debug, sd, "chip found @ 0x%x\n", client->addr<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) for (desc = chiplist; desc->name != NULL; desc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (0 == *(desc->insmodopt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (client->addr < desc->addr_lo ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) client->addr > desc->addr_hi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (desc->checkit && !desc->checkit(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (desc->name == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) v4l2_dbg(1, debug, sd, "no matching chip description found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) v4l2_info(sd, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (desc->flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) v4l2_dbg(1, debug, sd, "matches:%s%s%s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) /* fill required data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) strscpy(client->name, desc->name, I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) chip->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) chip->shadow.count = desc->registers+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) chip->prevmode = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) chip->audmode = V4L2_TUNER_MODE_LANG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) /* initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (desc->initialize != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) desc->initialize(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) chip_cmd(chip, "init", &desc->init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) v4l2_ctrl_handler_init(&chip->hdl, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if (desc->flags & CHIP_HAS_INPUTSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) v4l2_ctrl_new_std(&chip->hdl, &tvaudio_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (desc->flags & CHIP_HAS_VOLUME) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (!desc->volfunc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* This shouldn't be happen. Warn user, but keep working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) without volume controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) v4l2_info(sd, "volume callback undefined!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) desc->flags &= ~CHIP_HAS_VOLUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) chip->volume = v4l2_ctrl_new_std(&chip->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) &tvaudio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) 0, 65535, 65535 / 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) desc->volinit ? desc->volinit : 65535);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) chip->balance = v4l2_ctrl_new_std(&chip->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) &tvaudio_ctrl_ops, V4L2_CID_AUDIO_BALANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) 0, 65535, 65535 / 100, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) v4l2_ctrl_cluster(2, &chip->volume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (desc->flags & CHIP_HAS_BASSTREBLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (!desc->bassfunc || !desc->treblefunc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* This shouldn't be happen. Warn user, but keep working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) without bass/treble controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) v4l2_info(sd, "bass/treble callbacks undefined!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) desc->flags &= ~CHIP_HAS_BASSTREBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) v4l2_ctrl_new_std(&chip->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) &tvaudio_ctrl_ops, V4L2_CID_AUDIO_BASS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) 0, 65535, 65535 / 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) desc->bassinit ? desc->bassinit : 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) v4l2_ctrl_new_std(&chip->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) &tvaudio_ctrl_ops, V4L2_CID_AUDIO_TREBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) 0, 65535, 65535 / 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) desc->trebleinit ? desc->trebleinit : 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) sd->ctrl_handler = &chip->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (chip->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) int err = chip->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) v4l2_ctrl_handler_free(&chip->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* set controls to the default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) v4l2_ctrl_handler_setup(&chip->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) chip->thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) timer_setup(&chip->wt, chip_thread_wake, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (desc->flags & CHIP_NEED_CHECKMODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (!desc->getrxsubchans || !desc->setaudmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) /* This shouldn't be happen. Warn user, but keep working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) without kthread
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) v4l2_info(sd, "set/get mode callbacks undefined!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) /* start async thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) chip->thread = kthread_run(chip_thread, chip, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) client->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (IS_ERR(chip->thread)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) v4l2_warn(sd, "failed to create kthread\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) chip->thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) static int tvaudio_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) struct CHIPSTATE *chip = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) del_timer_sync(&chip->wt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (chip->thread) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* shutdown async thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) kthread_stop(chip->thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) chip->thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) v4l2_ctrl_handler_free(&chip->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) /* This driver supports many devices and the idea is to let the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) detect which device is present. So rather than listing all supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) devices here, we pretend to support a single, fake device type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) static const struct i2c_device_id tvaudio_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) { "tvaudio", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) MODULE_DEVICE_TABLE(i2c, tvaudio_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) static struct i2c_driver tvaudio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .name = "tvaudio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .probe = tvaudio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .remove = tvaudio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .id_table = tvaudio_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) module_i2c_driver(tvaudio_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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