^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tp2855 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TP2855_TEST_PATTERN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TP2855_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TP2855_LINK_FREQ_297M (297000000UL >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TP2855_LINK_FREQ_594M (594000000UL >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TP2855_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TP2855_BITS_PER_SAMPLE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TP2855_NAME "tp2855"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) enum{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CH_1=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CH_2=1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CH_3=2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) CH_4=3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CH_ALL=4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MIPI_PAGE=8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) STD_TVI, //TVI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) STD_HDA, //AHD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct tp2855_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct regval *global_reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 channel_reso[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct tp2855 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct tp2855_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool lost_video_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct task_struct *detect_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define to_tp2855(sd) container_of(sd, struct tp2855, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static __maybe_unused const struct regval common_setting_297M_720p_25fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {0x40, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {0xf5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {0x02, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {0x07, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {0x0b, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {0x0c, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {0x0d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {0x15, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {0x16, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {0x17, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0x18, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {0x19, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {0x1a, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0x1c, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {0x1d, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {0x20, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0x21, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0x22, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0x23, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #if TP2855_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0x2a, 0x3c}, //vi test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x2b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x2c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x2d, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x2e, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x30, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x31, 0xbb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x32, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x33, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x35, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x38, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x39, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x40, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x01, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x02, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x08, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x20, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x34, 0xe4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x14, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x15, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x25, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x26, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x27, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x29, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x33, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x33, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x14, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x14, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) // {0x23, 0x02}, //vi test ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) // {0x23, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static __maybe_unused const struct regval common_setting_594M_1080p_25fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x40, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0xf5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x02, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x07, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x0b, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x0c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x0d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x15, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x16, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x17, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x18, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x19, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x1a, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x1c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x1d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x20, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x21, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x22, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x23, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #if TP2855_TEST_PATTERN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x2a, 0x3c}, //vi test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x2b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x2c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x2d, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x2e, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x30, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x31, 0xbb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x32, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x33, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x35, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x38, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x39, 0x1C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x40, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x01, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x02, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x08, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x20, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x34, 0xe4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x15, 0x0C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x25, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x26, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x27, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x29, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x33, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x33, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x14, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x14, 0xb3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x14, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) // {0x23, 0x02}, //vi test ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) // {0x23, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct tp2855_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .global_reg_list = common_setting_594M_1080p_25fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .bpp = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .global_reg_list = common_setting_297M_720p_25fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .bpp = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) TP2855_LINK_FREQ_594M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) TP2855_LINK_FREQ_297M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* sensor register write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int tp2855_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) buf[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) usleep_range(300, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "tp2855 write reg(0x%x val:0x%x) failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int tp2855_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) const struct regval *regs, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) while (i < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = tp2855_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_err(&client->dev, "%s failed !\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* sensor register read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int tp2855_read_reg(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u8 buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) buf[0] = reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_err(&client->dev, "tp2855 read reg(0x%x) failed !\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int tp2855_get_reso_dist(const struct tp2855_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const struct tp2855_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) tp2855_find_best_fit(struct tp2855 *tp2855,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) for (i = 0; i < tp2855->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dist = tp2855_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) supported_modes[i].bus_fmt == framefmt->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int tp2855_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) const struct tp2855_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u64 pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mutex_lock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mode = tp2855_find_best_fit(tp2855, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) fmt->format.colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mutex_unlock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) __v4l2_ctrl_s_ctrl(tp2855->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * TP2855_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) __v4l2_ctrl_s_ctrl_int64(tp2855->pixel_rate, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_dbg(&tp2855->client->dev, "mipi_freq_idx %d\n", mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_dbg(&tp2855->client->dev, "pixel_rate %lld\n", pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mutex_unlock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int tp2855_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct i2c_client *client = tp2855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) const struct tp2855_mode *mode = tp2855->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mutex_lock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mutex_unlock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (fmt->pad < PAD_MAX && fmt->pad >= PAD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mutex_unlock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_dbg(&client->dev, "%s: %x %dx%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) __func__, fmt->format.code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) fmt->format.width, fmt->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int tp2855_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) code->code = tp2855->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int tp2855_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct i2c_client *client = tp2855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_dbg(&client->dev, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (fse->index >= tp2855->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int tp2855_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) cfg->type = V4L2_MBUS_CSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) cfg->flags = V4L2_MBUS_CSI2_4_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) V4L2_MBUS_CSI2_CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void tp2855_get_module_inf(struct tp2855 *tp2855,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) strlcpy(inf->base.sensor, TP2855_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) strlcpy(inf->base.module, tp2855->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) strlcpy(inf->base.lens, tp2855->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static long tp2855_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) tp2855_get_module_inf(tp2855, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static long tp2855_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = tp2855_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = tp2855_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int detect_thread_function(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct tp2855 *tp2855 = (struct tp2855 *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct i2c_client *client = tp2855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u8 detect_status = 0, reg26_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) bool lost_video = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) tp2855->lost_video_status = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) while (!kthread_should_stop()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (tp2855->power_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) tp2855_write_reg(client, 0x40, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) tp2855_read_reg(client, 0x01, &detect_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) tp2855_read_reg(client, 0x26, ®26_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) lost_video = (detect_status & 0x80) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (tp2855->lost_video_status != lost_video) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (lost_video) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) tp2855_write_reg(client, 0x26, (reg26_val & 0xfe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) tp2855_write_reg(client, 0x26, (reg26_val | 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) tp2855->lost_video_status = lost_video;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) tp2855_read_reg(client, 0x26, ®26_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_err(&client->dev, "tp2855 detect video lost status %d reg26_val %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) lost_video, reg26_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) schedule_timeout(msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int __maybe_unused detect_thread_start(struct tp2855 *tp2855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct i2c_client *client = tp2855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tp2855->detect_thread = kthread_create(detect_thread_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) tp2855, "tp2855_kthread");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (IS_ERR(tp2855->detect_thread)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_err(&client->dev, "kthread_create tp2855_kthread failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = PTR_ERR(tp2855->detect_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) tp2855->detect_thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) wake_up_process(tp2855->detect_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int __maybe_unused detect_thread_stop(struct tp2855 *tp2855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (tp2855->detect_thread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) kthread_stop(tp2855->detect_thread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) tp2855->detect_thread = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static int __tp2855_start_stream(struct tp2855 *tp2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int array_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct i2c_client *client = tp2855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (tp2855->cur_mode->global_reg_list == common_setting_594M_1080p_25fps_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) array_size = ARRAY_SIZE(common_setting_594M_1080p_25fps_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) } else if (tp2855->cur_mode->global_reg_list == common_setting_297M_720p_25fps_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) array_size = ARRAY_SIZE(common_setting_297M_720p_25fps_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = tp2855_write_array(tp2855->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) tp2855->cur_mode->global_reg_list, array_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(&client->dev, "__tp2855_start_stream global_reg_list faild");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) detect_thread_start(tp2855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int __tp2855_stop_stream(struct tp2855 *tp2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct i2c_client *client = tp2855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) tp2855_write_reg(client, 0x40, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) tp2855_write_reg(client, 0x23, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) detect_thread_stop(tp2855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int tp2855_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct i2c_client *client = tp2855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_dbg(&client->dev, "s_stream: %d. %dx%d\n", on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) tp2855->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) tp2855->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mutex_lock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (tp2855->streaming == on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) __tp2855_start_stream(tp2855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) __tp2855_stop_stream(tp2855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) tp2855->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mutex_unlock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int tp2855_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct i2c_client *client = tp2855->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) mutex_lock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (tp2855->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dev_dbg(&client->dev, "%s: on %d\n", __func__, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) tp2855->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) tp2855->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) mutex_unlock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int __tp2855_power_on(struct tp2855 *tp2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct device *dev = &tp2855->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_dbg(dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!IS_ERR_OR_NULL(tp2855->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = pinctrl_select_state(tp2855->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) tp2855->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_err(dev, "could not set pins. ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!IS_ERR(tp2855->power_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) gpiod_set_value_cansleep(tp2855->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) usleep_range(25*1000, 30*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) usleep_range(1500, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = clk_set_rate(tp2855->xvclk, TP2855_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_warn(dev, "Failed to set xvclk rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (clk_get_rate(tp2855->xvclk) != TP2855_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_warn(dev, "xvclk mismatched\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = clk_prepare_enable(tp2855->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (!IS_ERR(tp2855->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) gpiod_set_value_cansleep(tp2855->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) usleep_range(10*1000, 20*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) gpiod_set_value_cansleep(tp2855->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) usleep_range(10*1000, 20*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) usleep_range(10*1000, 20*1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!IS_ERR(tp2855->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) gpiod_set_value_cansleep(tp2855->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!IS_ERR_OR_NULL(tp2855->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pinctrl_select_state(tp2855->pinctrl, tp2855->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static void __tp2855_power_off(struct tp2855 *tp2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct device *dev = &tp2855->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_dbg(dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (!IS_ERR(tp2855->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) gpiod_set_value_cansleep(tp2855->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) clk_disable_unprepare(tp2855->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!IS_ERR_OR_NULL(tp2855->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = pinctrl_select_state(tp2855->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) tp2855->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (!IS_ERR(tp2855->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) gpiod_set_value_cansleep(tp2855->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int tp2855_initialize_controls(struct tp2855 *tp2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) const struct tp2855_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u64 pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) handler = &tp2855->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mode = tp2855->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = v4l2_ctrl_handler_init(handler, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) handler->lock = &tp2855->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) tp2855->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ARRAY_SIZE(link_freq_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) __v4l2_ctrl_s_ctrl(tp2855->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * TP2855_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) tp2855->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) V4L2_CID_PIXEL_RATE, 0, pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 1, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_err(&tp2855->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) tp2855->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int tp2855_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return __tp2855_power_on(tp2855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int tp2855_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) __tp2855_power_off(tp2855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int tp2855_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) const struct tp2855_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev_dbg(&tp2855->client->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) mutex_lock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mutex_unlock(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static const struct v4l2_subdev_internal_ops tp2855_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .open = tp2855_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static const struct v4l2_subdev_video_ops tp2855_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .s_stream = tp2855_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .g_mbus_config = tp2855_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static const struct v4l2_subdev_pad_ops tp2855_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .enum_mbus_code = tp2855_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .enum_frame_size = tp2855_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .get_fmt = tp2855_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .set_fmt = tp2855_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const struct v4l2_subdev_core_ops tp2855_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .s_power = tp2855_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .ioctl = tp2855_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .compat_ioctl32 = tp2855_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const struct v4l2_subdev_ops tp2855_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .core = &tp2855_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .video = &tp2855_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .pad = &tp2855_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static int check_chip_id(struct i2c_client *client){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) unsigned char chip_id = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) tp2855_read_reg(client, 0x34, &chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dev_err(dev, "chip_id : 0x%2x\n", chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (chip_id != 0x0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int tp2855_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct tp2855 *tp2855;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) __maybe_unused char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) tp2855 = devm_kzalloc(dev, sizeof(*tp2855), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (!tp2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) &tp2855->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) &tp2855->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) &tp2855->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) &tp2855->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dev_err(dev, "could not get %s!\n", RKMODULE_CAMERA_LENS_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) tp2855->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) tp2855->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) tp2855->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (IS_ERR(tp2855->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) tp2855->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (IS_ERR(tp2855->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) tp2855->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (IS_ERR(tp2855->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_warn(dev, "Failed to get power-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) tp2855->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (!IS_ERR(tp2855->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) tp2855->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) pinctrl_lookup_state(tp2855->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (IS_ERR(tp2855->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dev_info(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) tp2855->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) pinctrl_lookup_state(tp2855->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (IS_ERR(tp2855->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_info(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dev_info(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) mutex_init(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) sd = &tp2855->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) v4l2_i2c_subdev_init(sd, client, &tp2855_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ret = tp2855_initialize_controls(tp2855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) dev_err(dev, "Failed to initialize controls tp2855\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = __tp2855_power_on(tp2855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_err(dev, "Failed to power on tp2855\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ret = check_chip_id(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_err(dev, "Failed to check senosr id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) sd->internal_ops = &tp2855_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) tp2855->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ret = media_entity_pads_init(&sd->entity, 1, &tp2855->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (strcmp(tp2855->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) tp2855->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) TP2855_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) __tp2855_power_off(tp2855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) v4l2_ctrl_handler_free(&tp2855->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) mutex_destroy(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int tp2855_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct tp2855 *tp2855 = to_tp2855(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) v4l2_ctrl_handler_free(&tp2855->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) mutex_destroy(&tp2855->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) __tp2855_power_off(tp2855);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static const struct dev_pm_ops tp2855_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) SET_RUNTIME_PM_OPS(tp2855_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) tp2855_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static const struct of_device_id tp2855_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) { .compatible = "tp2855" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) MODULE_DEVICE_TABLE(of, tp2855_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static const struct i2c_device_id tp2855_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) { "tp2855", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static struct i2c_driver tp2855_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .name = TP2855_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .pm = &tp2855_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .of_match_table = of_match_ptr(tp2855_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .probe = &tp2855_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .remove = &tp2855_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .id_table = tp2855_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return i2c_add_driver(&tp2855_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) i2c_del_driver(&tp2855_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) MODULE_AUTHOR("Vicent Chi <vicent.chi@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) MODULE_DESCRIPTION("tp2855 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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