^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * ths8200 - Texas Instruments THS8200 video encoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2013 Cisco Systems, Inc. and/or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you may redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This program is distributed .as is. WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "ths8200_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_PARM_DESC(debug, "debug level (0-2)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_DESCRIPTION("Texas Instruments THS8200 video encoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MODULE_AUTHOR("Martin Bugge <martin.bugge@cisco.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct ths8200_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) uint8_t chip_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Is the ths8200 powered on? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct v4l2_dv_timings dv_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct v4l2_dv_timings_cap ths8200_timings_cap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .type = V4L2_DV_BT_656_1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* keep this initialization for compatibility with GCC < 4.4.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .reserved = { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1080, 25000000, 148500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) V4L2_DV_BT_STD_CEA861, V4L2_DV_BT_CAP_PROGRESSIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline struct ths8200_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return container_of(sd, struct ths8200_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline unsigned htotal(const struct v4l2_bt_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return V4L2_DV_BT_FRAME_WIDTH(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline unsigned vtotal(const struct v4l2_bt_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return V4L2_DV_BT_FRAME_HEIGHT(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int ths8200_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) v4l2_err(sd, "I2C Write Problem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * and then the value-mask (to be OR-ed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uint8_t clr_mask, uint8_t val_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int ths8200_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) reg->val = ths8200_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int ths8200_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int ths8200_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct ths8200_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) v4l2_info(sd, "----- Chip status -----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) v4l2_info(sd, "version: %u\n", state->chip_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) v4l2_info(sd, "test pattern: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (reg_03 & 0x20) ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) v4l2_info(sd, "format: %ux%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) v4l2_print_dv_timings(sd->name, "Configured format:",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) &state->dv_timings, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Power up/down ths8200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int ths8200_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct ths8200_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) state->power_on = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Power up/down - leave in reset state until input video is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct v4l2_subdev_core_ops ths8200_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .log_status = ths8200_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .s_power = ths8200_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .g_register = ths8200_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .s_register = ths8200_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * V4L2 subdev video operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int ths8200_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct ths8200_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (enable && !state->power_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ths8200_s_power(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) (enable ? 0x01 : 0x00));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) v4l2_dbg(1, debug, sd, "%s: %sable\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __func__, (enable ? "en" : "dis"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void ths8200_core_init(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* setup clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /**** Data path control (DATA) ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Set FSADJ 700 mV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * bypass 422-444 interpolation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * input format 30 bit RGB444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ths8200_write(sd, THS8200_DATA_CNTL, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* DTG Mode (Video blocked during blanking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * VESA slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ths8200_write(sd, THS8200_DTG1_MODE, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /**** Display Timing Generator Control, Part 1 (DTG1). ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Disable embedded syncs on the output by setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * the amplitude to zero for all channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) uint8_t polarity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) uint16_t line_start_active_video = (bt->vsync + bt->vbackporch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) uint16_t line_start_front_porch = (vtotal(bt) - bt->vfrontporch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*** System ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Set chip in reset while it is configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ths8200_s_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* configure video output timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Zero for progressive scan formats.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!bt->interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Distance from leading edge of h sync to start of active video.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * MSB in 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (bt->hbackporch + bt->hsync) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Zero for SDTV-mode. MSB in 0x2b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * MSB for dtg1_spec(d/e/h). See comment for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * corresponding LSB registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ((bt->hbackporch + bt->hsync) & 0x100) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* h front porch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ((bt->hfrontporch) & 0x700) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Half the line length. Used to calculate SDTV line types. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ((htotal(bt)/2) >> 8) & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Total pixels per line (ex. 720p: 1650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Frame height and field height */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Field height should be programmed higher than frame_size for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * progressive scan formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ((vtotal(bt) >> 4) & 0xf0) + 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Should be programmed higher than frame_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * for progressive formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!bt->interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /**** Display Timing Generator Control, Part 2 (DTG2). ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Set breakpoint line numbers and types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * THS8200 generates line types with different properties. A line type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * that sets all the RGB-outputs to zero is used in the blanking areas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * while a line type that enable the RGB-outputs is used in active video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * area. The line numbers for start of active video, start of front
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * porch and after the last line in the frame must be set with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * corresponding line types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Line types:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * 0x9 - Full normal sync pulse: Blocks data when dtg1_pass is off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Used in blanking area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * 0x0 - Active video: Video data is always passed. Used in active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * video area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ((line_start_active_video >> 4) & 0x70) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ((line_start_front_porch >> 8) & 0x07));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* line types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* h sync width transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) (bt->hsync >> 2) & 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* The pixel value h sync is asserted on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) (htotal(bt) >> 8) & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* v sync width transmitted (must add 1 to get correct output) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync + 1) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ((bt->vsync + 1) >> 2) & 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* The pixel value v sync is asserted on (must add 1 to get correct output) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ((vtotal(bt) + 1) >> 8) & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* For progressive video vlength2 must be set to all 0 and vdly2 must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * be set to all 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Internal delay factors to synchronize the sync pulses and the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Experimental values delays (hor 0, ver 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Polarity of received and transmitted sync signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (bt->polarities & V4L2_DV_HSYNC_POS_POL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) polarity |= 0x01; /* HS_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) polarity |= 0x08; /* HS_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (bt->polarities & V4L2_DV_VSYNC_POS_POL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) polarity |= 0x02; /* VS_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) polarity |= 0x10; /* VS_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* RGB mode, no embedded timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Timing of video input bus is derived from HS, VS, and FID dedicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ths8200_write(sd, THS8200_DTG2_CNTL, 0x44 | polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* leave reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ths8200_s_stream(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "horizontal: front porch %d, back porch %d, sync %d\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "vertical: sync %d\n", __func__, htotal(bt), vtotal(bt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) polarity, bt->hfrontporch, bt->hbackporch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) bt->hsync, bt->vsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int ths8200_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct ths8200_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!v4l2_valid_dv_timings(timings, &ths8200_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) NULL, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!v4l2_find_dv_timings_cap(timings, &ths8200_timings_cap, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) NULL, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) v4l2_dbg(1, debug, sd, "Unsupported format\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* save timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) state->dv_timings = *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ths8200_setup(sd, &timings->bt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int ths8200_g_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct ths8200_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *timings = state->dv_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int ths8200_enum_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct v4l2_enum_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (timings->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return v4l2_enum_dv_timings_cap(timings, &ths8200_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int ths8200_dv_timings_cap(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct v4l2_dv_timings_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (cap->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *cap = ths8200_timings_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Specific video subsystem operation handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const struct v4l2_subdev_video_ops ths8200_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .s_stream = ths8200_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .s_dv_timings = ths8200_s_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .g_dv_timings = ths8200_g_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct v4l2_subdev_pad_ops ths8200_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .enum_dv_timings = ths8200_enum_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .dv_timings_cap = ths8200_dv_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* V4L2 top level operation handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct v4l2_subdev_ops ths8200_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .core = &ths8200_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .video = &ths8200_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .pad = &ths8200_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int ths8200_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct ths8200_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) v4l2_i2c_subdev_init(sd, client, &ths8200_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) state->chip_version = ths8200_read(sd, THS8200_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ths8200_core_init(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) error = v4l2_async_register_subdev(&state->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int ths8200_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct ths8200_state *decoder = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ths8200_s_power(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) v4l2_async_unregister_subdev(&decoder->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const struct i2c_device_id ths8200_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { "ths8200", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MODULE_DEVICE_TABLE(i2c, ths8200_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct of_device_id ths8200_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { .compatible = "ti,ths8200", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_DEVICE_TABLE(of, ths8200_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static struct i2c_driver ths8200_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .name = "ths8200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .of_match_table = of_match_ptr(ths8200_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .probe_new = ths8200_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .remove = ths8200_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .id_table = ths8200_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) module_i2c_driver(ths8200_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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